JPS5618439A - Semiconductor device consisting of different ic - Google Patents

Semiconductor device consisting of different ic

Info

Publication number
JPS5618439A
JPS5618439A JP9452079A JP9452079A JPS5618439A JP S5618439 A JPS5618439 A JP S5618439A JP 9452079 A JP9452079 A JP 9452079A JP 9452079 A JP9452079 A JP 9452079A JP S5618439 A JPS5618439 A JP S5618439A
Authority
JP
Japan
Prior art keywords
different
ics
defective
oblong
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9452079A
Other languages
Japanese (ja)
Inventor
Toshio Fujita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9452079A priority Critical patent/JPS5618439A/en
Publication of JPS5618439A publication Critical patent/JPS5618439A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PURPOSE:To obtain an improved yield by a method wherein a size and a shape of the IC of a component element are determined in a way that a unit, having two or more of ICs performing different functions arranged on a chip with prescribed functions, can be cut into an oblong in general appearance. CONSTITUTION:In the case of 1 chip microcomputer, a prescribed function is obtained by having four different IC combinations: They are a central processing unit called microprocessor and its associated section (MPU), and exclusive-for-read- out memory (ROM), a write-in and read-out memory (RWM) and an interface adapter (PIA) to be used with peripheral units. These four different ICs are arranged on the same wafer so that the whole of them will make an oblong shape when combined. In the case when there is a defective IC, all the ICs including the defective one are scribed in order to make an oblong shape in general appearance. As a result, an automatic wire-connection using a machine can be performed, thereby enabling to have an improved yield.
JP9452079A 1979-07-25 1979-07-25 Semiconductor device consisting of different ic Pending JPS5618439A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9452079A JPS5618439A (en) 1979-07-25 1979-07-25 Semiconductor device consisting of different ic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9452079A JPS5618439A (en) 1979-07-25 1979-07-25 Semiconductor device consisting of different ic

Publications (1)

Publication Number Publication Date
JPS5618439A true JPS5618439A (en) 1981-02-21

Family

ID=14112597

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9452079A Pending JPS5618439A (en) 1979-07-25 1979-07-25 Semiconductor device consisting of different ic

Country Status (1)

Country Link
JP (1) JPS5618439A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63220542A (en) * 1987-03-09 1988-09-13 Nec Corp Manufacture of semiconductor device
JPS63293852A (en) * 1987-05-26 1988-11-30 Nec Corp Master slice integrated circuit
JPH04218943A (en) * 1991-04-19 1992-08-10 Toshiba Corp Manufacture of large-scale integrated circuit device
EP0516185A2 (en) * 1987-04-22 1992-12-02 Hitachi, Ltd. Wafer-scale semiconductor integrated circuit device
US5309011A (en) * 1987-04-22 1994-05-03 Hitachi, Ltd. Wafer scale or full wafer memory system, packaging method thereof, and wafer processing method employed therein
JP2010219189A (en) * 2009-03-16 2010-09-30 Fujitsu Semiconductor Ltd Production method and design device of semiconductor device
JP5956708B1 (en) * 2015-11-30 2016-07-27 株式会社ＰＥＺＹ Ｃｏｍｐｕｔｉｎｇ DIE AND PACKAGE, DIE MANUFACTURING METHOD, AND PACKAGE GENERATION METHOD
WO2017094092A1 (en) * 2015-11-30 2017-06-08 株式会社ＰＥＺＹ Ｃｏｍｐｕｔｉｎｇ Die and package

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63220542A (en) * 1987-03-09 1988-09-13 Nec Corp Manufacture of semiconductor device
EP0516185A2 (en) * 1987-04-22 1992-12-02 Hitachi, Ltd. Wafer-scale semiconductor integrated circuit device
US5309011A (en) * 1987-04-22 1994-05-03 Hitachi, Ltd. Wafer scale or full wafer memory system, packaging method thereof, and wafer processing method employed therein
JPS63293852A (en) * 1987-05-26 1988-11-30 Nec Corp Master slice integrated circuit
JPH04218943A (en) * 1991-04-19 1992-08-10 Toshiba Corp Manufacture of large-scale integrated circuit device
JP2010219189A (en) * 2009-03-16 2010-09-30 Fujitsu Semiconductor Ltd Production method and design device of semiconductor device
JP5956708B1 (en) * 2015-11-30 2016-07-27 株式会社ＰＥＺＹ Ｃｏｍｐｕｔｉｎｇ DIE AND PACKAGE, DIE MANUFACTURING METHOD, AND PACKAGE GENERATION METHOD
WO2017094091A1 (en) * 2015-11-30 2017-06-08 株式会社ＰＥＺＹ Ｃｏｍｐｕｔｉｎｇ Die and package, and manufacturing method for die and producing method for package
WO2017094092A1 (en) * 2015-11-30 2017-06-08 株式会社ＰＥＺＹ Ｃｏｍｐｕｔｉｎｇ Die and package
US10691634B2 (en) 2015-11-30 2020-06-23 Pezy Computing K.K. Die and package
US10818638B2 (en) 2015-11-30 2020-10-27 Pezy Computing K.K. Die and package

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