KR960003003B1 - Vlsi semiconductor device - Google Patents

Abstract

The device is manufactured by a layout method capable of patterning a fine portion using a photolithography process. In the same pitch, a space between patterns in higher step difference portion of a semiconductor is larger than that between patterns in lower step difference portion, and a pattern width in higher step difference portion is smaller than that in lower step difference portion. Pref. the pattern is one of conduction wire and metallic wiring. Also the higher step difference portion is a field region of the semiconductor, and the lower step difference portion is its active region.

Description

Ultra-Integrated Semiconductor Device

1 shows the arrangement of a conventional mask rom,

2 and 3 show partial cross-sectional views of FIG.

4 shows another example of a conventional mask ROM cell layout.

5 is a partial cross-sectional view of FIG. 4,

6 shows another example of a conventional mask ROM cell layout.

7 shows a partial cross-sectional view of FIG.

8 shows the layout of the mask rom of the present invention,

9 and 10 show partial cross-sectional views of FIG.

Figure 11 shows an embodiment of the present invention,

12 shows another embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to an ultra-high density semiconductor device manufactured by a layout method capable of patterning fine portions using a photolithography process.

As semiconductor devices become more integrated, the pitch of the conductive and metal wiring of the semiconductor device decreases, and the stepper when the conductive and metal wiring pitch decreases below the stepper limit of the photoliithography process. Depth of Focus (DOF) is based on the active area of the semiconductor device, so conductive and metal wires formed on the field area cannot be accurately patterned due to the difference in the depth of focus and cause a defect such as a bridge. Done.

1 and 2 and 3 show the layout and vertical structure of a conventional mask ROM cell.

FIG. 1 is a layout of a conventional mask ROM cell, in which an active region 1 extending along a longitudinal axis and a field region 2 for electrically isolating it are shown, and a plurality of gate electrodes 3 extending along the horizontal axis are electrically connected to each other. The contact region 4 and the metallization 5 for connecting the cell arrays are respectively shown.

2 and 3 are vertical structures when cut along the lines AA ′ and BB ′ of the layout of FIG. 1, and FIGS. 1 and 3 show gate electrodes 23 formed on the active region 24. Width L1 and the distance S1 between the gate electrode and the gate electrode are laid out to be equal to the width L2 of the gate electrode 23 formed on the field region 21 and the distance S2 between the gate electrodes. have.

Next, FIGS. 4 to 7 show another example of the conventional mask ROM layout, and FIG. 4 shows an active region 31 extending longitudinally and a field region 32 for electrically isolating it. A plurality of gate electrodes 33 are shown extending along the horizontal axis.

FIG. 5 is a vertical structure diagram taken along the line A-A 'of FIG. 4, wherein a gate electrode 33 is formed on the semiconductor substrate 30 divided into the active region and the field region 32. FIG. Reference numeral 35 denotes a photoresist used for patterning the gate electrode 33. Reference numeral D1 denotes the depth of focus of the stepper from the photoresist 35 to the gate electrode on the active region, and D2 denotes the depth of focus from the photoresist 35 to the gate electrode on the field region.

6 shows an active region 41 extending along the longitudinal axis and a field region 42 for electrically isolating it, and a plurality of metal wires 45 extending along the horizontal axis.

FIG. 7 is a vertical structural view taken along line AA ′ of FIG. 6, wherein an interlayer insulating film 44 and a metal wiring layer 45 are formed on a semiconductor substrate 40 divided into an active region and a field region 42. have. Here, reference numeral 46 denotes a photoresist used for patterning the gate electrode 43. Reference numeral D3 denotes the depth of focus of the stepper from the photoresist 46 to the active region, and D4 denotes the depth of focus from the photoresist 46 to the field region.

In FIG. 4 and FIG. 6, the spacing S1 between the gate electrodes 33 extending along the horizontal axis and the spacing S2 between the metal wirings 45 are identically arranged in both the active region and the field region. have.

In the conventional layout method, when the gate electrode and the metal wiring are formed on the active region and the field region as described above, the spacing between the gate electrodes and the metal wirings is equally laid out, thus, between the gate electrodes and the metal wirings. If the spacing is reduced below the photolithography limit, the pattern formed in the field area with high step height may not be accurately formed due to the difference in the depth of focus of the stepper due to the step difference between the active area and the field area during patterning by the photolithography process. Couplings, etc., cause a problem of lowering the reliability of the semiconductor device.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a pattern layout method of an ultra-high density semiconductor device with high reliability and ultra-fine photo resource. In order to achieve the above object, the present invention is a super-high density semiconductor device, in which the interval between the patterns of the high stepped portion of the semiconductor device in the same pitch is larger than the interval between the patterns of the low stepped portion, the semiconductor The device is characterized in that the width of the pattern of the portion having the high step is laid out smaller than the width of the pattern of the portion having the low step.

Next, a pattern layout method of a semiconductor according to the present invention will be described with reference to FIG.

8 shows a layout of a NAND type mask romsel array, in which an active region 51 extending longitudinally, a field region 52 for electrically isolating it, a plurality of gate electrodes 53 extending horizontally, It is composed of a contact region 54 and a metal wiring 55 for electrically forming a cell array.

9 and 10 show the vertical structures when the layout of FIG. 8 is cut along the lines A-A 'and B-B' in the figure. In FIGS. 9 and 10, reference numeral 60 denotes a semiconductor substrate, 61 an active region, 62 a field region, 63 a gate insulating film, and 64 a gate electrode.

As shown in FIG. 8 and FIG. 10, the width L4 of the gate electrodes 53 and 64 on the field region is laid out smaller than the width L3 of the gate electrodes 53 and 64 on the active region. The spacing S4 between the gate electrodes 53 and 64 on the field region is laid out larger than the spacing S3 between the gate electrodes 53 and 64 on the active region.

By laying out the gate electrode pattern as described above, the pattern on the field region caused by the difference in the depth of focus of the stepper during the photolithography process caused by the step between the active regions 51 and 61 and the field regions 52 and 62. Since it is possible to prevent the formation of bridges between the liver, there is an advantage that can increase the reliability of the semiconductor device.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

11 and 12 show partial plan views of FIG. 8, FIG. 11 shows a gate electrode pattern layout, and FIG. 12 shows a metal wiring pattern layout.

In FIG. 11, an active region 71 is shown, a field region 72, and a gate electrode made of polysilicon or polycide is indicated by 73.

When the pitch of the gate electrode pattern is 1 mu m, the photoresist is applied to a thickness of 1.17 mu m using a g-line stepper having an exposure wavelength of 430 nm to 440 nm, and the exposure time is set to 340 mu m to 400 mu m. When the photolithography process is performed with a lamp intensity of 49 W, the line dimension of the gate electrode pattern and the space dimension between the gate electrode patterns are the same on the mask L5 = L6 = 0.5 µm. And S5 = S6 = 0.5㎛, with the depth of focus margin usually being ± 0.3. Here, the roughness of the surface of the wafer itself may be large, or there may be a difference in distance between the lens of the stepper and the wafer, or there may be a difference in the thickness of the photoresist at the wafer, or at each part of the wafer, or the lamp intensity of the stepper may change. In this case, a defect such as a bridge occurs with the depth of focus margin (± 0.3).

Accordingly, as shown in FIG. 11, the line spacing between the gate electrode patterns on the active region 71 and the space spacing between the gate electrode patterns are all equally 0.5 μm, and the gate electrodes on the field region 72 are equally laid out. If the space spacing between the patterns is 0.55 占 퐉 and the line spacing of the gate electrode pattern is 0.45 占 퐉, the depth of focus margin is ± 0.4, resulting in an additional margin of ± 0.1 for the various variables in the above photoresist process. Therefore, the photoresist process can be performed on the field area with high step height without defects such as bridges.

FIG. 12 shows a layout of the metal wiring, where the active region is indicated by reference numeral 81, the field region by reference numeral 82, and the metal wiring composed of aluminum or barrier metal is indicated by reference numeral 83.

When the pitch of the metal wiring pattern is 1.2 占 퐉, the photoresist is applied to a thickness of 1.42 占 퐉 using a g-line stepper having an exposure wavelength of 430 nm to 440 nm, and the exposure time is set to 340 ㎱ to 400 ㎱ and the stepper lamp When the photolithography process is performed with the intensity of 492W, the space spacing between the metal wiring patterns and the line spacing between the metal wiring patterns is the same as L7 = L8 = 0.6 μm and S7 = S8 = 0.6 μm on the mask. Depth margin is typically ± 0.3.

Here too, the roughness of the surface of the wafer itself may be large, or there may be a difference in distance between the lens of the stepper and the wafer, or there may be a difference in the thickness of the photoresist on each wafer or each part of the wafer, or the lamp intensity of the stepper may change. In this case, a defect such as a bridge occurs with the depth of focus margin (± 0.3).

Accordingly, as shown in FIG. 12, the line spacing between the metal wiring pattern on the active region 81 and the space spacing between the metal wiring patterns are all laid out at 0.6 占 퐉, and the metal wiring pattern on the field region 82 is laid out. If the line spacing is 0.55㎛, and the space spacing between the metal wiring patterns is 0.65㎛, the depth of focus becomes ± 0.4, resulting in a margin of ± 0.1 for the variable that may occur during the photolithography process. The photolithography process can be performed without defects such as bridges and the like on the field region.

As described above, according to the present invention, the lithography limitation of the stepper can be overcome in the photolithography process during the semiconductor device manufacturing process. As a result, the margin is increased during the photolithography process, thereby improving the reliability of the chip and reducing the defective rate. In addition, since the pattern size can be reduced to a dimension capable of photolithography, the overall chip size can be reduced.

Claims (4)

Within the same pitch, the gap between the patterns of the high stepped portion of the semiconductor device is laid out larger than the gap between the patterns of the low stepped portion, and the width of the pattern of the high stepped portion of the semiconductor device is An ultra-high density semiconductor device, characterized in that the layout is smaller than the width of the pattern. The ultra-high density semiconductor device according to claim 1, wherein the pattern is any one of a conductive line and a metal wiring of the semiconductor device. The ultra-high density semiconductor device according to claim 1, wherein the high step portion is on a field region of the semiconductor device. The ultra-high density semiconductor device according to claim 1, wherein the low step portion is on an active region of the semiconductor device.