CN113589638A - Mask layout and semiconductor structure - Google Patents

Mask layout and semiconductor structure Download PDF

Info

Publication number
CN113589638A
CN113589638A CN202010364447.2A CN202010364447A CN113589638A CN 113589638 A CN113589638 A CN 113589638A CN 202010364447 A CN202010364447 A CN 202010364447A CN 113589638 A CN113589638 A CN 113589638A
Authority
CN
China
Prior art keywords
sub
pattern
interconnection layer
layer
graph
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202010364447.2A
Other languages
Chinese (zh)
Other versions
CN113589638B (en
Inventor
杨青
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN202010364447.2A priority Critical patent/CN113589638B/en
Publication of CN113589638A publication Critical patent/CN113589638A/en
Application granted granted Critical
Publication of CN113589638B publication Critical patent/CN113589638B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

A reticle layout and a semiconductor structure, the reticle layout comprising: the first mask layout comprises a first sub-graph, a second sub-graph and a third sub-graph which are positioned on one side of the first sub-graph; the second sub-graph and the third sub-graph are positioned in the same layout, and the first sub-graph extends along the first direction; the second sub-pattern extends along a second direction, the first direction is perpendicular to the second direction, and the extending direction of the second sub-interconnection layer is intersected with the extending direction of the first sub-interconnection layer; in the first direction, the third sub-pattern is positioned on at least one side of the second sub-pattern, and the third sub-pattern is connected with the end part of the second sub-pattern close to one side of the first sub-pattern. In the exposure process, the length of the formed second sub-interconnection layer in the second direction is longer, correspondingly, the formed contact plug is easily formed on the second sub-interconnection layer, and the contact plug is in good contact with the second sub-interconnection layer, so that the electrical property of the semiconductor structure is improved.

Description

Mask layout and semiconductor structure
Technical Field
The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a mask layout and a semiconductor structure.
Background
Before the photolithography process is started, the wafer layout is copied to the reticle by a specific device, and then the pattern on the reticle is copied to the physical wafer used for production by the photolithography device generating light with a specific wavelength (for example, 248 nm ultraviolet light).
Photolithography (Lithograph) is a key process technology for implementing integrated circuit patterns. In the photolithography technique, a photosensitive material (photoresist) is coated on a thin film of a substrate, light of a wavelength band corresponding to the photosensitive characteristic of the photoresist is adopted, the light is irradiated to the surface of the photoresist through a mask plate with a specific pattern, and a photoresist pattern corresponding to the pattern on the mask plate is formed after development. In the subsequent process of the integrated circuit, the photoresist pattern is used as a barrier layer to selectively etch the film below the photoresist pattern, so that the pattern on the mask plate can be completely transferred to the film on the substrate. As the line width of the integrated circuit pattern becomes thinner, the imaging resolution of the photoresist is required to be higher, and the imaging resolution of the photoresist is inversely proportional to the wavelength of the exposure light source, and therefore, reducing the wavelength of the exposure light source becomes a main approach for realizing a fine line width pattern.
With the continuous improvement of the integration level of an integrated circuit, the integrated circuit is rapidly developed towards submicron and deep submicron directions, the line width of a pattern of the integrated circuit is thinner and thinner, the original pattern of one-time exposure needs to be realized through multiple times of exposure, which puts higher requirements on the precision of a semiconductor process, and in a multilayer structure, the slight deviation between an upper layer pattern and a lower layer pattern can cause the final semiconductor structure to have the defect of bridging or breaking.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a mask layout and a semiconductor structure, and improves the electrical performance of the semiconductor structure.
In order to solve the above problem, an embodiment of the present invention provides a reticle layout, including: the first mask layout comprises a plurality of interconnection layer graphs, and the interconnection layer graphs comprise a first sub graph, a second sub graph and a third sub graph which are positioned on one side of the first sub graph; the second sub-graph and the third sub-graph are positioned in the same layout, the first sub-graph, the second sub-graph and the third sub-graph are arranged at intervals, and the first sub-graph extends along a first direction; the second sub-pattern extends along a second direction, the first direction is perpendicular to the second direction, and the extending direction of the second sub-pattern is intersected with the extending direction of the first sub-pattern; in the first direction, the third sub-graph is positioned on at least one side of the second sub-graph, and the third sub-graph is connected with the end part, close to one side of the first sub-graph, of the second sub-graph; and the second mask layout comprises a plurality of hole patterns, wherein the hole patterns are positioned in the area where the interconnection layer patterns are positioned, and in the second sub-pattern, the hole patterns are positioned at the end part of the second sub-pattern close to one side of the first sub-pattern.
Optionally, the interconnect layer pattern further includes: and the fourth sub-pattern is spaced from the second sub-pattern in the first direction and spaced from the first sub-pattern in the second direction, and the fourth sub-pattern is positioned on the side, back to the third sub-pattern, of the second sub-pattern.
Optionally, in the first direction, the third sub-pattern is located on both sides of the second sub-pattern; the interconnect layer pattern further includes: a fourth sub-pattern located at one side of the second sub-pattern and spaced from the third sub-pattern in the first direction, the fourth sub-pattern being spaced from the first sub-pattern in the second direction; and the fifth sub-graph is positioned on the other side of the second sub-graph and is spaced from the third sub-graph in the first direction, and the fifth sub-graph is spaced from the first sub-graph in the second direction.
Optionally, in the first direction, a distance from the second sub-pattern to the fourth sub-pattern is less than or equal to 30 nanometers; in the second direction, the distance between the fourth sub-pattern and the first sub-pattern is greater than 50 nanometers and less than 60 nanometers.
Optionally, in the first direction, the length of the third subpattern is at least 96 nanometers.
Optionally, the interconnect layer pattern further includes: a fifth sub-pattern, located on a side of the second sub-pattern facing away from the fourth sub-pattern in the first direction and spaced from the third sub-pattern, and spaced from the first sub-pattern in the second direction; in the first direction, the distance from the third subpattern to the fifth subpattern is greater than or equal to 24 nanometers.
Optionally, in the first direction, the length of the third sub-pattern is greater than or equal to 10 nm.
Optionally, in the first direction, a distance from the fourth sub-pattern to an adjacent third sub-pattern is greater than or equal to 20 nm; the distance from the fifth sub-pattern to the adjacent third sub-pattern is greater than or equal to 20 nanometers.
Optionally, in the second direction, a distance from the first sub-pattern to the second sub-pattern is less than or equal to 50 nm.
Optionally, in the second direction, the hole pattern in the second sub-pattern has a first edge facing the first sub-pattern, the second sub-pattern has a second edge facing the second sub-pattern, and a distance from the first edge to the second edge is greater than or equal to 6 nm.
Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate; an interconnect layer on the substrate, the interconnect layer comprising: a first sub-interconnect layer extending in a first direction; the second sub-interconnection layer is positioned on the substrate on one side of the first sub-interconnection layer, the second sub-interconnection layer and the first sub-interconnection layer are arranged at intervals, the second sub-interconnection layer extends along a second direction, the first direction is perpendicular to the second direction, and the extending direction of the second sub-interconnection layer is intersected with the extending direction of the first sub-interconnection layer; a third sub-interconnection layer located on at least one side of the second sub-interconnection layer in the first direction, and connected to an end portion of the second sub-interconnection layer on a side close to the first sub-interconnection layer; and a plurality of contact plugs which are positioned on the interconnection layer and are in contact with the top of a second sub-interconnection layer, wherein on the second sub-interconnection layer, the contact plugs are positioned at the end part of the second sub-interconnection layer close to one side of the first sub-interconnection layer.
Optionally, the interconnect layer further includes: and the fourth sub-interconnection layer is positioned on the substrate, is spaced from the second sub-interconnection layer in the first direction and is spaced from the first sub-interconnection layer in the second direction, and is positioned on one side, facing away from the third sub-interconnection layer, of the second sub-interconnection layer.
Optionally, in the first direction, the third sub-interconnection layers are located on two sides of the second sub-interconnection layer; the interconnect layer pattern further includes: a fourth sub-interconnection layer on the substrate on one side of the second sub-interconnection layer, spaced from the third sub-interconnection layer in the first direction, the fourth sub-interconnection layer being spaced from the first sub-interconnection layer in the second direction; a fifth sub-interconnection layer on the substrate on the other side of the second sub-interconnection layer, spaced from the third sub-interconnection layer in the first direction, the fifth sub-interconnection layer being spaced from the first sub-interconnection layer in the second direction.
Optionally, in the first direction, a distance from the second sub-interconnect layer to the fourth sub-interconnect layer is less than or equal to 30 nanometers; the distance from the fourth sub-interconnection layer to the first sub-interconnection layer is greater than 50 nanometers and less than 60 nanometers.
Optionally, in the first direction, the length of the third sub-interconnect layer is at least 96 nm.
Optionally, the interconnect layer further includes: a fifth sub-interconnection layer, located on a side of the second sub-interconnection layer facing away from the fourth sub-interconnection layer in the first direction, and spaced apart from the third sub-interconnection layer, and spaced apart from the first sub-interconnection layer in the second direction; a distance from the third sub-interconnect layer to the fifth sub-interconnect layer in the first direction is greater than or equal to 24 nanometers.
Optionally, in the first direction, a length of the third sub-interconnection layer is greater than or equal to 10 nanometers.
Optionally, in the first direction, a distance from the fourth sub-interconnect layer to an adjacent third sub-interconnect layer is greater than or equal to 20 nanometers; the distance from the fifth sub-interconnect layer to an adjacent third sub-interconnect layer is greater than or equal to 20 nanometers.
Optionally, in the second direction, a distance from the first sub-interconnect layer to the second sub-interconnect layer is less than or equal to 50 nanometers.
Optionally, in the second direction, the second sub-interconnect layer has a first face facing the second sub-interconnect layer, and a distance from a bottom of the contact plug to the first face is greater than or equal to 6 nm.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
the embodiment of the invention provides a mask layout, wherein the second sub-pattern and the third sub-pattern are located in the same layout, and in the same step, a first opening (not shown in the figure) is formed by exposure according to the second sub-pattern, a second opening is formed by exposure according to the third sub-pattern, conductive materials are filled in the first opening and the second opening, a second sub-interconnection layer is respectively formed in the first opening, and a third sub-interconnection layer is formed in the second opening, wherein the hole pattern is used for forming a contact plug connected with the second interconnection layer, and in the second sub-pattern, the hole pattern is located at an end part of the second sub-pattern close to one side of the first sub-pattern. In the embodiment of the invention, the third sub-pattern is connected with the second sub-pattern, the third sub-pattern and the second sub-pattern are positioned in the same layout, and the third sub-pattern is connected with one end of the second sub-pattern close to the first sub-pattern.
Drawings
Fig. 1 to 3 are schematic structural diagrams corresponding to a semiconductor structure;
FIG. 4 is a schematic structural diagram of a first embodiment of a reticle layout of the present invention;
FIG. 5 is a schematic structural diagram of a second embodiment of the reticle layout of the present invention;
FIGS. 6 and 7 are schematic structural diagrams of a first embodiment of a semiconductor structure of the present invention;
FIG. 8 is a schematic structural diagram of a semiconductor structure according to a second embodiment of the present invention.
Detailed Description
The devices formed at present still have the problem of poor performance. The reason for the poor performance of a semiconductor structure is now analyzed in conjunction with a semiconductor structure.
Referring to fig. 1 to 3, a structure diagram of a semiconductor structure is shown.
The semiconductor structure includes: an underlying interconnect structure, the underlying interconnect structure comprising: a substrate (not shown); a first sub-interconnect layer 1 on the substrate, the first sub-interconnect layer 1 having an extending direction; a second sub-interconnection layer 2, located on the substrate on one side of the first sub-interconnection layer 1, the second sub-interconnection layer 2 being spaced apart from the first sub-interconnection layer 1, the second sub-interconnection layer 2 extending along a second direction, the extending direction of the second sub-interconnection layer 2 being perpendicular to the extending direction of the first sub-interconnection layer 1, and the extending direction of the second sub-interconnection layer 2 intersecting the extending direction of the first sub-interconnection layer 1; a third sub interconnection layer 3 on the substrate, spaced from the second sub interconnection layer 2 in the first direction, and spaced from the first sub interconnection layer 1 in the second direction; a fourth sub interconnection layer 4 on the substrate on the other side of the second sub interconnection layer 2, spaced from the second sub interconnection layer 2 in the first direction, the fourth sub interconnection layer 4 being spaced from the first sub interconnection layer 1 in the second direction; and a top layer interconnection structure located on the bottom layer interconnection structure, wherein the top layer interconnection structure comprises the contact plug 5, the bottom of the contact plug 5 is in contact with the top of the second sub-interconnection layer 2, and the contact plug 5 is located at one end, close to the first sub-interconnection layer 1, of the second sub-interconnection layer 2 in the extending direction.
Fig. 1 is a top view, fig. 2 is a cross-sectional view at aa of fig. 1, in order to enable the contact plug 5 to contact with one end of the second sub-interconnection layer 2 close to the first sub-interconnection layer 1, the second sub-interconnection layer 2 is extended towards the first sub-interconnection layer 1, accordingly, the designed interval between the mask of the first sub-interconnection layer 1 and the mask of the second sub-interconnection layer is small, and generally the mask of the first sub-interconnection layer 1 and the mask of the second sub-interconnection layer are in the same layout, so that in the step of forming the second opening by exposure according to the mask of the first sub-interconnection layer 1, the first opening and the second opening are too close due to optical proximity effect, and the first opening and the second opening are filled with conductive materials to form the first sub-interconnection layer 1 and the second sub-interconnection layer 2 respectively, the second sub-interconnect layer 2 and the first sub-interconnect layer 1 are easily bridged (as shown at B in fig. 2), resulting in poor electrical performance of the semiconductor structure.
Fig. 3 is a cross-sectional view at aa of fig. 1, in order to avoid bridging between the second sub-interconnect layer 2 and the first sub-interconnect layer 1, the interval between the second sub-interconnect layer 2 and the first sub-interconnect layer 1 is enlarged, which may result in that the contact plug 5 is not easily contacted with one end of the second sub-interconnect layer 2 close to the first sub-interconnect layer 1, and an open circuit (as shown at C in fig. 3) exists between the contact plug 5 and the second sub-interconnect layer 2, resulting in poor electrical performance of the semiconductor structure.
In order to solve the technical problem, an embodiment of the present invention provides a reticle layout, including: the first mask layout comprises a plurality of interconnection layer graphs, and the interconnection layer graphs comprise a first sub graph, a second sub graph and a third sub graph which are positioned on one side of the first sub graph; the second sub-graph and the third sub-graph are positioned in the same layout, the first sub-graph, the second sub-graph and the third sub-graph are arranged at intervals, and the first sub-graph extends along a first direction; the second sub-pattern extends along a second direction, the first direction is perpendicular to the second direction, and the extending direction of the second sub-pattern is intersected with the extending direction of the first sub-pattern; in the first direction, the third sub-graph is positioned on at least one side of the second sub-graph, and the third sub-graph is connected with the end part, close to one side of the first sub-graph, of the second sub-graph; and the second mask layout comprises a plurality of hole patterns, wherein the hole patterns are positioned in the area where the interconnection layer patterns are positioned, and in the second sub-pattern, the hole patterns are positioned at the end part of the second sub-pattern close to one side of the first sub-pattern.
The embodiment of the invention provides a mask layout, wherein the second sub-pattern and the third sub-pattern are located in the same layout, and in the same step, a first opening (not shown in the figure) is formed by exposure according to the second sub-pattern, a second opening is formed by exposure according to the third sub-pattern, conductive materials are filled in the first opening and the second opening, a second sub-interconnection layer is respectively formed in the first opening, and a third sub-interconnection layer is formed in the second opening, wherein the hole pattern is used for forming a contact plug connected with the second interconnection layer, and in the second sub-pattern, the hole pattern is located at an end part of the second sub-pattern close to one side of the first sub-pattern. In the embodiment of the invention, the third sub-pattern is connected with the second sub-pattern, the third sub-pattern and the second sub-pattern are positioned in the same layout, and the third sub-pattern is connected with one end of the second sub-pattern close to the first sub-pattern.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
FIG. 4 is a schematic structural diagram of a first embodiment of the reticle layout of the present invention. The structure of the reticle layout of the present invention will be described in detail with reference to fig. 4.
The mask layout comprises the following steps: the mask layout comprises a plurality of interconnection layer graphs, wherein each interconnection layer graph comprises a first sub-graph 101, a second sub-graph 102 and a third sub-graph 103, wherein the second sub-graph 102 and the third sub-graph are positioned on one side of the first sub-graph 101; the second sub-pattern 102 and the third sub-pattern 103 are located in the same layout, the first sub-pattern 101 is arranged at intervals with the second sub-pattern 102 and the third sub-pattern 103, and the first sub-pattern 101 extends along a first direction; the second sub-pattern 102 extends along a second direction, the first direction and the second direction are perpendicular, and the extending direction of the second sub-pattern 102 intersects with the extending direction of the first sub-pattern 101; in the first direction, the third subpattern 103 is positioned on at least one side of the second subpattern 102, and the third subpattern 103 is connected with the end part of the second subpattern 102 close to one side of the first subpattern 101; and the second mask layout comprises a plurality of hole patterns 201, wherein the hole patterns 201 are positioned in the region where the interconnection layer patterns are positioned, and in the second sub-pattern 102, the hole patterns 201 are positioned at the end part of the second sub-pattern 102 close to one side of the first sub-pattern 101.
In the mask layout provided in the embodiment of the present invention, the second sub-pattern 102 and the third sub-pattern 103 are located in the same layout, and in the same step, a first opening (not shown in the figure) is formed by exposure according to the second sub-pattern 102, a second opening is formed by exposure according to the third sub-pattern 103, conductive materials are filled in the first opening and the second opening, a second sub-interconnection layer is formed in the first opening, and a third sub-interconnection layer is formed in the second opening, and the hole pattern 201 is used for forming a contact plug connected to the second interconnection layer, where in the second sub-pattern 102, the hole pattern 201 is located at an end of the second sub-pattern 102 close to the first sub-pattern 101. In the embodiment of the present invention, the third sub-pattern 103 is connected to the second sub-pattern 102, the third sub-pattern 103 and the second sub-pattern 102 are located in the same layout, and one end of the third sub-pattern 103, which is close to the first sub-pattern 101, is connected to one end of the second sub-pattern 102, so that the total area of the third sub-pattern 103 and the second sub-pattern 102 is larger than that in the case without the third sub-pattern, during an exposure process, according to an optical proximity effect, the size of the formed first opening in the second direction is easy to conform to a design, the correspondingly formed second sub-interconnection layer meets design requirements, the formed contact plug is easy to form on the second sub-interconnection layer, the contact plug is in good contact with the second sub-interconnection layer, the semiconductor structure is not easy to have bridging or short circuit, and the electrical performance of the semiconductor structure is improved.
In this embodiment, the first reticle layout includes a plurality of interconnection layer patterns, the interconnection layer patterns are used to form an interconnection layer, and the interconnection layer is a back end of line (BEOL) metal link.
Specifically, the first sub-pattern 101 is used for forming a first sub-interconnection layer subsequently, the second sub-pattern 102 is used for forming a second sub-interconnection layer subsequently, and the third sub-pattern 103 is used for forming a third sub-interconnection layer subsequently.
In this embodiment, in the second direction, the distance D6 between the first sub-pattern 101 and the second sub-pattern 102 is not too large or too small. If the distance D6 between the first sub-pattern 101 and the second sub-pattern 102 is too large, the distance between the first sub-interconnection layer and the second sub-interconnection layer in the subsequently formed semiconductor structure is too large, the utilization rate of the planar area of the semiconductor structure is low, which is not favorable for improving the integration level of the semiconductor structure, and the power consumption of the semiconductor structure is large. If the distance D6 between the first sub-pattern 101 and the second sub-pattern 102 is too small, the first sub-pattern 101 and the second sub-pattern 102 are in the same layout, resulting in a first opening (not shown in the figure) formed by exposure according to the first sub-pattern 101, and in the step of forming a second opening by exposure according to the second sub-pattern 102, the first opening and the second opening are too close to each other due to the optical proximity effect, and accordingly, a first sub-interconnect layer formed in the first opening and a second sub-interconnect layer formed in the second opening are prone to contact, resulting in poor electrical performance of the semiconductor structure. In this embodiment, in the second direction, a distance D6 between the first sub-pattern 101 and the second sub-pattern 102 is less than or equal to 50 nm.
The hole pattern 201 is used to form a contact plug, and the bottom of the contact plug is in contact with the interconnection layer in the semiconductor structure.
In this embodiment, in the second direction, the hole pattern 201 in the second sub-pattern 102 has a first edge 2011 facing the first sub-pattern 101, and the second sub-pattern 102 has a second edge 1021 facing the first sub-pattern 102. It should be noted that the distance D1 between the first side 2011 and the second side 1021 is not necessarily too small. If the distance D1 is too small, even a small overlay error may cause the contact area between the formed contact plug and the second sub-interconnection layer to be too small, or the contact plug may be directly disconnected from the second sub-interconnection layer during the formation of the contact plug according to the hole pattern 201, resulting in poor electrical performance of the semiconductor structure. In this embodiment, a distance D1 between the first side 2011 and the second side 1021 is greater than or equal to 6 nanometers.
It should be noted that the second sub-pattern 102 and the third sub-pattern 103 are located in the same layout, and the corresponding second sub-pattern 102 and the third sub-pattern 103 are exposed in one step.
In this embodiment, the interconnect layer pattern further includes: a fourth sub-pattern 104 spaced from the second sub-pattern 102 in the first direction and spaced from the first sub-pattern 101 in the second direction, wherein the fourth sub-pattern 104 is located on a side of the second sub-pattern 102 facing away from the third sub-pattern 103.
The fourth sub-pattern 104 is used to form a fourth sub-interconnect layer.
It should be noted that, in the first direction, the distance D2 between the second sub pattern 102 and the fourth sub pattern 104 is not too large. If the distance D2 between the second sub-pattern 102 and the fourth sub-pattern 104 is too large, the distance D2 between the second sub-interconnection layer and the fourth sub-interconnection layer in the formed semiconductor structure is too large, the planar area utilization rate of the semiconductor structure is low, which is not favorable for improving the integration level of the semiconductor structure, and the power consumption of the semiconductor structure is large. In this embodiment, the distance D2 between the second sub-pattern 102 and the fourth sub-pattern 104 is less than or equal to 30 nm.
In the second direction, the distance D3 between the fourth sub-pattern 104 and the first sub-pattern 101 is not too large or too small. If the distance D3 between the fourth sub-pattern 104 and the first sub-pattern 101 is too large, the planar area utilization rate of the semiconductor structure is low, which is not favorable for improving the integration of the semiconductor structure, resulting in larger energy consumption of the semiconductor structure. If the distance D3 between the fourth sub-pattern 104 and the first sub-pattern 101 is too small, during the process of forming the first sub-interconnect layer according to the first sub-pattern 101 and forming the fourth sub-interconnect layer according to the fourth sub-pattern 104, even a slight overlay error may cause bridging between the formed first sub-interconnect layer and the fourth sub-interconnect layer, resulting in poor electrical performance of the semiconductor structure. In this embodiment, in the second direction, a distance D3 between the fourth sub-pattern 104 and the first sub-pattern 101 is greater than 50 nm and less than 60 nm.
It should be noted that, in the first direction, the length D4 of the third sub-pattern 103 is not too short. The second sub-pattern 102 and the third sub-pattern 103 are exposed in one step, and the total area of the third sub-pattern 103 and the second sub-pattern 102 is larger than that of the third sub-pattern, so that the size of the formed first opening in the second direction is easily matched with the design according to the optical proximity effect during the exposure process. If the third sub-pattern 103 is too short, that is, the third sub-pattern 103 is too short in the first direction, the total area of the third sub-pattern 103 and the second sub-pattern 102 does not increase significantly, under the effect of the optical proximity effect, the first opening formed by exposure is shorter in the second direction, and the corresponding second sub-interconnection layer is shorter in the second direction, accordingly, the contact plug is not easily formed on the second sub-interconnection layer, and the contact area between the contact plug and the second sub-interconnection layer is smaller or even open, resulting in electrical performance of the semiconductor structure. In this embodiment, in the first direction, the length D4 of the third sub-pattern 103 is at least 96 nm.
In this embodiment, the interconnect layer pattern further includes: a fifth sub-pattern 105, wherein in the first direction, the fifth sub-pattern 105 is located on a side of the second sub-pattern 102 facing away from the fourth sub-pattern 104 and spaced from the third sub-pattern 103, and in the second direction, the fifth sub-pattern 105 is spaced from the first sub-pattern 101.
The fifth sub-pattern 105 is used to form a fifth sub-interconnection layer.
In the first direction, the distance D5 between the third sub-pattern 103 and the fifth sub-pattern 105 should not be too small. If the distance D5 between the third sub-pattern 103 and the fifth sub-pattern 105 in the first direction is too small, even a small overlay error may cause the third sub-interconnection layer and the fifth sub-interconnection layer to be bridged during the process of forming the third sub-interconnection layer according to the third sub-pattern 103 and forming the fifth sub-interconnection layer according to the fifth sub-pattern 105, resulting in poor electrical performance of the semiconductor structure. If the distance D5 between the third sub-pattern 103 and the fifth sub-pattern 105 in the first direction is too large, the planar area utilization rate of the semiconductor structure is low, which is not favorable for improving the integration of the semiconductor structure, and the power consumption of the semiconductor structure is large. In this embodiment, in the first direction, a distance D5 between the third sub-pattern 103 and the fifth sub-pattern 105 is greater than or equal to 24 nm.
It should be noted that the corresponding region in the fifth sub-pattern 105 also corresponds to the via pattern 201, and the via pattern 201 in the fifth sub-pattern 105 is prepared for forming a contact plug connected to the fifth sub-interconnection layer.
FIG. 5 is a schematic structural diagram of a second embodiment of the reticle layout of the present invention. The same parts of the embodiment of the present invention as the first embodiment are not described herein again, but the differences are: the third sub-pattern 303 is located on both sides of the second sub-pattern 302. The first embodiment and the second embodiment are different design schemes under different process requirements.
The embodiment of the invention provides a reticle layout, wherein the second sub-pattern 302 and the third sub-pattern 303 are located in the same layout, and in the same step, a first opening (not shown in the figure) is formed by exposure according to the second sub-pattern 302, a second opening is formed by exposure according to the third sub-pattern 303, conductive materials are filled in the first opening and the second opening, a second sub-interconnection layer is formed in the first opening, and a third sub-interconnection layer is formed in the second opening, and the hole pattern 401 is used for forming a contact plug connected with the second interconnection layer, wherein in the second sub-pattern 302, the hole pattern 401 is located at an end portion of the second sub-pattern 302 close to one side of the first sub-pattern 301. In the embodiment of the present invention, the third sub-pattern 303 and the second sub-pattern 302 are located in the same layout, and the third sub-pattern 303 and the second sub-pattern 302 are connected at an end close to the first sub-pattern 301, so that the total area of the third sub-pattern 303 and the second sub-pattern 302 is larger than that in the case of no third sub-pattern.
In this embodiment, in the first direction, the third sub-pattern 303 is located on both sides of the second sub-pattern 302; the interconnect layer pattern further includes: a fourth sub-pattern 304 on one side of the second sub-pattern 302 spaced from the third sub-pattern in the first direction, the fourth sub-pattern 304 spaced from the first sub-pattern 101 in the second direction; a fifth sub-pattern 305 located on the other side of the second sub-pattern 302 and spaced from the third sub-pattern in the first direction, the fifth sub-pattern 305 being spaced from the first sub-pattern 301 in the second direction.
It should be noted that, in the first direction, the length E3 of the third sub-pattern 303 is not too small. If the length of the third sub-pattern 303 is too small in the first direction, the total area increase of the third sub-pattern 303 and the second sub-pattern 302 is not significant, during the exposure process, according to the optical proximity effect, the size of the formed first opening in the second direction is relatively short, the size of the correspondingly formed second sub-interconnection layer in the second direction is relatively short, accordingly, the formed contact plug is not easily formed on the second sub-interconnection layer, the contact area of the contact plug and the second sub-interconnection layer is relatively small, and even is open, so that the electrical performance of the semiconductor structure is caused. In this embodiment, in the first direction, the length E3 of the third sub-pattern 303 is greater than or equal to 10 nm.
It should be noted that, in the first direction, the distance E5 from the fourth sub pattern 304 to the adjacent third sub pattern 303 is not too small. In the first direction, the distance E5 from the fourth sub-pattern 304 to the adjacent third sub-pattern 303 is too small, and even a slight overlay error is liable to cause bridging between the formed third sub-interconnection layer and the fourth sub-interconnection layer during the process of forming the third sub-interconnection layer according to the third sub-pattern 303 and forming the fourth sub-interconnection layer according to the fourth sub-pattern 304, resulting in poor electrical performance of the semiconductor structure. In this embodiment, in the first direction, a distance E5 from the fourth sub pattern 304 to the adjacent third sub pattern 303 is greater than or equal to 20 nm.
It should be noted that, in the first direction, the distance E4 from the fifth sub-pattern to the adjacent third sub-pattern is not too small. In the first direction, the distance E4 from the fifth sub-pattern 305 to the adjacent third sub-pattern 303 is too small, and in the process of forming the third sub-interconnection layer according to the third sub-pattern 303 and forming the fifth sub-interconnection layer according to the fifth sub-pattern 305, even a slight overlay error easily causes bridging between the formed third sub-interconnection layer and the fifth sub-interconnection layer, resulting in poor electrical performance of the semiconductor structure. In this embodiment, in the first direction, a distance E4 from the fifth sub-pattern 305 to the adjacent third sub-pattern 303 is greater than or equal to 20 nm.
It should be noted that the corresponding region in the fifth sub-pattern 305 also corresponds to the via pattern 401, and the via pattern 401 in the fifth sub-pattern 305 is prepared for the subsequent formation of a contact plug connected to the fifth sub-interconnection layer.
Correspondingly, the embodiment of the invention also provides a semiconductor structure. Referring to fig. 6 and 7, schematic structural diagrams of an embodiment of the semiconductor structure of the present invention are shown.
The semiconductor structure includes: a substrate (not shown); an interconnect layer on the substrate, the interconnect layer comprising: a first sub-interconnect layer 501, the first sub-interconnect layer 501 extending in a first direction; a second sub-interconnection layer 502 located on the substrate on one side of the first sub-interconnection layer 501, the second sub-interconnection layer 502 and the first sub-interconnection layer 501 being arranged at intervals, the second sub-interconnection layer 502 extending along a second direction, the first direction being perpendicular to the second direction, and the extending direction of the second sub-interconnection layer 502 intersecting the extending direction of the first sub-interconnection layer 501; the third sub-interconnection layer 503 is located on at least one side of the second sub-interconnection layer 502 in the first direction, and the third sub-interconnection layer 503 is connected to an end portion of the second sub-interconnection layer 502 close to one side of the first sub-interconnection layer 501; and a plurality of contact plugs 601 located on the interconnect layer, wherein the contact plugs 601 are in contact with the top of the second sub-interconnect layer 502, and in the second sub-interconnect layer 502, the contact plugs 601 are located at the end of the second sub-interconnect layer 502 close to the first sub-interconnect layer 501.
In this embodiment of the present invention, the third sub-interconnection layer 503 and the second sub-interconnection layer 502 are formed according to a second sub-pattern and a third sub-pattern, respectively, where the second sub-pattern and the third sub-pattern are located in the same layout, and the step of forming the second sub-interconnection layer 502 and the third sub-interconnection layer 503 includes: in the same step, a first opening (not shown in the figure) is formed by exposure according to a second sub-pattern, a second opening is formed by exposure according to a third sub-pattern, the first opening and the second opening are filled with conductive materials, a second sub-interconnection layer 502 is respectively formed in the first opening, a third sub-interconnection layer 503 is formed in the second opening, compared with the case without the third sub-pattern, the total area of the third sub-pattern and the second sub-pattern is larger, correspondingly, during the exposure process, the size of the formed first opening in the second direction is easy to conform to the design according to the optical proximity effect, the size of the formed second sub-interconnection layer 502 in the second direction meets the design requirement, the formed contact plug 601 is easy to form on the second sub-interconnection layer 502, the contact plug 601 is in good contact with the second sub-interconnection layer 502, and the semiconductor structure is not easy to bridge or short circuit, the method is favorable for improving the electrical property of the semiconductor structure.
In this embodiment, the interconnect layer is a back end of line (BEOL) metal interconnect. The material of the interconnection layer comprises: one or more of Cu, Co, Ni, Pt and Al.
In the second direction, the distance D6 from the first sub-interconnect layer 501 to the second sub-interconnect layer 502 should not be too large or too small. If the distance D6 between the first sub-interconnect layer 501 and the second sub-interconnect layer 502 is too large, the planar area utilization rate of the semiconductor structure is low, which is not favorable for improving the integration level of the semiconductor structure, and the power consumption of the semiconductor structure is large. If the distance D6 between the first sub-interconnect layer 501 and the second sub-interconnect layer 502 is too small, the first sub-interconnect layer 501 and the second sub-interconnect layer 502 are prone to bridging, resulting in poor electrical performance of the semiconductor structure. In this embodiment, in the second direction, a distance D6 between the first sub-interconnect layer 501 and the second sub-interconnect layer 502 is less than or equal to 50 nm.
In the second direction, the second sub-interconnect layer 502 has a first face 5021 facing the first sub-interconnect layer 501, and the distance F from the bottom of the contact plug 601 to the first face 5021 is not too small. If the distance is too small, the contact plug 601 is easily formed between the first sub-interconnect layer 501 and the second sub-interconnect layer 502, which may cause the contact plug 601 and the second sub-interconnect layer 502 to be disconnected, or may cause the contact area between the contact plug 601 and the second sub-interconnect layer 502 to be too small, which may result in poor electrical performance of the semiconductor structure. In this embodiment, a distance F from the bottom of the contact plug 601 to the first face 5021 is greater than or equal to 6 nm.
In this embodiment, the interconnect layer further includes: a fourth sub-interconnection layer 504 on the substrate, spaced from the second sub-interconnection layer 502 in the first direction, spaced from the first sub-interconnection layer 501 in the second direction, and the fourth sub-interconnection layer 504 is located on a side of the second sub-interconnection layer 502 facing away from the fourth sub-interconnection layer 504.
It should be noted that, in the first direction, the distance D2 between the second sub-interconnect layer 502 and the fourth sub-interconnect layer 504 is not too large. If the distance D2 between the second sub-interconnect layer 502 and the fourth sub-interconnect layer 504 is too large, the planar area utilization rate of the semiconductor structure is low, which is not favorable for improving the integration level of the semiconductor structure, and the power consumption of the semiconductor structure is large. In the present embodiment, in the first direction, a distance D2 between the second sub-interconnect layer 502 and the fourth sub-interconnect layer 504 is less than or equal to 30 nanometers.
It should be noted that, in the second direction, the distance D3 from the fourth sub-interconnect layer 504 to the first sub-interconnect layer 501 is not too large nor too small. If the distance D3 from the fourth sub-interconnect layer 504 to the first sub-interconnect layer 501 is too large, the planar area utilization rate of the semiconductor structure is low, which is not favorable for improving the integration level of the semiconductor structure, and the power consumption of the semiconductor structure is large. If the distance D3 from the fourth sub-interconnect layer 504 to the first sub-interconnect layer 501 is too small, the first sub-interconnect layer 501 and the fourth sub-interconnect layer 504 are bridged, resulting in poor electrical performance of the semiconductor structure. In the present embodiment, in the second direction, the distance D3 between the fourth sub-interconnect layer 504 and the first sub-interconnect layer 501 is greater than 50 nm and less than 60 nm.
Note that, in the first direction, the length D4 of the third sub-interconnect layer 503 is not too short. The third sub-interconnection layer 503 is formed according to a third sub-pattern, the second sub-interconnection layer 502 is formed according to a second sub-pattern, and the total area of the third sub-pattern and the second sub-pattern is larger than that of the third sub-pattern, so that the size of the first opening formed in the second direction is easily matched with the design according to the optical proximity effect during the exposure process according to the embodiment of the invention. If the third sub-interconnection layer 503 is too short, that is, the third sub-pattern is too short in the first direction, the total area increase of the third sub-pattern and the second sub-pattern is not significant, in the process of forming the second sub-interconnection layer 502 and the third sub-interconnection layer 503 according to the second sub-pattern and the third sub-pattern, respectively, under the effect of the optical proximity effect, the size increase of the first opening formed by exposure in the second direction is not significant, the size increase of the correspondingly formed second sub-interconnection layer 502 in the second direction is not significant, accordingly, the contact plug 601 is not easily formed on the second sub-interconnection layer 502, the contact area of the contact plug 601 and the second sub-interconnection layer 502 is small, and even is open, resulting in the electrical performance of the semiconductor structure. In the present embodiment, the length D4 of the third sub-interconnect layer 503 is at least 96 nm in the first direction.
In this embodiment, the interconnect layer further includes: a fifth sub-interconnection layer 505, the fifth sub-interconnection layer 505 being located on a side of the second sub-interconnection layer 502 facing away from the fourth sub-interconnection layer 504 and spaced apart from the third sub-interconnection layer 503 in the first direction, and the fifth sub-interconnection layer 505 being spaced apart from the first sub-interconnection layer 501 in the second direction.
In this embodiment, in the first direction, the distance D5 between the third sub-interconnect layer 503 and the fifth sub-interconnect layer 505 is not too small. If the distance D5 between the third sub-interconnect layer 503 and the fifth sub-interconnect layer 505 is too small in the first direction, the third sub-interconnect layer 503 and the fifth sub-interconnect layer 505 are prone to bridging, resulting in poor electrical performance of the semiconductor structure. If the distance D5 between the third sub-interconnect layer 503 and the fifth sub-pattern 105 in the first direction is too large, the planar area utilization of the semiconductor structure is low, which is not favorable for improving the integration of the semiconductor structure, and the power consumption of the semiconductor structure is large. In the first direction, a distance D5 from the third sub-interconnect layer 503 to the fifth sub-interconnect layer 505 is greater than or equal to 24 nanometers.
It should be noted that a contact plug 601 is also corresponding to a corresponding region in the fifth sub-interconnect layer 505, and the contact plug 601 in the fifth sub-interconnect layer 505 is connected to the fifth sub-interconnect layer 505.
Fig. 8 is a schematic structural diagram of a semiconductor structure according to a second embodiment of the present invention, and the same points as those in the first embodiment of the present invention are not repeated herein, except that: the third sub-interconnect layers 703 are located on both sides of the second sub-interconnect layer 702.
In this embodiment of the present invention, the third sub-interconnection layer 703 and the second sub-interconnection layer 702 are formed according to a second sub-pattern and a third sub-pattern, respectively, where the second sub-pattern and the third sub-pattern are located in the same layout, and the step of forming the second sub-interconnection layer 702 and the third sub-interconnection layer 703 includes: in the same step, a first opening (not shown in the figure) is formed by exposure according to a second sub-pattern, a second opening is formed by exposure according to a third sub-pattern, the first opening and the second opening are filled with conductive materials, a second sub-interconnection layer 702 is respectively formed in the first opening, a third sub-interconnection layer 703 is formed in the second opening, compared with the case without the third sub-pattern, the total area of the third sub-pattern and the second sub-pattern is larger, correspondingly, during the exposure process, the size of the formed first opening in the second direction is easy to conform to the design according to the optical proximity effect, the size of the formed second sub-interconnection layer 702 in the second direction meets the design requirement, the formed contact plug 801 is easy to form on the second sub-interconnection layer 702, the contact plug 801 is in good contact with the second sub-interconnection layer 702, and the semiconductor structure is not easy to bridge or short-circuit, the method is favorable for improving the electrical property of the semiconductor structure.
In the first direction, the third sub-interconnect layer 703 is located on both sides of the second sub-interconnect layer 702; the interconnect layer pattern further includes: a fourth sub interconnection layer 704 on the substrate on one side of the second sub interconnection layer 702, spaced from the third sub interconnection layer 703 in the first direction, the fourth sub interconnection layer 704 being spaced from the first sub interconnection layer 701 in the second direction; a fifth sub interconnection layer 705 on the substrate on the other side of the second sub interconnection layer 702, spaced from the third sub interconnection layer 703 in the first direction, the fifth sub interconnection layer 705 being spaced from the first sub interconnection layer 701 in the second direction.
It should be noted that, in the first direction, the length E3 of the third sub-interconnect layer 703 is not too small. The third sub-interconnection layer 703 is formed according to a third sub-pattern, and the second sub-interconnection layer 702 is formed according to a second sub-pattern, where the second sub-pattern and the third sub-pattern are located in the same layout and exposed at the same time. If the length of the third sub-interconnect layer 703 is too small in the first direction, the formed first opening does not significantly increase in the second direction under the effect of the optical proximity effect during the formation of the third sub-interconnect layer and the second sub-interconnect layer according to the third sub-pattern and the second sub-pattern, the corresponding size increase of the formed second sub-interconnect layer 702 in the second direction is not significant, and accordingly, the formed contact plug 801 is easily formed between the second sub-interconnect layer 702 and the first sub-interconnect layer 701, which may cause the contact plug 801 and the second sub-interconnect layer 702 to be disconnected, or the contact area of the contact plug 801 and the second sub-interconnect layer 702 is smaller, which may cause the electrical performance of the semiconductor structure. In this embodiment, in the first direction, the length E3 of the third sub-interconnect layer 703 is greater than or equal to 10 nanometers.
It should be noted that, in the first direction, the distance E5 from the fourth sub-interconnect layer 704 to the adjacent third sub-interconnect layer 703 is not too small. In the first direction, the distance E5 from the fourth sub-interconnect layer 704 to the adjacent third sub-interconnect layer 703 is too small, and the third sub-interconnect layer 703 and the fourth sub-interconnect layer 704 are prone to bridging, resulting in poor electrical performance of the semiconductor structure. In the first direction, a distance E5 from the fourth sub-interconnect layer 704 to the adjacent third sub-interconnect layer 703 is greater than or equal to 20 nanometers.
In addition, in the first direction, the distance E4 from the fifth sub-pattern 705 to the adjacent third sub-interconnection layer 703 is not excessively small. In the first direction, the distance E4 from the fifth sub-interconnect layer 705 to the adjacent third sub-interconnect layer 703 is too small, and the third sub-interconnect layer 703 and the fifth sub-interconnect layer 705 are prone to bridging, resulting in poor electrical performance of the semiconductor structure. In this embodiment, in the first direction, a distance E4 from the fifth sub-interconnect layer 705 to the adjacent third sub-interconnect layer 703 is greater than or equal to 20 nanometers.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A reticle layout, comprising:
the first mask layout comprises a plurality of interconnection layer graphs, and the interconnection layer graphs comprise a first sub graph, a second sub graph and a third sub graph which are positioned on one side of the first sub graph; the second sub-graph and the third sub-graph are positioned in the same layout, the first sub-graph, the second sub-graph and the third sub-graph are arranged at intervals, and the first sub-graph extends along a first direction; the second sub-pattern extends along a second direction, the first direction is perpendicular to the second direction, and the extending direction of the second sub-pattern is intersected with the extending direction of the first sub-pattern; in the first direction, the third sub-graph is positioned on at least one side of the second sub-graph, and the third sub-graph is connected with the end part, close to one side of the first sub-graph, of the second sub-graph;
and the second mask layout comprises a plurality of hole patterns, wherein the hole patterns are positioned in the area where the interconnection layer patterns are positioned, and in the second sub-pattern, the hole patterns are positioned at the end part of the second sub-pattern close to one side of the first sub-pattern.
2. The reticle layout of claim 1, wherein the interconnect layer pattern further comprises: and the fourth sub-pattern is spaced from the second sub-pattern in the first direction and spaced from the first sub-pattern in the second direction, and the fourth sub-pattern is positioned on the side, back to the third sub-pattern, of the second sub-pattern.
3. The reticle layout of claim 1, wherein the third sub-feature is located on both sides of the second sub-feature in the first direction;
the interconnect layer pattern further includes: a fourth sub-pattern located at one side of the second sub-pattern and spaced from the third sub-pattern in the first direction, the fourth sub-pattern being spaced from the first sub-pattern in the second direction;
and the fifth sub-graph is positioned on the other side of the second sub-graph and is spaced from the third sub-graph in the first direction, and the fifth sub-graph is spaced from the first sub-graph in the second direction.
4. The reticle layout of claim 2, wherein a distance from the second sub-feature to the fourth sub-feature in the first direction is less than or equal to 30 nanometers;
in the second direction, the distance between the fourth sub-pattern and the first sub-pattern is greater than 50 nanometers and less than 60 nanometers.
5. The reticle layout of claim 2, wherein the length of the third sub-feature in the first direction is at least 96 nanometers.
6. The reticle layout of claim 2 or 5, wherein said interconnect layer pattern further comprises: a fifth sub-pattern, located on a side of the second sub-pattern facing away from the fourth sub-pattern in the first direction and spaced from the third sub-pattern, and spaced from the first sub-pattern in the second direction;
in the first direction, the distance from the third subpattern to the fifth subpattern is greater than or equal to 24 nanometers.
7. The reticle layout of claim 3, wherein a length of the third sub-feature is greater than or equal to 10 nanometers in the first direction.
8. The reticle layout of claim 3 or 7, wherein a distance from the fourth sub-pattern to an adjacent third sub-pattern in the first direction is greater than or equal to 20 nanometers;
the distance from the fifth sub-pattern to the adjacent third sub-pattern is greater than or equal to 20 nanometers.
9. The reticle layout of claim 1, wherein a distance from the first sub-feature to the second sub-feature in the second direction is less than or equal to 50 nanometers.
10. The reticle layout of claim 1, wherein in the second direction, the hole pattern in the second sub pattern has a first edge facing the first sub pattern, the second sub pattern has a second edge facing the second sub pattern, and a distance from the first edge to the second edge is greater than or equal to 6 nanometers.
11. A semiconductor structure, comprising:
a substrate;
an interconnect layer on the substrate, the interconnect layer comprising:
a first sub-interconnect layer extending in a first direction;
the second sub-interconnection layer is positioned on the substrate on one side of the first sub-interconnection layer, the second sub-interconnection layer and the first sub-interconnection layer are arranged at intervals, the second sub-interconnection layer extends along a second direction, the first direction is perpendicular to the second direction, and the extending direction of the second sub-interconnection layer is intersected with the extending direction of the first sub-interconnection layer;
a third sub-interconnection layer located on at least one side of the second sub-interconnection layer in the first direction, and connected to an end portion of the second sub-interconnection layer on a side close to the first sub-interconnection layer;
and a plurality of contact plugs which are positioned on the interconnection layer and are in contact with the top of a second sub-interconnection layer, wherein on the second sub-interconnection layer, the contact plugs are positioned at the end part of the second sub-interconnection layer close to one side of the first sub-interconnection layer.
12. The semiconductor structure of claim 11, wherein the interconnect layer further comprises: and the fourth sub-interconnection layer is positioned on the substrate, is spaced from the second sub-interconnection layer in the first direction and is spaced from the first sub-interconnection layer in the second direction, and is positioned on one side, facing away from the third sub-interconnection layer, of the second sub-interconnection layer.
13. The semiconductor structure of claim 11, wherein in the first direction, the third sub-interconnect layer is located on both sides of the second sub-interconnect layer;
the interconnect layer pattern further includes: a fourth sub-interconnection layer on the substrate on one side of the second sub-interconnection layer, spaced from the third sub-interconnection layer in the first direction, the fourth sub-interconnection layer being spaced from the first sub-interconnection layer in the second direction;
a fifth sub-interconnection layer on the substrate on the other side of the second sub-interconnection layer, spaced from the third sub-interconnection layer in the first direction, the fifth sub-interconnection layer being spaced from the first sub-interconnection layer in the second direction.
14. The semiconductor structure of claim 12, wherein a distance from the second sub-interconnect layer to the fourth sub-interconnect layer in the first direction is less than or equal to 30 nanometers;
the distance from the fourth sub-interconnection layer to the first sub-interconnection layer is greater than 50 nanometers and less than 60 nanometers.
15. The semiconductor structure of claim 12, wherein a length of the third sub-interconnect layer in the first direction is at least 96 nanometers.
16. The semiconductor structure of claim 12 or 15, wherein the interconnect layer further comprises: a fifth sub-interconnection layer, located on a side of the second sub-interconnection layer facing away from the fourth sub-interconnection layer in the first direction, and spaced apart from the third sub-interconnection layer, and spaced apart from the first sub-interconnection layer in the second direction;
a distance from the third sub-interconnect layer to the fifth sub-interconnect layer in the first direction is greater than or equal to 24 nanometers.
17. The semiconductor structure of claim 13, wherein a length of the third sub-interconnect layer in the first direction is greater than or equal to 10 nanometers.
18. The semiconductor structure of claim 13 or 17, wherein a distance from the fourth sub-interconnect layer to an adjacent third sub-interconnect layer in the first direction is greater than or equal to 20 nanometers;
the distance from the fifth sub-interconnect layer to an adjacent third sub-interconnect layer is greater than or equal to 20 nanometers.
19. The semiconductor structure of claim 11, wherein a distance from the first sub-interconnect layer to the second sub-interconnect layer in the second direction is less than or equal to 50 nanometers.
20. The semiconductor structure of claim 11, wherein in the second direction, the second sub-interconnect layer has a first face facing the second sub-interconnect layer, and a distance from a bottom of the contact plug to the first face is greater than or equal to 6 nanometers.
CN202010364447.2A 2020-04-30 2020-04-30 Mask layout and semiconductor structure Active CN113589638B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010364447.2A CN113589638B (en) 2020-04-30 2020-04-30 Mask layout and semiconductor structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010364447.2A CN113589638B (en) 2020-04-30 2020-04-30 Mask layout and semiconductor structure

Publications (2)

Publication Number Publication Date
CN113589638A true CN113589638A (en) 2021-11-02
CN113589638B CN113589638B (en) 2024-05-24

Family

ID=78237304

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010364447.2A Active CN113589638B (en) 2020-04-30 2020-04-30 Mask layout and semiconductor structure

Country Status (1)

Country Link
CN (1) CN113589638B (en)

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001284455A (en) * 2000-03-29 2001-10-12 Kawasaki Steel Corp Method and apparatus for automatic layout and semiconductor integrated circuit using them
US20020162079A1 (en) * 2001-04-27 2002-10-31 Mutsunori Igarashi Automated wiring pattern layout method
US20030052386A1 (en) * 2001-09-20 2003-03-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with resistor layer having heat radiation path to semiconductor substrate
US20040021227A1 (en) * 2002-07-31 2004-02-05 Fujitsu Limited Semiconductor device and method for fabricating the same
US20060188824A1 (en) * 2005-02-23 2006-08-24 Harry Chuang Method for improving design window
US20070273028A1 (en) * 2006-05-26 2007-11-29 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device comprising different level interconnection layers connected by conductor layers including conductor layer for redundancy
CN101196682A (en) * 2006-12-05 2008-06-11 中芯国际集成电路制造(上海)有限公司 Mask plate territory for manufacturing connecting pore and its design method
US20080142977A1 (en) * 2006-12-19 2008-06-19 Fujitsu Limited Semiconductor device having a multilayer interconnection structure
US20090273100A1 (en) * 2008-05-02 2009-11-05 Texas Instruments Inc. Integrated circuit having interleaved gridded features, mask set and method for printing
CN102956612A (en) * 2011-08-26 2013-03-06 联华电子股份有限公司 Electric fuse structure
CN103187395A (en) * 2011-12-29 2013-07-03 中芯国际集成电路制造(上海)有限公司 Interconnection structure of semiconductors and formation method
CN103311103A (en) * 2013-04-28 2013-09-18 上海华力微电子有限公司 Layout-layer designing method of semiconductor chip and masking plate thereof
WO2019210618A1 (en) * 2018-05-03 2019-11-07 中芯集成电路（宁波）有限公司 Mask and manufacturing method therefor

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001284455A (en) * 2000-03-29 2001-10-12 Kawasaki Steel Corp Method and apparatus for automatic layout and semiconductor integrated circuit using them
US20020162079A1 (en) * 2001-04-27 2002-10-31 Mutsunori Igarashi Automated wiring pattern layout method
US20030052386A1 (en) * 2001-09-20 2003-03-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with resistor layer having heat radiation path to semiconductor substrate
US20040021227A1 (en) * 2002-07-31 2004-02-05 Fujitsu Limited Semiconductor device and method for fabricating the same
US20060188824A1 (en) * 2005-02-23 2006-08-24 Harry Chuang Method for improving design window
US20070273028A1 (en) * 2006-05-26 2007-11-29 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device comprising different level interconnection layers connected by conductor layers including conductor layer for redundancy
CN101196682A (en) * 2006-12-05 2008-06-11 中芯国际集成电路制造(上海)有限公司 Mask plate territory for manufacturing connecting pore and its design method
US20080142977A1 (en) * 2006-12-19 2008-06-19 Fujitsu Limited Semiconductor device having a multilayer interconnection structure
US20090273100A1 (en) * 2008-05-02 2009-11-05 Texas Instruments Inc. Integrated circuit having interleaved gridded features, mask set and method for printing
CN102956612A (en) * 2011-08-26 2013-03-06 联华电子股份有限公司 Electric fuse structure
CN103187395A (en) * 2011-12-29 2013-07-03 中芯国际集成电路制造(上海)有限公司 Interconnection structure of semiconductors and formation method
CN103311103A (en) * 2013-04-28 2013-09-18 上海华力微电子有限公司 Layout-layer designing method of semiconductor chip and masking plate thereof
WO2019210618A1 (en) * 2018-05-03 2019-11-07 中芯集成电路（宁波）有限公司 Mask and manufacturing method therefor

Also Published As

Publication number Publication date
CN113589638B (en) 2024-05-24

Similar Documents

Publication Publication Date Title
US8869079B2 (en) Semiconductor device and layout design method for the same
US8598712B2 (en) Semiconductor structure formed by double patterning technique
US7651950B2 (en) Method for forming a pattern of a semiconductor device
KR102697540B1 (en) Method of manufacturing imprint master template
KR100824200B1 (en) Metal layer of semiconductor device
KR20090070674A (en) Method of forming metal wiring in flash memory device
JP3420089B2 (en) Electronic device, semiconductor device, and electrode forming method
CN103066070B (en) Integrated circuit method with triple patterning
CN113589638B (en) Mask layout and semiconductor structure
CN215418179U (en) Semiconductor structure
KR20010017560A (en) Method for forming dual damascene structure
KR20110078794A (en) Producing method for contact hole mask for semiconductor
KR20100042941A (en) Methods of manufacturing a semiconductor device for photographing concurrently dpt area and non-dpt area by using one merging photomask
KR20170052886A (en) Photomask blank and method of photomask using the photomask blank
TWI822307B (en) Double patterning method of manufacturing select gates and word lines
CN113658937B (en) Semiconductor structure, manufacturing method thereof and method for manufacturing semiconductor layout
US20040127034A1 (en) Method for fabricating semiconductor device
US20240210816A1 (en) Method of forming a layout pattern and photomask
TWI573249B (en) Method for manufacturing semiconductor layout pattern, method for manufacturing semiconductor device, and semiconductor device
KR100902582B1 (en) Method for contact hole pattern formation of semiconductor
KR100214261B1 (en) Method for forming metal wiring in semiconductor device
KR20100022731A (en) Method for fabricating fine pattern having irregular width
KR20090103057A (en) Method of forming patterns in semiconductor device
KR100586531B1 (en) Method for settlement of etching time of pattern by pattern density
JP2004319637A (en) Method of forming alignment mark and method of manufacturing semiconductor device using the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant