TWI573249B - Method for manufacturing semiconductor layout pattern, method for manufacturing semiconductor device, and semiconductor device - Google Patents

Description

Semiconductor layout pattern manufacturing method, semiconductor device manufacturing method, and semiconductor device

The present invention relates to a method of fabricating a semiconductor layout pattern, a method of fabricating a semiconductor device, and a semiconductor device, and more particularly to a method of fabricating a semiconductor layout pattern that can avoid the influence of line-end rounding, and fabrication of a semiconductor device. Method and semiconductor component.

The photolithography process is one of the most important steps in the semiconductor process, which is used to transfer the layout patterns of integrated circuits (ICs) from the reticle to a certain ratio to The photoresist layer on the surface of the semiconductor wafer, in turn, transfers the layout pattern of the integrated circuit to the semiconductor wafer.

As the complexity and accumulative degree of the integrated circuit increase, the size of the component shrinks, and the layout integrity of the wafer surface deteriorates after the lithography process. In other words, the difference between the circuit pattern on the surface of the wafer and the original mask pattern becomes large. This phenomenon is due to many effects, such as optical proximity effects or/and chemical treatments, etc., and corner rounding, line end shortening, and The line ends are rounded and so on. In addition, these phenomena are also related to the underlying material and the density of the pattern.

Please refer to FIG. 1. FIG. 1 is a schematic view showing a photoresist pattern formed on a semiconductor wafer by a lithography process. As shown in FIG. 1, in the semiconductor process, at least one pattern layer 12, such as a doped region pattern, a conductive layer pattern, an insulating pattern, or the like, may have been formed on the wafer 10. Next, a photoresist layer (not shown) is formed on the wafer 10, and then a lithography process is performed to transfer a circuit layout pattern onto the photoresist layer to form a photoresist pattern layer 14. It is to be noted that the angle θ ₁ between the end of the overlapping photoresist pattern layer 14 and the front layer pattern layer 12 does not have an ideal or expected 90 degrees due to the phenomenon of optical proximity effects such as line end rounding. (°) (as indicated by the angle θ ₂ ). The acute angle existing between the photoresist pattern layer 14 and the front layer pattern layer 12 indicates that the transferred pattern already has a defect of pattern distortion, and this defect not only causes difficulty in subsequent semiconductor processing, but is more likely to cause components. Deformation or even loss affects semiconductor process yield and semiconductor component performance.

Since the optical proximity effect cannot be avoided in the lithography process, that is, the problem of rounding of the wire ends cannot be avoided, how to avoid the influence of the rounding of the wire ends on the semiconductor components is a problem that the industry is eager to overcome.

Accordingly, it is an object of the present invention to provide a method of fabricating a semiconductor layout pattern, a method of fabricating a semiconductor device, and a semiconductor device obtained by the methods, which can avoid an optical proximity effect such as rounding of a wire end.

According to the patent application scope of the present invention, there is provided a method of fabricating a semiconductor device, which first provides a substrate, and a mask layer is formed on the substrate. The manufacturing method further includes a first mask and a second mask, the first mask includes a first layout pattern, the first layout pattern includes a plurality of active regions and at least one neck portion. And the neck connects two adjacent active area portions; and the second photomask includes a second layout pattern. Next, the first layout pattern is transferred from the first mask to the mask layer to form a plurality of active area patterns and at least one neck pattern in the mask layer, and the neck pattern connects two phases The active area pattern of the neighbor. And then transferring the second layout pattern from the second mask to the mask layer to remove the neck pattern and form a patterned mask, the patterned mask comprising the active area patterns, and at least two A slot is formed between the active area patterns.

According to the patent application scope provided by the present invention, there is further provided a method for fabricating a semiconductor layout pattern, which first provides a first pattern, the first pattern comprising a plurality of independent predetermined active area patterns. Next, a second pattern is provided for defining a slit between two adjacent predetermined active area patterns. After the slit is defined, a third pattern is provided to the first pattern to form a neck compensation pattern in the first pattern, and the neck compensation pattern corresponds to the slit. After the neck compensation pattern is formed in the first pattern, the first pattern and the neck compensation pattern are outputted to a first mask to form a first layout pattern, and the second pattern is outputted to a second pattern. Photomask Into a second layout pattern.

According to the patent application scope of the present invention, a semiconductor device includes a substrate, a plurality of active regions disposed in the substrate, and at least one disposed between the adjacent two active regions. a slit, and two of the active regions on either side of the slit respectively comprise at least three obtuse angles.

The method for fabricating a semiconductor layout pattern according to the present invention is such that a corresponding neck compensation pattern is formed where linear end rounding may occur, such as at a slit. Therefore, when forming the semiconductor component, the neck compensation pattern can avoid the negative influence of the process difficulty and the process yield caused by the rounding of the wire end.

Please refer to FIG. 2 to FIG. 7 . FIG. 2 to FIG. 7 are schematic diagrams showing a first preferred embodiment of a method for fabricating a semiconductor layout pattern according to the present invention. As shown in FIG. 2, the preferred embodiment first provides a plurality of independent predetermined active area patterns 100 in a computer system. In the preferred embodiment, the predetermined active area pattern 100 may be a doped area predetermined pattern, but is not limited thereto. It should also be noted that in FIG. 2, each predetermined active area pattern 100 has a predetermined gap 102 therebetween, and the predetermined gap 102 has a predetermined width w ₁ . In the preferred embodiment, the predetermined width w ₁ is a minimum width, but those skilled in the art will recognize that the predetermined width w ₁ is not limited thereto and may be greater than or equal to the minimum width.

Please refer to Figure 3. Next, each predetermined active area pattern 100 is merged to form a first pattern 110. It is to be noted that, in order to emphasize the relationship between the predetermined active area pattern 100 and the first pattern 110, the opposite side lines of the adjacent predetermined active area patterns 100 in FIG. 3 are respectively indicated by broken lines. In other words, the first pattern 110 still contains a plurality of predetermined active area patterns 100.

Please refer to Figure 4. The method for fabricating the semiconductor layout pattern provided by the preferred embodiment further provides a second pattern 120 corresponding to a predetermined gap 102 between each predetermined active region pattern 100 for adjacent two A slit (not shown) is defined between the predetermined active area patterns 100. And as shown in FIG. 4, the width w ₂ of the second pattern 120 is equal to a predetermined width w ₁ of the predetermined gap 102 between the predetermined active region patterns 100.

Please refer to FIG. 5, which is a modification of the method for fabricating the semiconductor layout pattern provided by the preferred embodiment. In the present variation, the step of increasing the second pattern 120 is further performed to form an enlarged second pattern 122. It is to be noted that increasing the width w ₃ of the second pattern 122 is greater than the predetermined width w ₁ to facilitate the alignment of the first pattern 110 with the increase of the second pattern 122 and to increase the process margin.

Please refer to Figure 6. Next, the semiconductor provided by the preferred embodiment The layout pattern is formed by shrinking the first pattern 110 by a certain ratio to form a third pattern 130.

Please refer to Figure 7. Next, the first pattern 110 and the second pattern 120 are overlapped to remove a portion of the first pattern 110 corresponding to the second pattern 120, and a slit 142 is defined between the adjacent two predetermined active region patterns 100. This is because the predetermined width w ₁ between the predetermined active area patterns 100 is too small, so that when the active area is subsequently formed, the difficulty in pattern transfer and the occurrence of pattern deformation may occur due to the predetermined width w _{1 of} the predetermined gap 102 being too small. Therefore, in the preferred embodiment, when the predetermined width w _{1 is} less than or equal to a certain value, the predetermined active area patterns 100 on both sides of the predetermined gap 102 are merged to improve the integrity of the pattern transfer. And a slit 142 is defined in the first pattern 110 by the second pattern 120 between the merged predetermined active area patterns 100 to form mutually independent active regions in subsequent processes. Therefore, in the preferred embodiment, the second pattern 120 is provided to the first pattern 110, and the second pattern 120 is overlapped with the first pattern 110 corresponding to the gap 102 between the predetermined active area patterns 100 to be moved. In addition to a portion of the first pattern 110, a slit 142 is defined.

Please continue to see Figure 7. Subsequently, the third pattern 130 is provided to the first pattern 110 to form a neck compensation pattern in the first pattern 110, and the neck compensation pattern corresponds to the slit 142. After performing an optical proximity correction method, it is formed as shown in FIG. A first layout pattern 140. Subsequently, the first layout pattern 140 is output to a first mask 150 (shown in FIG. 12B). The first layout pattern 140 includes a plurality of active area portions 146 (corresponding to a predetermined active area pattern 100) and a neck portion 144 (corresponding to a predetermined gap 102) disposed at the slit 142, and the neck portion 144 connects two adjacent ones. Active area section 146. In addition, after performing an optical proximity correction method on the second pattern 120, the preferred embodiment outputs the second pattern 120 to a second mask 152 (shown in FIG. 14) to form a second layout pattern 148.

It should be noted that the preferred embodiment further provides a Boolean operation method for forming the first layout pattern 140. First, when the predetermined width w _{1 of the} predetermined gap 102 is less than or equal to a certain value, the first pattern 110 formed by combining the predetermined active area patterns 100 on both sides of the predetermined gap 102 is defined as A, which will be used to define the slit 142. The second pattern 120 is defined as B, the third pattern 130 formed by shrinking the first pattern 110 by a certain ratio is defined as C, and the first layout pattern 140 to be obtained is defined as D, and the first layout pattern D (140) ) is obtained according to the following Boolean expression: D = (A not B) or C

According to the method for fabricating the semiconductor layout pattern provided by the preferred embodiment, the predetermined active area pattern 100 of which the predetermined width w ₁ of the predetermined gap 102 is less than or equal to a certain value is merged into the first pattern 110, and the second pattern 120 is The defined slits 142 (corresponding to the predetermined gaps 102) ensure that the resulting active regions remain separate from each other. More importantly, the preferred embodiment further forms a neck 144 connecting the active region 146 on both sides of the slit 142 in the slit 142, and the neck 144 is used in the subsequent process to avoid rounding of the end of the wire. The process causes problems such as increased complexity and pattern distortion.

Please refer to FIG. 2 to FIG. 4 and FIG. 8 to FIG. 10 . FIG. 8 to FIG. 10 are schematic diagrams showing a second preferred embodiment of a method for fabricating a semiconductor layout pattern according to the present invention. It should be noted that the same components in the second preferred embodiment as the first preferred embodiment are denoted by the same reference numerals, and the details of these components can be referred to the first preferred embodiment, so Let me repeat. As shown in FIGS. 2 to 4, the preferred embodiment also provides a plurality of independent predetermined active area patterns 100 with predetermined gaps 102 between the predetermined active area patterns 100. Next, each predetermined active area pattern 100 is combined to form a first pattern 110 as shown in FIG. 3; and the preferred embodiment further provides a second pattern 120 as shown in FIG.

Please refer to Figure 8 for the next figure. In the preferred embodiment, an intersection of the first pattern 110 and the second pattern 120 is first obtained to obtain an intersection pattern 112. Next, as shown in FIG. 9, the intersection pattern 112 is reduced in a certain ratio to form a predetermined compensation pattern 144.

Please refer to Figure 10. Next, the predetermined compensation pattern 144 is provided to the pre- The active area patterns 100 are defined and corresponding to the predetermined gaps 102 to form a neck compensation pattern between the predetermined active area patterns 100. After an optical proximity correction method is performed, a first layout pattern 140' as shown in Fig. 10 is formed. Subsequently, the first layout pattern 140' is output to a first mask 150 (shown in Figure 12B). The first layout pattern 140' includes a plurality of active area portions 146 (corresponding to a predetermined active area pattern 100) and a neck portion 144' (corresponding to a predetermined compensation pattern 144), and the neck portion 144' connects two adjacent active area portions. 146. In addition, as described above, after performing an optical proximity correction method on the second pattern 120, the preferred embodiment also outputs the second pattern 120 to a second mask 152 (shown in FIG. 14) to form a second. Layout pattern 148.

According to the method for fabricating the semiconductor layout pattern provided by the preferred embodiment, a predetermined compensation pattern 144 corresponding to the predetermined gap 102 is obtained by reducing the intersection pattern of the first pattern 110 and the second pattern 120, and the predetermined compensation pattern is obtained. 144 becomes the neck 144 ′ of the first reticle 150 for connecting at least two active area portions 146 , so as to avoid the problems of complexity increase and pattern deformation of the process in the subsequent process.

Referring to FIG. 11 to FIG. 17B, FIG. 11 to FIG. 17B are schematic views showing a preferred embodiment of a method for fabricating a semiconductor device according to the present invention. As shown in FIG. 11, the preferred embodiment first provides a substrate 200, which may be a substrate, but is not limited thereto. A doped region 202 is selectively formed in the substrate 200, and a pad is formed on the substrate 200. A pad oxide layer 204 and a first mask layer 206. In the preferred embodiment, the first mask layer 206 is a composite mask layer, and the composite mask layer may sequentially include a silicon nitride layer 206a and a silicon oxide layer 206b. , but not limited to this. A second mask layer 208 is further formed on the first mask layer 206. In the embodiment, the second mask layer 208 may include an organic dielectric layer (Organic Dielectric Layer) from bottom to top. ODL) 208a, a Silicon-containing Hardmask Bottom anti-reflection coating (SHB) 208b, and a photoresist layer 208c. In addition, since an amorphous germanium layer such as an advanced patterning film (APF) has good high aspect ratio (HAR), low edge line roughness (LER), and ashing PR-like ashability can therefore also be used to replace the ODL 208a in this embodiment. In summary, the second mask layer 208 provided by the preferred embodiment is a three-layer structure layer, and the implementation form may include ODL/SHB/resist or APF/germanium inorganic dielectric layer/resistance, etc., but Not limited to this.

Referring to Figures 12A and 12B, it should be noted that Figure 12B is a cross-sectional view taken along line A ₁ -A ₁ ' in Figure 12A. As shown in FIG. 12A and FIG. 12B, the method for fabricating the semiconductor device provided by the preferred embodiment provides a first mask 150 formed on the first mask 150 according to the method for fabricating the semiconductor layout pattern. The first layout pattern 140, as shown in FIG. 7, includes a plurality of active area portions 146, at least one slit 142 disposed between each active area portion 146, and a slit The neck 144 at the 142 is sewn, and the neck 144 is connected to two adjacent active region portions 146. Next, the first layout pattern 140 is transferred from the first mask 150 to the photoresist layer 208c to form a plurality of active region patterns 210 and at least one neck pattern 212 in the photoresist layer 208c, and the neck pattern 212 is connected to the two. Adjacent active area patterns 210. In addition, it can be noted that, as shown in Fig. 12A, the right angle in the predetermined pattern is affected by the optical proximity effect, and is rounded to become an arc angle after development.

Please refer to Figure 13. Next, the SHB 208b, the ODL 208a, and the first mask layer 206 are exposed by the photoresist layer 208c until the pad oxide layer 204 is exposed, and the active region pattern 210 and the neck pattern 212 are transferred to the first mask layer. 206, then removing the second mask layer 208 (including the ODL 208a, the SHB 208b, and the photoresist layer 208c). After the second mask layer 208 is removed, a third mask layer 220 is formed on the substrate 200. The third mask layer 220 can also be a three-layer structure layer, which is the same as the second mask layer 208. From the bottom up, there may be an ODL 220a-SHB 220b and a photoresist layer 220c. Similarly, the APF/germanium inorganic dielectric layer/resistor can also be used in this embodiment, but is not limited thereto.

Please refer to Figure 14. In the preferred embodiment, after the active area pattern 210 and the neck pattern 212 are transferred to the first mask layer 206 and the third mask layer 220 is formed, a second mask 152 is further provided, and the second mask 152 is provided. The second layout pattern 148 described above is included. Next, the second layout pattern 148 is transferred from the second mask 152 to the photoresist layer 220c, and the second layout pattern 148 corresponds to the neck. The portion pattern 212 is transferred to form at least one opening pattern 222 at the corresponding neck pattern 212.

Please refer to Figures 15A to 15C. It should be noted that Figure 15B is a cross-sectional view taken along line A ₂ -A ₂ ' in Figure 15A, and Figure 15C is a circle E in Figure 15A. An enlarged view of the circled part. To emphasize the second layout pattern 148 and the active area pattern 210 and the neck pattern 212, the second layout patterns 148 in FIGS. 15A and 15C are each indicated by a broken line. As shown in FIGS. 15A to 15C, after the second layout pattern 148 is transferred to the photoresist layer 220c to form the opening pattern 222, the SHB 220b, the ODL 220c, and the first mask layer 206 are etched downward through the opening pattern 222. Until a portion of the pad oxide layer 204 is exposed. It is noted that this etching step removes the neck pattern 212 within the first mask layer 206 and forms a patterned mask 224. It should be noted that the patterned mask 224 includes the active area pattern 210, and a slot 214 is formed between the at least two adjacent active area patterns 210. Subsequently, the third mask layer 220 (including the photoresist layer 220c, the SHB 220b and the ODL 220a) is removed, and as shown in FIGS. 15A to 15B, only the patterned mask including the active region pattern 210 remains on the substrate 200. 224. It is worth noting that the slit 214 is formed at the original neck pattern 212. And since the neck pattern 212 is removed in this step, a separate active area pattern 210 can be obtained as desired. In addition, in the preferred embodiment, the 2P2E mode of development-etch-develop-etch is used as an example, but those skilled in the art should understand that the preferred embodiment can also adopt the development-development-etching 2P1E method. Not limited to this.

Referring to Figure 15C, and more importantly, the second layout pattern 148 has a significant line end rounding effect due to the optical proximity effect. Since the preferred embodiment is provided with a recessed neck pattern 212 between two adjacent active area patterns 210, the line end rounding effect of the second layout pattern 148 can be slowed down for the active area pattern 210. influences. As shown in FIG. 15C, after the neck pattern 212 is removed, the active area pattern 210 on both sides of the slit 214 has an included angle θ ₃ at the slit 214, and the included angle θ ₃ is greater than 90°, that is, The active area pattern 210 has two obtuse angles on the side of the slit 214. As described above, since the active area pattern 210 is also affected by the rounding effect when the first layout pattern 140 is transferred, each of the active area patterns 210 on both sides of the slit 214 includes at least as shown in FIG. 15A. The three obtuse angles, for example, have four obtuse angles in the preferred embodiment. Even in all corners of the active area pattern 210, the corners are obtuse, and in particular, the active area pattern 210 on the slit 214 side must be an obtuse angle.

Next, please refer to Figure 16. After forming the individual active region patterns 210, an etching process is performed to etch the pad oxide layer 204 and the substrate 200 through the patterned mask 224 to form a plurality of trenches 230 in the substrate 200.

Please refer to Figures 17A and 17B. It should be noted that Figure 17B is a cross-sectional view taken along line A ₃ -A ₃ ' in Figure 17A. After the trench 230 is formed, the preferred embodiment further fills an insulating material in the trench 230, especially in the trench 230 at the slit 214, and removes excess insulating material and patterned by a planarization process. The cover 224 forms a shallow trench isolation 232 with the pad oxide layer 204, and active regions 234 surrounded and electrically isolated by the shallow trench isolation 232.

Please continue to refer to Figures 17A and 17B. According to the method of fabricating a semiconductor device provided by the present invention, a semiconductor device is provided. The semiconductor device includes a substrate 200, a plurality of active regions 234 disposed in the substrate 200, and at least one active region 234 disposed adjacent to each other. Between the slits 214. In the preferred embodiment, the active regions 234 each include a doped region 202, but are not limited thereto. As shown in Fig. 17A, the two active regions 234 on either side of the slit 214 each contain at least three obtuse angles. More notably, the two active regions 234 on both sides of the slit 214 must have an included angle θ ₃ at an obtuse angle on the slit 214 side, respectively. It is also worth noting that since the two active regions 234 on both sides of the slit 214 must have an angle θ ₃ which is an obtuse angle on the slit 214 side, the presence of the obtuse angle may be present when the trench 230 is filled with an insulating material. The insulating material is more smoothly filled into the trench 230 at the slit 214 to ensure electrical isolation there.

According to the method for fabricating the semiconductor device and the semiconductor device according to the preferred embodiment, a neck pattern 212 is formed between the active region patterns 210, and the position of the neck pattern 212 is formed by subsequent isolation. the Lord The slit 214 of the moving region pattern 210. Therefore, when the slit 214 is formed, the neck pattern 212 can be prevented from causing an undesired influence on the active area pattern 210 by rounding the line end. Thus, in forming the shallow trench isolation 232 between the active region 234 and the active active region 234, a complete pattern can be obtained and the electrical isolation of the active regions 234 on both sides of the slit 214 can be enhanced.

In the above, the semiconductor layout pattern provided by the present invention is formed at a point where rounding of the line ends may occur, for example, where a slit is to be formed, a corresponding compensation neck pattern is formed first. Therefore, when forming the semiconductor component, the compensation of the neck pattern can avoid the negative influence of the process difficulty and the process yield caused by the rounding of the wire end.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10‧‧‧ wafer

12‧‧‧pattern layer

14‧‧‧ photoresist pattern layer

100‧‧‧Predetermined active area pattern

102‧‧‧Predetermined gap

110‧‧‧ first pattern

112‧‧‧Intersection pattern

120‧‧‧second pattern

122‧‧‧Enlarge the second pattern

130‧‧‧ Third pattern

140, 140’‧‧‧ first layout pattern

142‧‧‧slit

144, 144’ ‧ ‧ neck

146‧‧‧Active Regional Department

148‧‧‧Second layout pattern

150‧‧‧First mask

152‧‧‧second mask

200‧‧‧Base

202‧‧‧Doped area

204‧‧‧Mat oxide layer

206‧‧‧First mask layer

206a‧‧‧ layer of tantalum nitride

206b‧‧‧Oxide layer

208‧‧‧second mask layer

208a‧‧‧Organic dielectric layer

208b‧‧‧Anti-reflective layer with hard mask bottom

208c‧‧‧ photoresist layer

210‧‧‧Active area pattern

212‧‧‧Neck pattern

214‧‧‧slit

220‧‧‧ third mask layer

220a‧‧‧Organic Dielectric Layer

220b‧‧‧with hard cover Antireflection layer

220c‧‧‧ photoresist layer

222‧‧‧ opening pattern

224‧‧‧ patterned mask

230‧‧‧ Ditch

232‧‧‧Shallow trench isolation

234‧‧‧Active area

w ₁ ‧‧‧Predetermined width

w ₂ ‧‧‧second pattern width

w ₃ ‧‧‧Increase the width of the second pattern

A‧‧‧first pattern

B‧‧‧second pattern

C‧‧‧ third pattern

E‧‧‧ circle

D‧‧‧First layout pattern

A ₁ -A ₁ '‧‧‧ cut line

A ₃ -A ₃ '‧‧‧ Cut line

A ₂ -A ₂ '‧‧‧ cut line

FIG. 1 is a schematic view showing a conventional photoresist pattern formed on a semiconductor wafer by a lithography process.

2 to 7 are schematic views of a first preferred embodiment of a method for fabricating a semiconductor layout pattern according to the present invention, wherein FIG. 5 is a method for fabricating a semiconductor layout pattern according to a preferred embodiment of the present invention. A variant.

8 to 10 are schematic views showing a second preferred embodiment of a method for fabricating a semiconductor layout pattern provided by the present invention.

11 to 17B are schematic views showing a preferred embodiment of a method of fabricating a semiconductor device according to the present invention.

110‧‧‧ first pattern

120‧‧‧second pattern

130‧‧‧ Third pattern

140‧‧‧First layout pattern

142‧‧‧slit

144‧‧‧ neck

146‧‧‧Active Regional Department

A‧‧‧first pattern

B‧‧‧second pattern

C‧‧‧ third pattern

D‧‧‧First layout pattern

Claims (19)

A method of fabricating a semiconductor device, comprising: providing a substrate having a mask layer formed thereon; providing a first mask, the first mask comprising a first layout pattern, the first layout pattern comprising a plurality of An active area portion and at least one neck portion, and the neck portion connects two adjacent active portion portions; providing a second photomask, the second mask comprising a second layout pattern; a mask transfers the first layout pattern to the mask layer to form a plurality of active area patterns and at least one neck pattern in the mask layer, and the neck pattern connects two adjacent active area patterns And transferring the second layout pattern from the second mask to the mask layer to remove the neck pattern and form a patterned mask, the patterned mask comprising the active area patterns, wherein at least two A slot is formed between the active area patterns. The method of claim 1, wherein the active area patterns on both sides of the slit comprise at least three obtuse angles. The method of claim 1, wherein the mask layer is a composite mask layer. The method of claim 3, further comprising the steps of: performing an etching process, etching the substrate through the patterned mask to form Forming a plurality of ditches; and filling an insulating material in the ditches. The manufacturing method of claim 1, wherein the first layout pattern and the second layout pattern are formed on the first mask and the second mask by providing: a first pattern, The first pattern includes a plurality of independent predetermined active area patterns; a second pattern is provided to the first pattern for defining a slit between two adjacent predetermined active area patterns; and the second is provided After the pattern is defined in the first pattern to define the slit, a third pattern is provided to the first pattern and the slit to form the neck portion in the first pattern, and the neck portion corresponds to the slit And outputting the first pattern and the neck to the first mask to form the first layout pattern, and outputting the second pattern to the second mask to form the second layout pattern. The manufacturing method of claim 5, further comprising combining the predetermined active area patterns to form the first pattern. The manufacturing method of claim 6, further comprising: overlapping the first pattern and the second pattern to remove a portion of the first pattern corresponding to the second pattern, and the adjacent two Predefined active area pattern definition The step of the slit is performed before the third pattern is provided. The manufacturing method of claim 7, further comprising the step of increasing the second pattern, before overlapping the first pattern and the second pattern. The manufacturing method of claim 5, further comprising the step of reducing the first pattern to form the third pattern. The manufacturing method of claim 5, further comprising an optical proximity correction (OPC), respectively performing outputting the first pattern to the first mask and outputting the second pattern to the Before the second mask. A method for fabricating a semiconductor layout pattern, comprising: providing a first pattern, the first pattern comprising a plurality of independent predetermined active area patterns; providing a second pattern to the first pattern for adjacent two Defining a slit between the predetermined active area patterns; after providing the second pattern into the first pattern to define the slit, providing a third pattern to the first pattern and the slit, Forming a neck compensation pattern in a pattern, and the neck compensation pattern corresponds to the slit; And outputting the first pattern and the neck compensation pattern to a first mask to form a first layout pattern, and outputting the second pattern to a second mask to form a second layout pattern. The manufacturing method of claim 11, further comprising combining the predetermined active area patterns to form the first pattern. The manufacturing method of claim 12, further comprising: overlapping the first pattern and the second pattern to remove a portion of the first pattern corresponding to the second pattern, and the adjacent two The step of defining the slit between the predetermined active area patterns is performed before the third pattern is provided. The manufacturing method of claim 13, further comprising the step of increasing the second pattern, before overlapping the first pattern and the second pattern. The manufacturing method of claim 11, further comprising the step of reducing the first pattern to form the third pattern. The manufacturing method of claim 11, further comprising an optical proximity correction method, respectively, before outputting the first pattern to the first mask and outputting the second pattern to the second mask. A semiconductor device comprising: a substrate; a plurality of active regions disposed in the substrate; and at least one slit disposed between the adjacent two of the active regions, and two of the two sides of the slit The active regions each contain at least three obtuse angles. The semiconductor device of claim 17, wherein the active regions each comprise a doped region. The semiconductor device according to claim 18, further comprising an insulating material surrounding the active regions and filling the slit.