525224 五、發明說明（1) 發明之領域 | 本發明係提供一種微影製程之光罩圖案的轉移方法， 尤指一種可避免微影製程產生圖案尺寸縮小化 (end-of-nne shortening)的圖案轉移方法。 背景說明 微影（photolithography)是半導體製程中最重要的一 個步驟，其可將積體電路（integrated circuits)的佈局 (lay out)圖案順利地轉移到半導體晶片上。晶圓廠為了在 丨半導體晶片上形成一設計的積體電路，必須先製作一光罩 I並在光罩上形成一設計的圖案，再藉由微影製程將光罩上 |的圖案以一定的比例轉移（t r a n s f e r )到該半導體晶片表面 丨的光阻層上。 ! 隨著積體電路的複雜度與積集度（integration)的不 丨斷提昇’光罩上的圖案亦被設計得越來越小。然而在進行 |圖案轉移時，由於曝光（exposure)製程所能製作出的圖案 |的臨界尺寸（critical dimension，CD)會受限於曝光機台 I (optical exposure tool)的解析度極限（resolution |lim it)，因此在對於這些高密度排列的光罩圖案進行曝光 |製程以形成光阻圖案時’便非常容易產生光學接近效應 i(optical proximity effect)，使得形成於光阻層上之圖 525224 五、發明說明（2) 案的轉角處（corner )將會因為過度曝光（0vereXp0se)或是 曝光不足（underexpose)，造成解析度減損（res〇lutiori 1 〇 s s )，進而導致所設計圖案之尺寸的縮小化，使得光罩 上的圖案與光阻層上的圖案不一致或是發生轉角圓形化效 應（corner rounding effect)，最後造成於光阻層上的圖 案會與原始的設計尺寸差異甚遠。 請參考圖一至圖三，圖一至圖三為習知微影製程的示 意圖。該微影製程係用來於一半導體晶片丨〇上定義一動態 隨機存取記憶體（dynamic random access memory，DRAM) 之電容下層儲存電極（storage node)的尺寸與位置。如圖 一所示，半導體晶片1 〇包含有一基底1 6，以^ 一光阻層i 7 設於基底1 6的表面。基底1 6包含一矽基底1 2，一由矽氧化 合物所構成之絕緣層1 3，複數個由摻雜多晶矽（doped =ly silicon)所構成之接觸電極（n〇de contact) 14設於 絕緣層1 3之中’以及一用來形成該下層儲存電極之非晶矽 層1 5設於絕緣層1 3的表面並覆蓋住各接觸電極1 4。 光阻層17可由一正型光阻（p〇sitiVe photo- resist) 或負型（negative)光阻所構成。當光阻層17係由一正型光 阻所構成時’在進行光化轉換（photochemical transformation)的曝光過程中，光束會穿過一光罩圖案 照射至基底1 6^面之光阻層1 7，讓未被該光束所照射到的 光阻層1 7在後續之顯影與清洗製程中會被留下，使得光阻 525224 五、發明說明（3) 層17上形成一與光罩圖案相同之硬罩幕（hard mask)。反 之’如光阻層1 7係由^一負型光阻劑構成’則未被該光源所 照射的光阻層17會在後續之顯影（devel〇Pment)與清洗製 程中被清除，形成一與光罩圖案互補（complementary)之 硬罩幕。在後敘之習知技術以及本發明的實施例中，半導 體晶片表面之光阻層皆係利用一正型光阻為例來作說明。 如圖二所示，習知在進行微影製程前，係先依據一設 5十的積體電路圖案來製作一光罩21，光罩21包含有一透明 的破璃或石英基板2 3，以及複數個以矩陣方式排列的不透 明之鉻膜圖案2 5設於透明基板23的表面。完成光罩21的製 作，’以光罩2 1對半導體晶片1 〇進行一曝光製程，然後將 =光後的半導體晶片1 Q置於一顯影液中，以進行一顯影製 ^二如，三所示，在顯影製程之後，半導體晶片丨〇必須再 仃數次的清洗製程，以去除顯影液與被溶解的正型光 戶^示而ΐ半導體晶片1 0表面留下一組光阻圖案1 9。如圖四 向=去隨後進行一蝕刻製程，以光阻圖案丨9為硬罩幕垂直 二表面除t被光阻圖案1 9覆蓋的非晶石夕層1 5直到絕緣層1 3 極2 0的輪$成了動態隨機存取記憶體之電容的下層儲存電 然而在 、、 體晶片1〇上；^ j的微影製程中，光學接近效應會造成半導 圆形化的現f 個孤立的（i s ο 1 a t e d)光阻圖案1 9發生轉角 象’亦即光阻圖案1 9的四個頂角係呈現一圓角 525224 五、發明說明（4) 而非原始設計的直角。這是因為在曝光的過程中，雖然光 源的照射能量相同，但是光阻層1 7上各部位的獲得照射能 量卻不盡相同。所以在半導體晶片1 0上光阻圖案1 9的轉角 處將會因為獲得過多的照射能量，即過度曝光，造成光阻 圖案19的轉角處形成圓形的輪廓。甚至產生更嚴重的光學 接近效應，會使得光阻圖案1 9的尺寸縮小化，即光阻圖案 1 9的尺寸小於原始的設計尺寸而呈現如島嶼般的形狀。因 為光阻圖案1 9的尺寸小於原始的設計圖案（圖三中以虛線 表示之圖案），使得後續形成的電容下層儲存電極2 0的尺 寸小於原先的設計尺寸，進而降低了電容下層儲存電極20 所能儲存的電荷容量，影響了積體電路的電性表現。 請參考圖五至圖九，圖五至圖為九習知微影製程另一 實施例的示意圖。該微影製程係用來於一半導體晶片4 0上 定義動態隨機存取記憶體之電容下層儲存電極的尺寸與位 置。如圖五所示，半導體晶片40包含有一基底46，以及一 光阻層47設於基底46的表面。基底4 6包含一矽基底42，一 由矽氧化合物所構成之絕緣層4 3，複數個由摻雜多晶矽 (doped poly silicon)所構成之接觸電極4 4設於絕緣層43 之中，以及一用來形成下層儲存電極之非晶矽層4 5設於絕 緣層43的表面並覆蓋接觸電極44。 如圖六、圖七所示，該微影製程係利用一橫向光罩5 1 與一縱向光罩5 5來代替上述單一光罩的微影製程。橫向光525224 V. Description of the Invention (1) Field of Invention | The present invention provides a method for transferring a reticle pattern of a lithographic process, especially a method for avoiding end-of-nne shortening of the pattern in the lithographic process. Pattern transfer method. Background photolithography is one of the most important steps in the semiconductor manufacturing process. It can smoothly transfer the layout patterns of integrated circuits to semiconductor wafers. In order to form a designed integrated circuit on a semiconductor wafer, a fab must first make a mask I and form a designed pattern on the mask, and then use a lithography process to fix the pattern on the mask to a certain level. Transfer to the photoresist layer on the surface of the semiconductor wafer. With the increasing complexity and integration of integrated circuits, the pattern on the photomask is also designed to be smaller and smaller. However, in the | pattern transfer, the critical dimension (CD) of the pattern that can be produced by the exposure process will be limited by the resolution limit of the optical exposure tool (resolution | lim it), so when these high-density mask patterns are exposed | processed to form a photoresist pattern, it is very easy to produce an optical proximity effect i (optical proximity effect), so that the figure formed on the photoresist layer 525224 V. Description of the invention (2) The corner of the case will be overexposed (0vereXp0se) or underexposed (underexpose), resulting in loss of resolution (resolotiori 1 〇ss), which will lead to the size of the design pattern The reduction in size makes the pattern on the photomask inconsistent with the pattern on the photoresist layer or causes a corner rounding effect. Finally, the pattern on the photoresist layer is far from the original design size. Please refer to Figures 1 to 3, which are schematic diagrams of the conventional lithography process. The lithography process is used to define the size and position of a storage node (storage node) of a capacitor of a dynamic random access memory (DRAM) on a semiconductor wafer. As shown in FIG. 1, the semiconductor wafer 10 includes a substrate 16, and a photoresist layer i 7 is provided on the surface of the substrate 16. The substrate 16 includes a silicon substrate 12, an insulating layer 13 composed of a silicon oxide compound, and a plurality of contact electrodes 14 made of doped polycrystalline silicon (doped = ly silicon). Among the layers 13 and an amorphous silicon layer 15 for forming the lower storage electrode is provided on the surface of the insulating layer 13 and covers each contact electrode 14. The photoresist layer 17 may be formed of a positive photoresist or a negative photoresist. When the photoresist layer 17 is composed of a positive type photoresist, during the exposure process of photochemical transformation, the light beam will pass through a mask pattern and irradiate the photoresist layer 1 on the 6 ^ face of the substrate. 7. Let the photoresist layer 1 which is not irradiated by the light beam 1 7 be left in the subsequent development and cleaning process, so that the photoresist 525224 5. Description of the invention (3) A layer 17 is formed with the same pattern as the mask Hard mask. Conversely, if the photoresist layer 17 is composed of a negative photoresist, the photoresist layer 17 not irradiated by the light source will be removed in the subsequent development and cleaning processes to form a photoresist layer. Complementary hard mask. In the conventional technology described later and the embodiments of the present invention, the photoresist layer on the surface of the semiconductor wafer is described by using a positive photoresist as an example. As shown in FIG. 2, before the lithography process is performed, a photomask 21 is first produced according to a 50-piece integrated circuit pattern. The photomask 21 includes a transparent broken glass or quartz substrate 2 3, and A plurality of opaque chromium film patterns 25 arranged in a matrix are provided on the surface of the transparent substrate 23. Complete the production of the photomask 21, 'expose the semiconductor wafer 10 with the photomask 21, and then place the semiconductor wafer 1 Q after the light in a developing solution to perform a development process. As shown, after the development process, the semiconductor wafer must be cleaned several times to remove the developing solution and the dissolved positive photoresist, and a set of photoresist patterns is left on the surface of the semiconductor wafer 10 9. As shown in the four directions in the figure, an etching process is performed, and a photoresist pattern is used as the vertical two surfaces of the hard mask. The amorphous layer 15 covered by the photoresist pattern 19 is removed to the insulating layer 1 3 and the pole 2 0. In the lithographic process of the lithography process, the optical proximity effect will cause the semi-conducting round shape to be isolated. (Is ο 1 ated) the photoresist pattern 19 has a corner image, that is, the four top corners of the photoresist pattern 19 have a rounded corner 525224. 5. Description of the invention (4) Rather than the right angle of the original design. This is because during the exposure, although the irradiation energy of the light source is the same, the obtained irradiation energy of each part on the photoresist layer 17 is different. Therefore, the corners of the photoresist pattern 19 on the semiconductor wafer 10 will cause a circular outline at the corners of the photoresist pattern 19 because of excessive exposure energy, that is, overexposure. Even more serious optical proximity effects will reduce the size of the photoresist pattern 19, that is, the size of the photoresist pattern 19 is smaller than the original design size and presents an island-like shape. Because the size of the photoresist pattern 19 is smaller than the original design pattern (the pattern indicated by the dotted line in FIG. 3), the size of the subsequent storage capacitor lower layer storage electrode 20 is smaller than the original design size, thereby reducing the capacitor lower storage electrode 20 The charge capacity that can be stored affects the electrical performance of the integrated circuit. Please refer to FIG. 5 to FIG. 9, which are schematic diagrams of another embodiment of the lithography process of Nine Learners. The lithography process is used to define the size and position of the storage electrode of the lower layer of the capacitor of the dynamic random access memory on a semiconductor wafer 40. As shown in FIG. 5, the semiconductor wafer 40 includes a substrate 46, and a photoresist layer 47 is disposed on the surface of the substrate 46. The substrate 46 includes a silicon substrate 42, an insulating layer 4 3 made of silicon oxide compound, a plurality of contact electrodes 4 4 made of doped poly silicon are provided in the insulating layer 43, and An amorphous silicon layer 45 for forming a lower storage electrode is provided on the surface of the insulating layer 43 and covers the contact electrode 44. As shown in FIG. 6 and FIG. 7, the lithography process uses a horizontal photomask 5 1 and a vertical photomask 55 to replace the single photolithography process. Lateral light
第7頁 525224 五、發明說明（5) 罩5 1包含一透明I板5 2，以及複數條橫向條狀圖案5 3設於 透明基板51的表面’而縱向光罩55包含一透明基板56，以 及複數條縱甸條狀圖案5 7設於透明基板5 6的表面。在進行 該微影製程時’孫、，以橫向光罩5 1對半導體晶片4 0進行第 一次曝光製程’ ^著再以縱向光罩5 5對半導體晶片4 0進行 第二次的曝光戴程。 如圖八所系^ *半導體晶片4 0完成曝光製程之後，隨 後便進行顯影製$ y以及數次的清洗製程。半導體晶片4 0經 曝光、顯影與讀^後’會相對應於橫向、縱向光罩5卜5 5 之條狀圖案53、 的4疊處’而於半導體晶片40表面上形 成光阻圖案4 9。$圖九所示’然後再利用一蝕刻製程，以 光阻圖案49為破單幕垂直向下去除未被光阻圖案49覆蓋的 非晶矽層i 5直到絕緣層4 3的表面’形成了動態隨機存取記 憶體之電容的卞層儲存電極50的輪廓。 雖然第二·習知技術之實施例的重覆曝光製程改善了光 學接近=廣、戶斤造成之設計圖案尺寸縮小化的缺點，但是由 於半導體晶片4 0上之光阻層4 7的部分區域亦將經歷二次的 曝光過程，形成複數個重覆曝光區48。這將使得重覆曝光 區4 8中的正型光阻會獲得過多的照射能量’即過度曝光， 而呈現較明顯的光學接近效應’進而造成鄰近之光阻圖案 49的頂角過度曝光，產生圓形輪廊。而且光阻圖案49的尺 寸亦將略小於原始設計圖案的尺寸’使得後續形成的電容 525224 五、發明說明（6) ' 下層儲存電極5 〇的尺寸小於原先的設計尺寸，進而降低了 電容下層儲存電極5 〇所能儲存的電荷容量。 發明概述 本發明之主要目的在於提供一種微影製程之光罩圖案 的轉移方法，以解決上述問題。 从ί Ϊ明係提供一種微影製程之光罩圖案的轉移方法。 該微影氣程係用來於一半導體晶片上定義複數個以陣列方 式排列=光阻圖案，該半導體晶片包含有一基底，以及一 ί殳於該基底之上。本發明之光罩圖案的轉移方法是 案’钬4〜光罩上製作一第一光罩圖案以及第二光罩圖 影製^ 再利用該二光罩圖案來進行一重覆曝光以及一顯 案轉移，使該光阻層相對應該第一與第二光罩圖案進行圖 歹的光卩進而在該光阻層上定義出該複數個以陣列方式排 的不逯^圖案。其中該第一光罩圖案係由複數條彼此平行 數個井條所構成，且每一不透明條均相對應並涵蓋有複 互垂直Ϊ案的相對位置，而該第二光罩圖案係由二組相 、不透明條所交錯構成一栅攔狀圖案。Page 7 525224 V. Description of the invention (5) The cover 5 1 includes a transparent I plate 5 2 and a plurality of horizontal stripe patterns 5 3 are provided on the surface of the transparent substrate 51 ′, and the vertical mask 55 includes a transparent substrate 56. A plurality of longitudinal stripe patterns 57 are provided on the surface of the transparent substrate 56. During this lithography process, 'Sun, perform the first exposure process on the semiconductor wafer 40 with the lateral mask 51', and then perform the second exposure with the longitudinal mask 55 on the semiconductor wafer 40. Cheng. As shown in Figure 8, after the semiconductor wafer 40 has completed the exposure process, the development process $ y and several cleaning processes are then performed. After exposure, development, and reading of the semiconductor wafer 40, a photoresist pattern 4 9 is formed on the surface of the semiconductor wafer 40 corresponding to the stripe patterns 53 and 4 of the horizontal and vertical photomasks 5 and 55. . As shown in FIG. 9, an etching process is then used, and the photoresist pattern 49 is used as a single screen to vertically remove the amorphous silicon layer i 5 not covered by the photoresist pattern 49 until the surface of the insulating layer 4 3 is formed. The outline of the capacitor storage layer 50 of the dynamic random access memory. Although the repeated exposure process of the second embodiment of the conventional technology improves the shortcomings of the reduction in the size of the design pattern caused by the optical proximity = wide and household weight, some areas of the photoresist layer 47 on the semiconductor wafer 40 It will also undergo a second exposure process to form a plurality of repeated exposure areas 48. This will cause the positive photoresist in the repeated exposure area 4 to 8 to obtain too much irradiation energy, that is, overexposure, and exhibit a more obvious optical proximity effect, thereby causing overexposure of the top corners of the adjacent photoresist patterns 49, resulting in Round wheel gallery. Moreover, the size of the photoresist pattern 49 will also be slightly smaller than the size of the original design pattern 'making the subsequent capacitor 525224 V. Description of the invention (6)' The size of the lower storage electrode 50 is smaller than the original design size, thereby reducing the lower storage capacity of the capacitor The charge capacity that electrode 50 can store. SUMMARY OF THE INVENTION The main object of the present invention is to provide a method for transferring a mask pattern in a lithography process to solve the above problems. A method for transferring the reticle pattern of the lithography process is provided from the Department of Lu Ming. The lithography air path is used to define a plurality of arrayed = photoresist patterns on a semiconductor wafer. The semiconductor wafer includes a substrate and a substrate on the substrate. The method of transferring the mask pattern of the present invention is to make a first mask pattern and a second mask image on the mask ^ and then use the two mask patterns to perform a repeated exposure and a display case. Transfer, so that the photoresist layer corresponds to the first and second photomask patterns, and then the photoresist layer is defined on the photoresist layer with a plurality of non-arranged patterns arranged in an array. The first mask pattern is composed of a plurality of well strips parallel to each other, and each of the opaque strips corresponds to and covers the relative position of the complex vertical patterns, and the second mask pattern is composed of two The phase and opaque strips are staggered to form a grid pattern.
罩以 因此 2 ^本發明係分別利用一 f具有柵攔狀光辜圖案的 <地改善了光學接近效應 525224 五、發明說明（7) 應。而且本發明之圖案轉移方法所形成的光阻圖案會略大 於原始的設計尺寸，如此不但可以補償在後續蝕刻製程中 的損失，甚至會使得後續所形成之電容下層儲存電極的尺 寸變得稍大，抵償下層儲存電極在後續清洗製程中的損 耗，使得完成的電容下層儲存電極的尺寸約略等於設計尺 寸，解決習知技術之尺寸縮小化的缺點。 圖示之簡單說明 圖一為 圖二為 圖二·為 圖四為 圖五為 圖六為 圖七為 圖為 圖九為 圖十為 圖Η— 圖十二 圖十三 圖十四 習知 習知 習知 習知 習知 習知 習知 習知 習知 本發 為本 為本 為本 為本 技術之 技術的 技術形 技術形 技術之 技術的 技術的 技術形 技術形 明之半 發明技 發明技 發明技 發明技 半導體晶片的剖面圖。 光罩圖案示意圖。 成之光阻圖案剖面圖。 成的電容下層儲存電極示意圖。 半導體晶片的剖面圖。 第一光罩圖案示意圖。 第二光罩圖案示意圖。 成之光阻圖案示意圖。 成的電容下層儲存電極剖面圖。 導體晶片的剖面圖。 術的第一光罩圖案示意圖。 術的第二光罩圖案示意圖。 術形成之光阻圖案示意圖。 術形成的電容下層儲存電極剖面 圖Therefore, the present invention uses an < ground with a grid-like light pattern to improve the optical proximity effect 525224. 5. Description of the invention (7). In addition, the photoresist pattern formed by the pattern transfer method of the present invention will be slightly larger than the original design size. This will not only compensate for the loss in the subsequent etching process, but even make the size of the capacitor storage layer formed later to be slightly larger , To compensate for the loss of the lower storage electrode in the subsequent cleaning process, so that the size of the completed capacitor lower storage electrode is approximately equal to the design size, and the shortcomings of the reduction in size of the conventional technology are solved. Brief description of the diagrams Figure 1 is Figure 2 is Figure 2 · Figure 4 is Figure 5 is Figure 6 is Figure 6 is Figure 7 is Figure 9 is Figure 10 is Figure Η-Figure 12 Figure 13 Figure 14 Knowledge, knowledge, knowledge, knowledge, knowledge, knowledge, knowledge, technology, technology, technology, technology, technology, technology, technology, technology, technology A cross-sectional view of a semiconductor wafer. Photomask pattern illustration. Into the photoresist pattern cross-section. Schematic diagram of the lower capacitor storage electrode. A cross-sectional view of a semiconductor wafer. Schematic diagram of the first photomask. Schematic diagram of the second photomask. Schematic photoresist pattern. A sectional view of the storage capacitor lower storage electrode. A cross-sectional view of a conductor wafer. Schematic diagram of the first photomask pattern. Schematic illustration of the second photomask pattern. Schematic photoresist pattern. Section of the capacitor storage electrode
第10頁 525224 五、發明說明（8) 圖示 之 符 號 說 明 先前 •技 術 10 半 導 體 晶 片 12 矽 基 底 13 絕 緣 層 14 接 觸 電 極 15 非 晶 矽 層 16 基 底 17 光 阻 層 19 光 阻 圖 案 20 下 層 儲 存 電極 21 光 罩 23 透 明 基 板 25 光 罩 圖 案 40 半 導 體 晶 片 42 矽 基 底 43 絕 緣 層 44 接 觸 電 極 45 非 晶 矽 層 46 基 底 47 光 阻 層 48 重 覆 曝 光 區 49 光 阻 圖 案 50 下 層 儲 存 電極 51 光 罩 52 透 明 基 板 53 條 狀 圖 案 55 光 罩 56 透 明 基 板 57 條 狀 圖 案 本發明 60 半 導 體 晶 片 62 矽 基 底 63 絕 緣 層 64 接 觸 電 極 65 非 晶 矽 層 66 基 底 67 光 阻 層 69 光 阻 圖 案Page 10 525224 V. Description of the invention (8) Symbols shown in the previous diagram • Technology 10 Semiconductor wafer 12 Silicon substrate 13 Insulating layer 14 Contact electrode 15 Amorphous silicon layer 16 Substrate 17 Photoresist layer 19 Photoresist pattern 20 Lower storage electrode 21 Photomask 23 Transparent substrate 25 Photomask pattern 40 Semiconductor wafer 42 Silicon substrate 43 Insulating layer 44 Contact electrode 45 Amorphous silicon layer 46 Substrate 47 Photoresist layer 48 Repeated exposure area 49 Photoresist pattern 50 Lower storage electrode 51 Photomask 52 Transparent substrate 53 Strip pattern 55 Photomask 56 Transparent substrate 57 Strip pattern The present invention 60 Semiconductor wafer 62 Silicon substrate 63 Insulating layer 64 Contact electrode 65 Amorphous silicon layer 66 Substrate 67 Photoresist layer 69 Photoresist pattern
第11頁 525224 五 、發明說明 (9) 70 電 容 下 層 儲 存 電 極 71 光 罩 72 透 明 基 板 73 條 狀 圖 案 75 光 罩 76 透 明 基 板 78 縱 向 條 狀 圖 案 79 橫 向 條 狀 圖 案 80 透 明 區 發 明 之詳 細 說 明 請參 考 圖 十 至 圖 十 四 ) 圖 十至 圖 十 四 為 利 用 本 發 明 的 微 影 製程 不 意 圖 0 該 微 影 製 程 係用 來 於 —— 半 導 體 晶 片 6 0上 定 義 動態 隨 機 存 取 記 憶 體 之 電 容下， 層 儲 存 電 極 的 尺 寸 與 位 置 〇 如圖 十 所 示 半 導 體 晶 片 60包 含 有 一 基 底 66， 以 及 一 光 阻 層6 7設 於 基 底 6 6的 表 面 〇 基底 66包 含 矽 基 底 62， _ _ 由 矽 氧化 合 物 所 構 成 之 絕 緣 層 63， 複 數 個 由 摻 雜 多 晶 矽 所 構成之接觸電極6 4設於絕緣層6 3之中，以及一用來形成該 |下層儲存電極之非晶矽層6 5設於絕緣層6 3的表面並覆蓋住 I各接觸電極64。其中接觸電極6 4係用來電連接一設於矽基 底6 2表面上之MOS電晶體的汲極（未顯示）以及後續所形成 的電容下層儲存電極70。 如圖十一及圖十二所示，利用本發明方法來進行微影 製程之前，必須先依據設計的積體電路圖案製作光罩7 1以 及光罩7 5。然後分別利用光罩7 1以及光罩7 5進行重複曝光 製程··即先以光罩7 1對半導體晶片6 0進行第一次曝光製Page 11 525224 V. Description of the invention (9) 70 Capacitor lower storage electrode 71 Photomask 72 Transparent substrate 73 Strip pattern 75 Photomask 76 Transparent substrate 78 Vertical strip pattern 79 Horizontal strip pattern 80 Transparent area invention Please explain in detail (Refer to Figures 10 to 14.) Figures 10 to 14 are the intention of using the lithography process of the present invention. The lithography process is used to define the dynamic random access memory capacitor on the semiconductor chip 60. The size and position of the layer storage electrode. As shown in FIG. 10, the semiconductor wafer 60 includes a substrate 66, and a photoresist layer 67 is provided on the surface of the substrate 66. The substrate 66 includes a silicon substrate 62. An insulating layer 63 is formed, a plurality of contact electrodes 64 made of doped polycrystalline silicon are disposed in the insulating layer 63, and a The amorphous silicon layer 65 forming the lower storage electrode is provided on the surface of the insulating layer 63 and covers each contact electrode 64. The contact electrode 64 is used to electrically connect a drain electrode (not shown) of a MOS transistor provided on the surface of the silicon substrate 62 and a capacitor lower storage electrode 70 formed later. As shown in FIG. 11 and FIG. 12, before using the method of the present invention to perform the lithography process, the photomask 7 1 and the photomask 75 must be made according to the designed integrated circuit pattern. Then use the mask 7 1 and the mask 7 5 to repeat the exposure process. That is, first use the mask 7 1 to perform the first exposure process on the semiconductor wafer 60.
第12頁 525224 五、發明說明α〇) … … ^ ’使得光阻層67相對應光罩71之光罩圖案73進行圖案轉 然後再以光罩7 5對半導體晶片6 0進行第二次的曝光製 程，使光阻層6 7相對應該光罩7 5之光罩圖案7 7進行圖案 移。隨後將曝光後的半導體晶片6 〇置於顯影液中，進一 顯影製程。 、/如圖十三所示，在完成顯影製程之後，半導體晶片6q 必須接著進行數次的清洗製程，以去除顯影液以及被顯影 液溶解的正型光阻，使得半導體晶片6〇表面留下複數個以 陣列方式排列的光阻圖案6 9。如圖十四所示，隨後利用光 阻圖案6 9作為硬罩幕，進行一蝕刻製程，垂直向下去除未 被光阻圖案6 9覆蓋的非晶矽層6 5直到絕緣層6 3的表面，以 形成了動態隨機存取記憶體之電容之下層儲存電極7 〇的輪 廓。 - 在上述之本發明方法的實施例中，光罩7 1是由一包含 有玻璃或石英的透明基板72，以及一由鉻膜構成之條狀光 罩圖案73上、下堆疊所構成。光罩圖案73係由複數條彼此 |不相接觸的不透明條7 4所構成，即由彼此平行的不透明條 ! I 74，而且每〆不透明條74均相對應並涵蓋有數個光阻圖案 6 9的相對位置。光罩75包含有一由玻璃或石英構成的透明 基板76，以及，由鉻膜構成之柵欄狀光罩圖案7 7設於透明 i 基板7 6的表面。光罩圖案77係由複數條二相互垂直的不透 I 明區所交錯構成，每一不透明區係由複數條彼此不相接觸Page 12 525224 V. Description of the invention α〇)… ^ 'Make the photoresist layer 67 corresponding to the mask pattern 73 of the photomask 71, and then perform the photomask 75 on the semiconductor wafer 60 a second time. During the exposure process, the photoresist layer 6 7 is pattern-shifted corresponding to the mask pattern 7 7 of the mask 75. Subsequently, the exposed semiconductor wafer 60 is placed in a developing solution, and a developing process is performed. // As shown in Figure 13, after the development process is completed, the semiconductor wafer 6q must be subjected to several cleaning processes to remove the developer and the positive photoresist dissolved by the developer, leaving the surface of the semiconductor wafer 60. A plurality of photoresist patterns 6 9 arranged in an array. As shown in FIG. 14, the photoresist pattern 69 is then used as a hard mask to perform an etching process, and the amorphous silicon layer 65 that is not covered by the photoresist pattern 69 is vertically removed to the surface of the insulating layer 63. To form the outline of the storage electrode 70 under the capacitor of the dynamic random access memory. -In the above-described embodiment of the method of the present invention, the photomask 71 is composed of a transparent substrate 72 containing glass or quartz, and a strip-shaped mask pattern 73 made of a chromium film stacked on and off. The mask pattern 73 is composed of a plurality of non-contact opaque strips 7 4, that is, opaque strips parallel to each other! I 74, and each opaque strip 74 corresponds to and covers several photoresist patterns 6 9 Relative position. The photomask 75 includes a transparent substrate 76 made of glass or quartz, and a fence-shaped photomask pattern 7 7 made of a chrome film is provided on the surface of the transparent i substrate 76. The mask pattern 77 is composed of a plurality of two opaque I transparent areas that are perpendicular to each other. Each opaque area is made of a plurality of opaque areas that are not in contact with each other.
第13頁 525224 五、發明說明（11) 之不透明區所排列構成，且其中一不透明區係涵蓋並相對 應於複數個光阻圖案6 9的相對位置。亦即彼此平行的縱向 不透明條7 7與彼此平行的橫向不透明條7 9交錯可構成光罩 圖案7 7，且縱向不透明條7 8涵蓋並相對應於複數個光阻圖 案6 9的相對位置。 由於光學接近效應，當曝光光源的光束穿過光罩75上 之透明區8 0照射於半導體晶片6 0上之光阻層6 7時，對應於 透明區8 0之四個頂角的光阻層6 7會因為其所獲得的照射能 量不足，即照射不足，進而使得完成的光阻圖案6 9的頂角 略為呈現外突的形狀，並同時使得光阻圖案6 9會較原始的 設計尺寸稍大。稍大的光阻圖案6 9可以補償非晶矽層6 5在 蝕刻製程中的損失，甚至會使得後續所形成之下層儲存電 極7 0的尺今變得較大，藉以抵償下層儲存電極7 0在後續清 洗製程中的損耗，使得最後完成的下層儲存電極70的尺寸 約略等於設計尺寸。 相較於習知的微影製程技術，本發明利用一具有條狀 光罩圖案第一光罩以及具有栅攔狀第二光罩圖案的光罩來 進行重覆曝光，藉以改善了光學接近效應所導致的尺寸端 小化的效應。甚至本發明之圖案轉移方法更有效地利用光 學接近效應的影響來使光阻圖案之四頂角獲得不足的照射 能量，即曝光不足，i而形成一尺寸稍大的下層儲存電 極，來補償非晶矽層在蝕刻製程以及後續之清洗製程中的Page 13 525224 V. Description of Invention (11) The opaque areas are arranged, and one of the opaque areas covers and corresponds to the relative positions of the plurality of photoresist patterns 69. That is, the longitudinal opaque strips 7 7 parallel to each other and the transverse opaque strips 7 9 parallel to each other can form a mask pattern 7 7, and the longitudinal opaque strips 7 8 cover and correspond to the relative positions of the plurality of photoresist patterns 6 9. Due to the optical proximity effect, when the light beam of the exposure light source passes through the transparent area 80 on the reticle 75 and irradiates the photoresist layer 67 on the semiconductor wafer 60, the photoresist corresponding to the four top corners of the transparent area 80 The layer 6 7 will have insufficient irradiation energy, that is, insufficient irradiation, so that the top corner of the completed photoresist pattern 6 9 will have a slightly protruding shape, and at the same time, the photoresist pattern 6 9 will be larger than the original design size. Slightly larger. The slightly larger photoresist pattern 6 9 can compensate the loss of the amorphous silicon layer 65 in the etching process, and even make the size of the lower storage electrode 70 formed later to be larger, thereby compensating the lower storage electrode 7 0 The loss in the subsequent cleaning process makes the size of the finally completed lower storage electrode 70 approximately equal to the design size. Compared with the conventional lithography process technology, the present invention uses a photomask with a stripe mask pattern and a photomask with a barrier-like second mask pattern to perform repeated exposure, thereby improving the optical proximity effect. The effect of minimizing the size ends. Even the pattern transfer method of the present invention makes more effective use of the effect of the optical proximity effect to obtain insufficient irradiation energy at the four corners of the photoresist pattern, that is, underexposure. The crystalline silicon layer is used in the etching process and subsequent cleaning processes.
525224 五、發明說明（12) 損耗，使得最後之下層儲存電極的尺寸及形狀約略等於設 計尺寸及形狀，解決習知技術之尺寸縮小的缺點。 以上所述僅為本發明之較佳實施例，凡依本發明申請 專利範圍所做之均等變化與修飾，皆應屬本發明專利之涵 蓋範圍。525224 V. Description of the invention (12) The loss makes the size and shape of the final lower storage electrode approximately equal to the design size and shape, which solves the disadvantages of the reduction in size of the conventional technology. The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application for the present invention shall fall within the scope of the invention patent.