TW469506B - Pattern transfer method - Google Patents

Abstract

A pattern transfer method transfers plural patterns arranged in array on a photo mask onto a semiconductor wafer. The semiconductor wafer consists of a substrate and a photoresist layer disposed on the surface of the substrate. The method comprises providing a light source and a photo mask to expose the photoresist layer, placing the photo mask between the light source and the photoresist layer, installing a dipole aperture having a common axis between the light source and the photo mask, and exposing the photoresist layer off-axis by the light source. During the exposure process by the light source, the dipole aperture causes patterns transferred to the photoresist layer to elongate in size along the direction parallel to the common axis and to shorten in size along the direction perpendicular to the common axis.

Description

46 95 ϋ 〇 ^ ____________ V. Description of the Invention (ι) Field of the Invention The present invention provides a method for transferring a photoresist pattern, particularly a method for transferring a plurality of photoresist patterns arranged in an array from a photomask to a semiconductor. Method on wafer. Background photolithography is one of the most important steps in semiconductor manufacturing. It can smoothly transfer the integrated circuit's 1 ay out pattern to the semiconductor wafer. In order to form a designed integrated circuit on a semiconductor wafer, a fab must first make a mask and form a designed pattern on the mask. Then the pattern on the mask is transferred by a lithographic process at a certain ratio. To the photoresist layer on the surface of the semiconductor wafer. With the increasing complexity of integrated circuits and integration, the patterns on the light beams are also designed to be smaller and smaller. However, when performing pattern transfer, the critical dimension (CD) of the pattern that can be produced due to the exposure process is limited by the resolution limit (res〇iuti of the optical exposure tool). n limit), so when an exposure process is performed on these high-density mask patterns to form a photoresist pattern, it is very easy to produce an optical proximity effect, so that it is formed on the photoresist layer

46 95 0 6 V. Description of the invention (2) The corner of the proposal (2) will be overexposed (underexposed) or underexposed (underexpose), resulting in resolution loss (resolution 1 〇ss), which will lead to all The reduction of the size of the design pattern makes the pattern on the photomask inconsistent with the pattern on the photoresist layer or a corner rounding effect. The pattern on the photoresist layer will be the same as the original The design dimensions are very different. Please refer to Figures 1 to 6. Figures 1 to 6 are conventional storage node (storage node) capacitors that define a dynamic random access memory (DRAM) on a semiconductor wafer 10. ) Size and location diagram. As shown in FIG. 1, the semiconductor wafer 10 includes a substrate 16 and a photoresist layer disposed on a surface of the substrate 16. The substrate 16 includes a silicon substrate 12, an insulating layer 13 is provided on the silicon substrate 12, and a plurality of node contacts 14 made of doped poly silicon are provided on the insulating layer 13 Among them, an amorphous silicon layer 15 for forming the lower storage electrode is provided on the surface of the insulating layer 13 and covers each contact electrode 14. As shown in Figure 2, before performing the lithography process, it is known to first create a mask 2L according to a designed integrated circuit pattern. The mask 21 includes a transparent quartz substrate 23, and a plurality of matrix methods. The arrayed opaque chromium, and the film pattern 25 is provided on the surface of the transparent substrate 23. As shown in FIG. 3, after the fabrication of the photomask 21 is completed, the photomask 21 is then placed in the exposure system 30, and an exposure process is performed on the semiconductor wafer 10 using the exposure system 30, and then

Page 5 46 95 0 6 V. Description of the invention (3) The exposed semiconductor wafer 10 is placed in a developing solution 'to perform a developing process. The exposure system 30 includes a light source 32 'for exposing the photoresist layer 17 on the surface of the semiconductor wafer 10, a light source shield 3 3 provided between the light source 32 and the semiconductor wafer 10, and a lens 34 provided on the light source shield. 3 3 and the semiconductor wafer 10 are used to focus the light beam emitted by the light source 32 on the mask 21, and the mask 21 is provided between the lens 34 and the semiconductor wafer 10, and a lens 36 is provided. A photoresist layer 17 between the photomask 21 and the semiconductor wafer 10 for focusing the light beam passing through the photomask 21 on the surface of the semiconductor wafer 10. As shown in FIG. 4, the light source shield 33 includes an opening 35 provided at the center of the light source shield 33. As shown in FIG. 5, after the development process, the semiconductor wafer 10 must be cleaned several times to remove the developing solution and the dissolved photoresist, leaving a set of photoresist patterns 19 on the surface of the semiconductor wafer 10. As shown in FIG. 6, an etching process is subsequently performed, and the photoresist pattern 19 is used as a hard mask to vertically remove the amorphous silicon layer 15 not covered by the photoresist pattern 19 until the surface of the insulating layer 13 is formed. The outline of the lower storage electrode 20 of the capacitor of the dynamic random access memory (DRAM). However, in the above-mentioned lithography process, the optical proximity effect will cause the corner rounding of each of the isolated photoresist patterns 19 on the semiconductor wafer 10, that is, the four corner systems of the photoresist pattern 19 Presents a rounded corner instead of a right angle as originally designed. This is because during the exposure, although the light

Page 6 469506 V. Description of the invention (4) The source has the same irradiation energy, but the amount of obtained irradiation energy I on the photoresist layer 17 is not the same. Therefore, the corners of the photoresist pattern 19 on the semiconductor wafer 10 will be overexposed because of obtaining too much irradiation energy, so that a round outline will be formed at the corners of the photoresist pattern 19. Even a more serious optical proximity effect will reduce the size of the photoresist pattern 19, that is, the size of the photoresist pattern 19 is smaller than the original design size and presents an island-like shape. I Because the size of the photoresist pattern 19 is smaller than the original design pattern (the pattern indicated by the dashed I line in Figure 5), the size of the subsequent storage capacitor storage layer 20 | is smaller than the original design size, which reduces the capacitance. The storage capacity of the lower storage electrode 20 can affect the electrical performance of the integrated circuit. SUMMARY OF THE INVENTION The main purpose of the present invention is to provide a method for transferring a photoresist pattern to solve the above problems. i] The present invention provides a photoresist pattern transfer method. The method uses I to transfer a plurality of photoresist patterns arranged in an array from a photomask to an i '1 semiconductor wafer. The semiconductor wafer includes a The substrate and a photoresist: 1 I layer are disposed on the surface of the substrate. The method first provides a light source and a photomask for exposing the photoresist layer, and then places the photomask between the light source and the photoresist I layer. Then, a light source shield having two dipole holes provided on a common axis is disposed between the light source and the mask, so that the light source is off-axis to expose the photoresist layer. When the light source is used for the exposure process, the dipole hole light source is shielded.

Page 7 469506 V. Description of the invention (5) The plate transfers the growth of the photoresist pattern of the photoresist layer in a direction parallel to the common axis direction and shortens the size in the vertical common axis direction. The distance between the photoresist patterns can meet the design size requirements of the next generation semiconductor process. The light source shield can make the light source off-axis irradiate the photoresist layer on the surface of the semiconductor wafer, thereby increasing the size of the photoresist pattern transferred to the semiconductor wafer in a direction parallel to the common axis, and shortening the photoresist pattern. Dimensions perpendicular to the common axis. Since the light source shield can shorten the size of the photoresist pattern in the direction of the common axis, the distance between the photoresist patterns arranged in an array can be shortened by using the present invention, that is, the present invention can shorten the storage of capacitors arranged in an array The distance between electrodes, contact holes or gates to meet the design size requirements of the next generation semiconductor process. For a detailed description of the invention, please refer to FIG. 7 to FIG. 12. FIG. 7 to FIG. 12 are schematic diagrams showing the size and position of a storage electrode of a capacitor lower layer of a dynamic random access memory formed on a semiconductor wafer 40 using the present invention . As shown in FIG. 7, the semiconductor wafer 40 includes a substrate 46, and a photoresist layer 47 is provided on the surface of the substrate 46. The substrate 46 includes a silicon substrate 42, an insulating layer 4 3 made of silicon oxide compound, a plurality of contact electrodes 4 4 made of doped polycrystalline silicon are provided in the insulating layer 4 3, and a lower layer is used to form the lower layer. The amorphous silicon layer 45 of the storage electrode is provided on the surface of the insulating layer 43 and covers each contact electrode 44. Which contacts

Page 8

J 469506 V. Description of the invention (6) The electrode 44 is used to electrically connect a drain (not shown) of a MOS transistor provided on the surface of the Shixi substrate 42 and a capacitor storage electrode 50 formed later. As shown in FIG. 8, before using the method of the present invention for the photolithography process, the light grass 51 must be made according to the designed integrated circuit pattern. The photomask 51 includes a transparent quartz substrate 53 and a plurality of opaque chromium film patterns 55 arranged in a matrix manner on the surface of the transparent substrate 53. Each of the pellicle patterns 55 corresponds to and covers a position of a photoresist pattern 49 to be formed on the surface of the semiconductor wafer. As shown in FIG. 9, after the fabrication of the photomask 51 is completed, the photomask 51 is then placed in the exposure system 60 and an exposure system 60 is used to perform an exposure process on the semiconductor wafer 40 to make the photoresist layer. 4 7 corresponds to the mask pattern 5 5 on the mask 5 1 for pattern transfer. The exposure system 60 includes a light source 62 for exposing a photoresist layer 47 on the surface of the semiconductor wafer 40. A light source shield 6 3 is disposed between the light source 62 and the semiconductor wafer 40. A lens 64 is disposed on The light source shield 63 and the semiconductor wafer 40 are used to focus the light beam emitted by the light source 62 on the photomask 51, which is disposed between the lens 64 and the semiconductor wafer 40 and a lens The photoresist layer 47 is provided between the photomask 5 i and the semiconductor wafer 40 to focus the light beam passing through the photomask 51 on the surface of the semiconductor wafer 40. Please refer to FIG. 10, which is a top view of the light source shield 63 of the present invention. The light source shutter 63 has two dipole holes 65 provided on a common axis. When the photoresist layer 47 on the surface of the semiconductor wafer is exposed by the exposure system 60,

Page 9 i 46 95 0 6 V. Description of the invention (7) The dipole holes 6 5 on the light source shield 6 3 will transfer the growth to the surface of the semiconductor wafer 4 0. The size of the photoresist pattern 49 parallel to the common axis direction ' The size of the photoresist pattern 49 in the direction of the common axis is shortened. As shown in FIG. 11, after the exposure process is completed, the semiconductor wafer 40 must be placed in a developing solution to perform a developing process. After the development process, the semiconductor wafer 40 must be cleaned several times to remove the developing solution and the dissolved photoresist, and a plurality of photoresist patterns arranged in an array manner are formed on the semiconductor wafer 40. . As shown in FIG. 12, an etching process is subsequently performed, using the photoresist pattern 49 as a hard curtain cover to remove the amorphous silicon layer 4 5 that is not covered by the photoresist pattern 4 9 vertically to the surface of the insulating layer 4 3 to form a dynamic The outline of the capacitor underlying storage electrode 50 of the random access memory. Since the dipole hole light source shield 63 can make the light source 62 off-axis irradiate the photoresist layer 47 on the surface of the semiconductor wafer 40, the photoresist pattern 49 transferred to the semiconductor wafer 40 is grown parallel to the common axis. And shorten the size of the photoresist pattern 49 in the direction of the vertical common axis, so that the photoresist pattern 49 formed on the semiconductor wafer 40 finally presents an elliptical pattern. That is, the method of the present invention uses a dipole The hole light source shield 6 3 shortens the size of the photoresist pattern 4 9 in the vertical common direction to reduce the distance between various photoresist patterns 49 arranged in an array or array, thereby enabling smaller and smaller semiconductor processes. The dimensions and positions of array elements such as contact holes, storage nodes, or gates are precisely defined in. ,

Page 10 46 95 0 6 V. Description of the invention (8) Therefore, even if the optical proximity effect makes the photoresist pattern formed on the surface of the semiconductor wafer appear rounded, resulting in loss of resolution and failure to comply with the next-generation semiconductor process Design rule requirements, but the method of the present invention can break through the effect of optical proximity effect, and form a capacitor lower storage electrode and contact hole with a small distance and arranged in an array on the semiconductor wafer. Or the gate process makes the invention meet the design size requirements of the next generation semiconductor process. Compared with the conventional technology, the present invention can shorten the distance between the photoresist patterns arranged in an array. Because the interval A of the oval photoresist pattern formed by using the dipole hole light source shield of the present invention is greater than the interval B of the circular photoresist pattern formed by using a conventional circular hole light source shield (as shown in FIG. 11) Therefore, the present invention can shorten the distance between photoresist patterns arranged in an array, that is, the present invention can shorten the distance between storage capacitors, contact holes, or gate electrodes arranged in an array to meet the next generation of semiconductors. Requirements for the design rule of the manufacturing process β The above are only the preferred embodiments of the present invention. Any equal changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the patent of the present invention.

Page 11 469506 Brief description of the diagrams Brief description of the diagrams Figures 1 to 6 are schematic diagrams of the size and position of the storage electrode of the capacitor underneath the capacitor used to form a dynamic random access memory on a semiconductor wafer. FIG. 7 to FIG. 12 are schematic diagrams illustrating the size and position of a capacitor lower storage electrode for forming a dynamic random access memory on a semiconductor wafer by applying the present invention. Explanation of reference symbols 10 semiconductor wafer 12 silicon substrate 13 insulating layer 14 contact electrode 15 amorphous silicon layer 16 substrate 17 photoresist layer 19 photoresist pattern 20 lower storage electrode 21 photomask 23 transparent substrate 25 photomask pattern 30 exposure system 32 Light source 33 Light source shield 34 Lens 35 On 03 Lens 40 Semiconductor wafer 42 Silicon substrate 43 Insulating layer 44 Contact electrode 45 Amorphous silicon layer 46 Substrate 47 Photoresist layer 49 Photoresist pattern 50 Lower storage electrode 51 Photomask

Page 12 469506 Schematic description

53 Transparent substrate 55 Mask pattern 60 Exposure system 62 Light source 63 Light source shutter 64 Lens 65 Opening 66 Lens

Claims (1)

4 6 9 b U 6 6. Patent application scope 1. A method for transferring a photoresist pattern (pattern) 'This method is used to transfer a plurality of photoresist patterns arranged in an array from a photomask to a semiconductor wafer The semiconductor wafer includes a substrate 'and a photo resist layer disposed on the surface of the substrate. The method includes: providing a light source for exposing the photoresist layer; placing the photomask on the light source; Between the photoresist layer and the photoresist layer, the photomask includes a transparent substrate, and a photo mask pattern is provided on the surface of the transparent substrate. The photomask pattern is composed of a plurality of opaque areas arranged in an array. And each opaque area corresponds to and covers the relative position of a photoresist pattern; and ~ a dipole hole light source shield is disposed between the light source and the mask, and the light source shield has a common axis The two dipole holes above make the light source off-axis to expose the photoresist layer; wherein when the light source is used for the exposure process, the dipole hole light source shield will grow and transfer to the photoresist pattern of the photoresist layer The size in the parallel coaxial axis direction is shortened in the vertical common axis direction. The rule is set at /, the door axis side. 2. The method of the first item of the patent application, wherein the photoresist pattern is used to define a contact hole. , The size and position of the storage electrode (st〇rage node) or the gate (gate). The method of claim 1 in the patent application range, wherein the transparent substrate is made of glass or quartz. Page 14 J 46950b 6. Scope of Patent Application 4. The method of the first scope of patent application, wherein the opaque area is composed of a chromium film. 5. A method for forming a plurality of photoresist patterns arranged in an array on a semiconductor wafer. The semiconductor wafer includes a substrate, and a photoresist layer is provided on the surface of the substrate. The method includes the following steps: providing a light source, For exposing the photoresist layer; placing a photomask between the light source and the photoresist layer, the photomask includes a transparent substrate, and a photomask pattern disposed on the surface of the transparent substrate, the photomask pattern is composed of a plurality of It consists of two opaque areas arranged in an array, and each opaque area corresponds to and covers the relative position of a photoresist pattern; a dipole hole light source shield is placed between the light source and the mask, and the light source The mask has two dipole holes provided on a common axis, so that the light source is off-axis exposed to the photoresist layer; an exposure process is performed to make the photoresist layer corresponding to the mask pattern on the mask for pattern transfer; And performing a development process to form the plurality of photoresist patterns arranged in an array on the semiconductor wafer; wherein in the exposure process, the dipole hole light source The mask shifts the size of the photoresist pattern in the photoresist layer parallel to the common axis direction and shortens the size of the photoresist pattern in the vertical common axis direction. Page 15 4 6 9 5 .0 6 6. Scope of Patent Application 6. For the method of the fifth scope of patent application, the photoresist pattern is used to define the size and position of the contact hole, storage electrode or gate. 7. The method of claim 5 in which the transparent substrate is made of glass or quartz. 8. The method of claim 5 in which the opaque area is formed by a chromium film. Page 16