JP2000047366A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the frequency of defective disconnection caused by the constriction of a photoresist pattern by arranging an auxiliary pattern at the corner part of a photomask so that constricted parts caused at both sides of the photoresist pattern in the width direction are deviated in the direction where they are away from each other. SOLUTION: The prescribed photoresist pattern 4 is transferred by irradiating a photoresist film formed on a semiconductor substrate with exposure light emitted from an exposure light source through the photomask. In such a case, the positions of constrictions NT1 and NT2 relatively formed on sides of a narrow-width pattern part in the width direction are deviated in the direction where they are away from each other. That means, the auxiliary pattern is arranged at the corner part formed by the first pattern part and the second pattern part and photolithography is executed by using the photomask showing a light transmission area 3. The pattern 4 obtained at this time is deviated in the direction where the plane positions of the constrictions NT1 and NT2 are away from each other in a horizontal direction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device technology, and more particularly to a technology effective when applied to an exposure processing technology for transferring a fine pattern.

[0002]

2. Description of the Related Art Exposure processing in a semiconductor device manufacturing process involves exposing a photoresist film on a semiconductor substrate (semiconductor wafer) to exposure light emitted from an exposure light source through a photomask to form a pattern on the photomask. This is to be transferred to a photoresist film. A normal photomask is
A light-shielding region formed by applying a light-shielding film that blocks light transmission on a main surface of a transparent mask substrate, and a light-transmitting region through which light is transmitted by removing the light-shielding film and exposing the mask substrate. And a mask pattern is formed.

Incidentally, not only patterns having a fixed width but also patterns having different widths in one figure exist as patterns constituting a semiconductor device. For example, in a wiring pattern forming a semiconductor device,
There is a pattern portion called a dock bone, which is wider than other portions, at a portion connecting the upper and lower wiring layers. That is, in the pattern, there are a relatively narrow portion and a relatively wide portion, and a planar pattern step occurs in both connecting portions.

However, when such a pattern is transferred to a photoresist film, planar narrowing occurs due to the interference of exposure light in a narrow wiring portion in the vicinity of the planar step portion, causing a wiring disconnection defect. There are issues.
As means for solving such a problem, for example,
Japanese Patent Application Laid-Open No. 1-107530 discloses a method of adding a rectangular or tapered (triangular) auxiliary pattern to a planar step portion (both sides) of a mask pattern. Also, for example, Japanese Patent Application Laid-Open No. 3-89347 discloses a method of adding an auxiliary pattern to a portion distant from the step portion (both sides),
For example, JP-A-6-175348 discloses a method of adding an auxiliary pattern to one side of the step. In each case, the auxiliary pattern is formed so as not to remain on the photoresist film.

[0005]

However, the present inventors have found that the photolithography technology studied by the present inventors has the following problems.

That is, in the above-described technique in which auxiliary patterns having the same size are provided on both sides of the pattern, although the constriction of the photoresist pattern is reduced, the planar positions of the constrictions on both sides of the pattern are substantially the same. In addition, depending on the aberration and defocus of the exposure apparatus, miniaturization of the pattern, introduction of the phase shift method, and the like, the width of the photoresist pattern may not be sufficiently obtained in the constricted portion, which may cause disconnection failure.

[0007] In the method of attaching the auxiliary pattern to only one side, if the step between the relatively narrow pattern and the relatively wide pattern is large, the narrowing may not be sufficiently corrected.

[0008] Further, adding a minute pattern of the resolution limit of the exposure apparatus to the mask pattern has a great problem in mask making. That is, since the current mask inspection apparatus inspects a completed mask pattern using light, the pattern size that can be inspected is limited by the wavelength of the inspection light.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a technique capable of reducing a disconnection defect occurrence rate due to a narrowing of a photoresist pattern transferred by an exposure process.

Another object of the present invention is to provide a technique capable of improving the easiness of inspection of a photomask used in an exposure process.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

The method of manufacturing a semiconductor device according to the present invention is directed to a semiconductor device for transferring a predetermined photoresist pattern by irradiating a photoresist film on a semiconductor substrate with exposure light emitted from an exposure light source via a photomask. In a manufacturing method, in a photoresist pattern in which pattern portions having relatively different widths are integrally formed, positions of constrictions formed on both sides in a width direction of a relatively narrow pattern portion are separated from each other. It is made to shift to.

Further, a method of manufacturing a semiconductor device according to the present invention
A method of manufacturing a semiconductor device for transferring a predetermined photoresist pattern by irradiating a photoresist film on a semiconductor substrate with exposure light emitted from an exposure light source via a photomask, wherein the photomask comprises (a A) a real pattern for transferring the predetermined photoresist pattern, the first pattern portion having a relatively small width; and (b) the real pattern being integrally formed with the first pattern portion. A second pattern portion having a relatively large width; and (c) the first pattern portion such that constrictions generated on both sides in the width direction of the photoresist pattern corresponding to the first pattern portion are shifted in directions away from each other. And an auxiliary pattern disposed at a corner formed by the second pattern portion.

Further, a method of manufacturing a semiconductor device according to the present invention
A method of manufacturing a semiconductor device for transferring a predetermined photoresist pattern by irradiating a photoresist film on a semiconductor substrate with exposure light emitted from an exposure light source via a photomask, wherein the photomask comprises (a A) a real pattern for transferring the predetermined photoresist pattern, the first pattern portion having a relatively small width; and (b) the real pattern being integrally formed with the first pattern portion. A second pattern portion having a relatively large width; and (c) a corner portion on one side formed by the first pattern portion and the second pattern portion so that the shape of the photoresist pattern in the width direction is asymmetric. And an auxiliary pattern arranged at the same position.

Another outline of the invention disclosed in the present application will be briefly described as follows.

The method of manufacturing a semiconductor device according to the present invention is directed to a semiconductor device for transferring a predetermined photoresist pattern by irradiating a photoresist film on a semiconductor substrate with exposure light emitted from an exposure light source via a photomask. In the manufacturing method, the photomask includes: (a) a first pattern portion having a relatively narrow width, which is a real pattern for transferring the predetermined photoresist pattern; A second pattern part formed integrally with the first pattern part and having a relatively large width;
A fifth pattern portion disposed at one corner formed by the pattern portion and the second pattern portion and reflected in the photoresist pattern such that the shape in the width direction of the photoresist pattern is asymmetric; In the fifth pattern portion, a width of the fifth pattern portion in a direction intersecting an extending direction of the first pattern portion is equal to a step between the first pattern portion and the second pattern portion.

Further, according to the present invention, the shape in the width direction of a wiring pattern formed by integrating patterns having relatively different widths is asymmetrical at a connection portion between the patterns having different widths.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. , And the repeated explanation is omitted).

(Embodiment 1) FIG. 1 is a plan view of a main part of a photomask according to an embodiment of the present invention, and FIG. 2 is a plan view of a concept of a photoresist pattern transferred using the photomask of FIG. FIG. 3A is a plan view of a main part of the photomask of this embodiment for explaining the results of the optical simulation, and FIG. 3B is an optical simulation using the photomask of FIG. FIG. 4 to FIG. 6 are plan views of main parts of a modified example of the photomask according to the present embodiment, and FIG. 7 to FIG. , FIG. 11 is a plan view of a main part of the semiconductor device in the present embodiment,
12 and 13 are explanatory views showing an example of the exposure apparatus used in the present embodiment, and FIGS. 19 to 23 are explanatory views of a technique studied by the present inventors.

First, prior to describing the technical concept of the present invention, a photolithography technique studied by the present inventors will be described.

FIG. 19A is a plan view of a mask pattern 50 of a photomask studied by the present inventor. Here, a case where a wiring pattern is formed, for example, is shown. The mask pattern 50 for forming the wiring includes a relatively narrow wiring portion 50A and a relatively wide dock bone portion 50.
B. A connection hole is arranged in the dockbone portion of the transferred wiring. In photolithography, reduction projection exposure is used, and in exposure at a reduction ratio K (K <1), the actual circuit pattern and photoresist pattern are K times larger than the mask pattern. For example, if K = 1/5,
The line width of the mask for obtaining a wiring width of 0.18 μm is 0.9 μm
It is.

Using this photomask, the light source is, for example, a KrF excimer laser having a wavelength λ = 0.248 μm, the numerical aperture of the lens NA = 0.6, the coherent coefficient σ = 0.3, and the reduction ratio K = 1/5. FIG. 19B is a conceptual diagram of a resist pattern obtained when lithography is performed by the exposure apparatus described above. The photoresist pattern 51 has a relatively narrow wiring pattern portion 51A and a relatively wide dock bone pattern portion 51B. The dock bone pattern portion 51B is often wide in order to allow a margin for overlapping the connection hole and the wiring. However, in the step region where the thickness of the wiring changes, the photoresist pattern 51 in the thin portion of the wiring is used. Neck NT1 and NT2 occur. The constrictions NT1 and NT2 may cause a wiring disconnection failure in a subsequent wiring forming process, or may be caused by variations in exposure conditions.
This causes the photoresist pattern 51 itself to break.

The effect of the photomask in this case will be described with reference to an optical simulation. This is to calculate contour lines of light intensity obtained on a photoresist film based on a mask pattern and optical constants of an exposure apparatus. FIG.
In the photomask pattern 50 of the photomask (a), the wiring width W1 was 0.18 μm and the dogbone size W2 was 0.4 μm at reduced values. As the optical constants, it is assumed that λ = 0.248 μm, NA = 0.6, σ = 0.3, defocus = −0.5 μm, and spherical aberration. In the subsequent simulations, the same optical constants are assumed.

FIG. 20B shows an optical image obtained by calculating such a photomask pattern. The contour lines of the relative intensities of light 0.35 and 0.49 are shown. The light intensity defines the light transmittance of a sufficiently large pattern as 1. The contour line having a light intensity of 0.35 shows the photoresist pattern actually obtained, and the wiring width W1 is 0.18 μm at a position sufficiently distant from the dog bone. However, the wiring is constricted near the dog bone, and Lmin is 0.154 μm. Also the light intensity
The contour line of 0.49 is broken, indicating that the light intensity is weak at this portion. Therefore, there is a problem that the photoresist film is reduced during development and the margin during wiring processing is reduced.

Such a problem has been remarkable due to miniaturization of the pattern. In particular, in a peripheral circuit and a logic circuit of a memory, the above problem is likely to occur because the pattern width is set to be equal to or less than the wavelength of the exposure light in order to achieve high integration and high performance. It also occurs due to aberration and defocus of the exposure device. Further, when a phase shift photolithography technique is used as a photolithography technique, a serious problem occurs. The phase shift photolithography technology uses a light interference effect by manipulating the phase of transmitted light to improve the resolution of fine patterns. This is also to make the exposure light coherence higher. At present, in photolithography, a pattern having a wavelength equal to or less than the light wavelength of an exposure apparatus is formed by using, for example, a phase shift method. As an example, a 1 Gb DRAM (Dynamic Random
In Access Memory, an exposure device using a KrF excimer laser with a wavelength of 0.248 μm as a light source is required to form word lines and data lines with a width of 0.16 μm, and a line and space pattern in which simple straight lines are repeated Uses a phase shift method which has a large effect.

To solve this problem, an exposure method using various auxiliary patterns has been proposed.
FIG. 21A shows a method of adding a rectangular auxiliary pattern 52a to a step portion of a photomask pattern 52, which is disclosed in Japanese Patent Application Laid-Open No. 1-107530. That is, FIG.
21A, a relatively narrow pattern 52b and a relatively wide pattern 52c are connected in the horizontal direction in FIG. 21A, and rectangular auxiliary patterns 52a are provided on both sides of the connection pattern 52b. Is provided. At this time, the length LC50 of both the auxiliary patterns 52a is about λ / (NA · K). Also, the width WC50 of both auxiliary patterns 52a is made smaller than the value obtained by dividing the resolution limit by K so that the auxiliary patterns 52a themselves do not remain in the resist pattern. Here, 2
The dimensions of the two auxiliary patterns 52a are the same. Note that the broken line in FIG. 21A shows the mask pattern in the design of the photomask 1 disassembled into constituent patterns, and is not formed on the actual photomask.

By doing so, as shown in FIG. 21B, the constrictions NT1, N1 of the photoresist pattern 53 are formed.
The size of T2 is reduced as compared with the case where FIGS. 19A and 20A are used. Here, an ideal resist pattern obtained by multiplying the mask pattern by K is indicated by a broken line. Further, the minimum wiring width at the narrow portion of the photoresist pattern 53 is defined as Lmin.

The effect of the photomask in this case will be described with reference to an optical simulation. FIG. 22A shows a mask pattern 52. LC1 = 0.25 with reduced value
μm, WC1 = 0.05 μm. An optical image obtained by calculation for such a mask pattern 52 is shown in FIG.
(B). The constriction of the contour at the light intensity of 0.35 is reduced, and Lmin is improved to 0.171 μm. In addition, contour lines having a light intensity of 0.49 are also connected. Therefore, it is understood that the disconnection is hardly caused by the auxiliary pattern.

Other structures of the photomask having the auxiliary pattern are shown in FIGS. FIG.
Japanese Patent Laid-Open Publication No. 1-107530 discloses a method of adding a tapered auxiliary pattern 52a to a step. FIG. 1B shows a method of adding an auxiliary pattern 52a to a portion away from a step, which is disclosed in Japanese Patent Application Laid-Open No. 3-89347. (C) is a method disclosed in JP-A-6-175348, in which an auxiliary pattern 52a is added to one side of a step.
In any case, the auxiliary pattern 52a is formed so as not to remain in the photoresist film. Note that the broken line in FIG. 23 has the same meaning as in FIG.

However, as shown in FIGS. 21 (a) and 21 (b), in the method in which the auxiliary patterns 52a of the same size are added to both sides of the pattern, the constricted plane positions of the photoresist patterns are substantially the same. In some cases, the width of the photoresist pattern cannot be sufficiently obtained in the narrow portion due to aberrations and defocus of the exposure apparatus, miniaturization of the pattern, introduction of the phase shift method, and the like. The width WC50 of the auxiliary pattern 52a has an optimum value. This is because, if it is too small, the effect of compensating for the constriction is small, and if it is too large, excessive correction occurs in which the resist pattern becomes constricted due to the step of the auxiliary pattern itself. The constrictions NT1 and NT2 in FIG. 21B are constrictions due to this overcorrection. The optimum value of the width WC50 is mainly determined by the optical constants of the exposure apparatus such as λ, NA, and K, but is also affected by unpredictable lens aberration and defocus. Therefore, it is difficult to completely eliminate the constriction due to overcorrection. Therefore, it is important to reduce the influence of the constriction due to the overcorrection.

As shown in FIG. 23C, in the method of providing the auxiliary pattern 52a only on one side, the relatively narrow pattern 52b and the relatively wide pattern 5b are used.
When the level difference from 2c is large, there is a possibility that constriction cannot be sufficiently corrected.

Further, adding a minute pattern, which is about the resolution limit of an exposure apparatus, to a mask pattern has a significant problem in mask preparation. That is, for example, the width on the mask of the auxiliary pattern such that the width of the resist pattern becomes 0.05 μm is 0.25 μm, where K = 1/5. Since the photomask is created using an electron beam lithography system, 0.25
It is possible to draw a size of μm. However, the current mask inspection equipment inspects the completed mask pattern using light, so the pattern size that can be inspected is limited by the wavelength of the inspection light. Is done. if,
0.25μm even if excimer laser is used for inspection light
It is difficult to completely inspect the auxiliary pattern. Therefore, it is necessary to increase the size of the auxiliary pattern to some extent in order to surely inspect the auxiliary pattern. At this time, the width WC50 becomes larger than the above-mentioned optimum value, and constriction due to overcorrection occurs. In this case, too, it is important to form the auxiliary pattern while reducing the influence of the overcorrection.

Next, an embodiment using the technical concept of the present invention will be described.

FIG. 1 shows a photomask 1 according to the first embodiment.
FIG. The photomask 1 is for transferring, for example, a wiring pattern, and a hatched area indicates a light-shielding area on which a light-shielding film 2 is formed, and a non-hatched area indicates that the light-shielding film 2 is removed. The light transmitting region 3 is shown in which the transparent mask substrate 1A of the photomask 1 is exposed. The broken lines indicate the light transmitting regions 3 in the design of the photomask 1 by the patterns P1 to P4.
This is not an actual one formed on the photomask 1. That is, the light transmission region 3 is
A strip-shaped pattern P1 extending in the horizontal direction in FIG. 1, a square pattern P4 connected to its end, and a pattern P1
, P4 have relatively small rectangular patterns P2 and P3 arranged at the corners formed by the sides of P4 and P4.

The patterns P1 and P2 are actual patterns corresponding to the integrated circuit pattern to be actually transferred to the photoresist film, and the patterns P3 and P4 are the patterns not to be transferred to the photoresist film. Moreover, the auxiliary pattern is such that the independent pattern is not transferred to the photoresist film. The mask substrate 1 is made of, for example, transparent synthetic quartz having a light transmittance of about 100%. The light-shielding film 2 is a film that generally forms a region having a light transmittance of approximately 0% (typically 1% or less), and is, for example, a single film of chromium or a laminated film of chromium and chromium oxide. ing.

In the present embodiment, the lengths of the small rectangular patterns P3 and P4 (length in the horizontal direction in FIG. 1)
Are different. The length LC1 of the relatively smaller pattern P3 is, for example, about λ / (2NA · K). For example, when λ = 0.248 μm, NA = 0.6, and K = 1/5,
LC1 is about 1 μm. Further, the length LC2 of the relatively larger pattern P4 is set to be longer than, for example, the length LC1 of the pattern P3 = λ / (2NA · K). Also,
The widths WC1, WC2 of the patterns P3, P4 are
3, so that P4 itself does not remain in the photoresist film and is smaller than the resolution limit, for example, smaller than the value obtained by dividing the resolution limit by K. For example, λ = 0.248 μm, K = 1/5
In this case, WC1 = WC2 = 0.25 .mu.m.

FIG. 2 is a conceptual diagram of a photoresist pattern obtained when photolithography is performed by an exposure apparatus using the photomask 1. The exposure conditions in this case are as follows, for example. Light source is wavelength λ = 0.2
48 μm KrF excimer laser, numerical aperture NA of lens
= 0.6, coherent coefficient σ = 0.3, reduction ratio K = 1/5
It is. The broken line indicates the light transmission region 3 in FIG.

When the center line of the pattern is a virtual straight line disposed so as to pass through the center of the pattern P1 in the width direction of the photoresist pattern 4, the center line may be vertically symmetrical. Further, there is a case where the position becomes asymmetric at a position corresponding to the auxiliary pattern. The pattern width of the photoresist pattern 4 (a portion having a small line width corresponding to the pattern P1) is assumed to be 0.18 μm, for example (that is, λ / (2NA) or less). By arranging the auxiliary pattern on the photomask 1 (see FIG. 1) as described above, the constriction (a narrow pattern portion) of the photoresist pattern 4 is reduced, but the constrictions NT1 and NT2 of the excessive correction remain. Would. However, according to the present embodiment, the plane positions of the constrictions NT1 and NT2 are shifted in a direction in which the constrictions NT1 and NT2 are separated from each other in the horizontal direction in FIG. Therefore, even if each neck NT1, NT
Even if the size of 2 is the same as that of the above-described technology, the minimum wiring width Lmin at the constricted portion of the wiring is larger than that of the above-described technology (FIG. 21). That is, according to the present embodiment, it is possible to increase the reliability of processing when forming a pattern having a width equal to or less than the exposure wavelength. In particular, the length L
The difference between C2 and length LC1 is λ / (2NA · K) or more (λ
= 0.248 μm, NA = 0.6, and about 1 μm for K = 1/5), the constrictions NT1 and NT2 are shifted, and the effect of improving Lmin is large.

The effect of the auxiliary pattern in the photomask 1 of the present embodiment will be described with reference to an optical simulation. FIG. 3A is a plan view of a main part of the photomask 1 used for describing the effect of the optical simulation. In the photomask 1, for example, the auxiliary pattern is added to a pattern for transferring a wiring and a dock bone. Length LC with reduced value
2-Length LC1 = 0.25 µm, width WC1 = width WC2 = 0.2.
It was set to 05 μm. The square pattern Pc in the center of FIG. 3A shows a pattern of connection holes for connecting the upper and lower layers.

In this case, as shown in FIG. 3B, the constriction of the contour line (outside) at the light intensity of 0.35 is further reduced as compared with the case where the auxiliary pattern of the above-described technique is added.
Has been improved to, for example, 0.175 μm. In addition, a contour line (inside) having a light intensity of 0.49 is also connected. Therefore, according to the present embodiment, it is understood that disconnection is more unlikely to occur.

Such a photomask 1 is not limited to the structure shown in FIG. 1, but can be variously modified.
For example, the structure shown in FIG. 4 or FIG. In addition,
The broken lines in FIGS. 4 and 5 have the same meaning as the broken lines in FIG.

In FIG. 4, the patterns P3 and P4 functioning as auxiliary patterns have a step-like planar shape and are added to both corners formed by the sides of the pattern P1 and the pattern P2, and the length LC1 and the length LC2 are added. By using different values, the effect of shifting the constriction is obtained in the same manner as described above. Here, the pattern P3, P4 has a stepped shape in which the width becomes larger as approaching the relatively large pattern P2. In this case, since the widths of the patterns P3 and P4 are gradually increased, when the difference between the widths of the patterns P1 and P2 is large, the effect of reducing the constriction is great. Also in this case, the difference between the length LC2 and the length LC1 is, for example, λ / (2NA ·
K) Given the above, the constrictions NT1 and NT2 shown in FIG.
And the effect of improving Lmin is large.

In FIG. 5, the patterns P3 and P4 functioning as auxiliary patterns are formed, for example, in a triangular planar shape.
Further, the width is gradually increased as approaching the large pattern P2, and is added to both corners formed by the sides of the pattern P1 and the pattern P2 so that the length LC1 and the length LC2 have different values. In this case as well, the effect of shifting the constriction is obtained in the same manner as described above, and the above-described technique (FIG.
Lmin can be made larger than in the case of (a)). Also in this case, the difference between the length LC2 and the length LC1 is λ /
(2NA · K) In this case, the constriction NT shown in FIG.
1 and NT2 are shifted, and the effect of improving Lmin is large.

Further, the light transmitting region 3 and the light shielding film 2 in FIG. 1 may be reversed as shown in FIG. In this case, the light shielding film 2 has the patterns P1 to P4. Otherwise, the description is the same as that described above, and thus the description is omitted. In addition,
This structure can also be applied to FIGS.

Next, the technical idea of the present invention is described, for example, by DRA
A specific example of a manufacturing method applied to an M (Dynamic Random Access Memory) will be described with reference to FIGS.

FIG. 7 is a cross-sectional view of a main part during a manufacturing process of a semiconductor device. Reference numeral 5 denotes a semiconductor substrate (semiconductor wafer) made of, for example, silicon single crystal, reference numeral 6 denotes an n-type buried well, and reference numeral Reference numerals 7NW1 and 7NW2 denote n-wells, reference numerals 7PW1 and 7PW2 denote p-wells, and reference numeral 8 denotes a groove-shaped separating portion. The p-well 7PW2 is surrounded and electrically isolated by the buried n-type well 6 and the n-well 7NW2. Thereby, p-well 7PW2
The transmission of noise from the semiconductor substrate 1 can be suppressed, and the potential of the p-well 7PW2 can be stabilized. The n-type buried wells, n-wells 7NW1, 7N
For example, phosphorus or arsenic is implanted in W2, and boron or boron difluoride is implanted in p-wells 7PW1 and 7PW2. In addition, the groove-type separation portion 8 is formed by burying a separation insulating film 8b made of, for example, a silicon oxide film in a separation groove 8a dug in the semiconductor substrate 1.

By subjecting the semiconductor substrate 1 to a gate oxidation process, a gate insulating film 9i made of, for example, a silicon oxide film is formed on the main surface of the semiconductor substrate 1. Although not particularly limited, after the gate insulating film 9i is formed, the semiconductor substrate 1 is made of NO (nitrogen oxide) or N
Nitrogen may be segregated at the interface between the gate insulating film 9i and the semiconductor substrate 1 by performing a heat treatment in a ₂ O (nitrous oxide) atmosphere (oxynitriding treatment). When the thickness of the gate insulating film 9i is reduced to about 7 nm, distortion generated at the interface between the semiconductor substrate 1 and the semiconductor substrate 1 due to a difference in thermal expansion coefficient becomes apparent, and hot carriers are generated. Since the nitrogen segregated at the interface with the semiconductor substrate 1 relaxes the distortion, the oxynitridation can improve the reliability of the extremely thin gate insulating film 9i.

Subsequently, a conductor film 1 for forming a gate electrode made of, for example, low-resistance polysilicon is formed on the gate insulating film 9i.
0 is formed by a CVD method or the like, and a cap insulating film 11 made of a silicon nitride film is formed thereon by a CVD method or the like. However, the conductor film 10 is not limited to the low-resistance polysilicon film, but can be variously modified. For example, a tungsten silicide film or the like may be formed on the low-resistance polysilicon film, or a metal film such as tungsten may be formed on the low-resistance polysilicon film via a barrier metal film such as tungsten nitride or titanium nitride. It may be formed.

Thereafter, after a photoresist film is applied on the cap insulating film 11, the gate electrode pattern is transferred to the photoresist film using the above-described photomask 1 (see FIG. 1 and the like), and the photoresist pattern 4 is formed. Form.
Subsequently, by using the photoresist pattern 4 as an etching mask, the cap insulating film 11, the conductor film 10, and the gate insulating film 9i are patterned by dry etching technology, thereby forming the gate electrode 1 as shown in FIG.
0g and the word line WL are formed. The gate electrode 10g in the memory cell region is also a part of the word line WL. In the present embodiment, the above-described photomask 1 (see FIG. 1 and the like) is used for this photolithography. Subsequently, as shown in FIG. 9, a p-channel type MIS • FET Q is formed on the semiconductor substrate 1 in accordance with a normal DRAM manufacturing method.
A p-channel and n-channel MIS-FET Qn and a memory cell selection MIS-FET Qs are formed. The code 1
2n is an n-type semiconductor region for source / drain, 12p
Is a p-type semiconductor region for source / drain, 13n is an n-type semiconductor region for well power supply, 13p is a p-type semiconductor region for well power supply, and 14n is a memory cell selection MIS.
An n-type semiconductor region 15 for the source / drain of the FET Qs; an insulating film 15 made of, for example, a silicon nitride film;
Reference numerals 6 and 17 denote insulating films made of, for example, a silicon oxide film;
Is a plug made of, for example, low-resistance polysilicon, 19 is a wiring, 19BL is a bit line, and 20 is a connection hole formed in an insulating film and connects the wiring 19 and the bit line 19BL to the semiconductor substrate 1. . The wiring 19 and the bit line 19BL are made of, for example, tungsten or the like, and the above-described photomask 1 (see FIG. 1 and the like) is also used in the photolithography for patterning these. Thereafter, as shown in FIG.
Form one. The capacitor 21 is formed, for example, in a crown shape, has a lower electrode 21 a, a capacitive insulating film 21 b on the exposed surface side thereof, and a plate electrode 21 c on the surface thereof, and has an insulating film deposited on the insulating film 17. It is formed so as to be buried in the capacitor opening region 23 opened in the film 22. The lower electrode 21 a is made of, for example, low-resistance polysilicon and is connected to the plug 18 through a connection hole 25 formed in the insulating film 24, and through this, the n ⁻ type semiconductor region 1 of the memory cell selection MIS • FET Qs is formed.
4n. The capacitance insulating film 21b
For example, it is composed of a laminated film of a silicon nitride film and a silicon oxide film, tantalum oxide, or the like, but is not limited thereto, and can be variously modified, for example, lead zirconium titanate, barium titanate, or zirconium titanate. It may be made of a ferroelectric material such as lanthanum lead.

The peripheral circuit formed in this manner, in particular, an n-channel MIS transistor in a direct peripheral circuit such as a word line driver circuit or a sense amplifier circuit, for example.
FIG. 11 shows a plan view of the FET Qn. In this direct peripheral circuit, the photomask 1 of the present embodiment is used because the line width and the interval are smaller than those of the other peripheral circuits in order to match the memory cells. In particular, the line width is smaller than the resolution limit (in this embodiment, the exposure light source is KrF (wavelength 0.24).
8 μm), for example, 0.25 μm or less)
Applied when transferring patterns.

Here, the wiring 19 around the connection hole 20a for electrically connecting the wiring 19 and the semiconductor region 12n, the wiring 19 around the connection hole 20b for electrically connecting the wiring 19 to the gate electrode 10g, and the like. The present invention is applied to the gate electrode 10g. Although the pattern of the gate electrode 10g and the wiring 19 has a constriction in the vicinity of the dockbone portion (wide portion), the constriction position is displaced in a plane, so that no disconnection occurs. Therefore, a highly reliable MIS • FET Qn can be formed. The width of the gate electrode 10g is, for example, about 0.25 μm. The width of the wiring 19 is, for example, 0.18 to 0.20 μm at the wiring portion (a relatively narrow portion), and is, for example, 0.4 μm at the dock bone portion (a relatively wide portion). It is about. The distance between the adjacent wirings 19 is, for example, about 0.18 to 0.2 μm.

The wiring 19A is a power supply wiring for supplying, for example, a high-potential power supply voltage or a low-potential power supply voltage (for example, GND (0 V)). The auxiliary pattern of the present embodiment is not added to the actual pattern for transferring the power supply wiring 19A. This is wiring 1 for power supply
This is because 9A is formed to be relatively wide, and the above-described constriction problem does not occur.

Next, an example of the exposure apparatus used in this embodiment will be described. As shown in FIG. 12, the reduction projection exposure apparatus 26 used in the present embodiment has an adsorption table 26a for adsorbing and holding a semiconductor substrate (semiconductor wafer) 5, and in this exposure processing, a step-and-repeat operation is performed. The exposure operation is performed according to the method. The suction table 26a has an X-axis moving table 26b that moves in the horizontal direction, and a Y-axis moving table 26c that moves the suction table 26a in a horizontal direction perpendicular to the X-axis moving table 26b.
And is movable up and down by a Z-axis moving table 26d. The exposure light source 26e is capable of emitting, for example, a KrF excimer laser, and is assembled to the condenser mirror 26f. Exposure light source 26e
Is, for example, a normal KrF excimer laser light source,
An oblique illumination light source may be used. Note that the ordinary light source is illumination that is non-deformed illumination and has a light intensity distribution that is relatively uniform within the light source plane. The oblique illumination is illumination in which the illuminance at the center of the light source is reduced, and includes a super-resolution technique using multipole illumination such as annular illumination, quadrupole illumination, and quadrupole illumination, or a pupil filter equivalent thereto. Further, an i-line (wavelength 365 nm) may be used as an exposure light source.

In the reduction projection exposure device 26, the KrF excimer laser light emitted from the exposure light source 26e is applied to a plane reflection mirror 26g1, a shutter 26h, a fly-eye lens 26i, an aperture 26j, a band-pass filter 26k.
Irradiates the plane reflecting mirror 26g2 through the mirror. The light transmitted through the fly-eye lens 26i has its partial coherent coefficient (σ value) adjusted by an aperture 26j, and illumination light other than exposure light is cut by a bandpass filter 26k. The exposure light applied to the plane reflection mirror 26g2 is further applied to the photomask 1 via a mask blind 26m and a condenser lens 26n. The photomask 1 is held by a mask holder 26p. This mask holder 26p can be finely moved in the vertical direction in FIG. In the plane area of the photomask 1, the area to be transferred to the semiconductor substrate 5 is the exposure light that has passed through the photomask 1 by the mask blind 26 m.
Irradiation is performed on the photoresist film on the semiconductor substrate through 6q.

The exposure apparatus is not limited to the above-described step-and-repeat type exposure apparatus, but can be variously modified. For example, a step-and-scan type exposure apparatus may be used.

The step-and-scan method transfers a pattern while relatively moving a semiconductor substrate and a photomask in opposite directions. That is, for example, FIG.
As shown in FIG. 3, the exposure light 28 of the reduction projection exposure device 27
Is formed on the photomask 1 after being formed by the slit 27a. Since the exposure light 28 and the exposure light source are the same as described above, the description will be omitted. The photomask 1 is held on a mask stage 27b. Exposure light transmitted through the photomask 1 is transmitted to the reduction projection lens 27c.
Irradiates the photoresist film on the main surface of the semiconductor substrate 5 through the. In the reduced projection exposure apparatus 27, the pattern is transferred into the semiconductor chip 5C of the semiconductor substrate 5 while the photomask 1 and the semiconductor substrate 5 move relatively in opposite directions.

According to the first embodiment, the following effects can be obtained.

(1) In photolithography, when transferring a fine pattern having a width equal to or smaller than the exposure wavelength and having a partially different line width and a planar step, the vicinity of the step is considered. Since the amount of constriction generated in the wiring can be reduced, it is possible to reduce the incidence of disconnection failure of the wiring.

(2) According to the above (1), wiring can be miniaturized, and it is possible to promote high integration, high functionality, and miniaturization of a semiconductor device.

(3) According to the above (1), the yield and reliability of the semiconductor device can be improved.

(Embodiment 2) FIG. 14 is a plan view of a main part of a photomask according to another embodiment of the present invention, and FIG. 15 is a conceptual view of a photoresist pattern transferred using the photomask of FIG. FIG. 16A is a plan view, and FIG. 16A is a main part plan view of a modified example of the photomask according to the second embodiment.
FIG. 17 is a plan view of an essential part of a photomask having the structure of the present embodiment, and FIG. 17 (b) is a plan view of the photomask having the structure of the present embodiment. FIG. 18 is an explanatory diagram showing a light intensity distribution as an optical simulation result, and FIG. 18 is a plan view of a main part of a semiconductor device according to another embodiment of the present invention.

In the second embodiment, a technique for facilitating inspection of a photomask will be described. As shown in FIG. 14, in the photomask 1 of the second embodiment, a pattern P5 functioning as an auxiliary pattern is provided on one side of both corners formed by the sides of the patterns P1 and P2. The broken line in FIG. 14 has the same meaning as the broken line in FIG. The pattern P5 in this case is made larger than the resolution of the photomask inspection device. For example, assuming that the length LC1 and the width WC1 of the pattern P5 are λd / λd, where the wavelength λd of the inspection light used for the photomask inspection apparatus and the numerical aperture of the lens are NAd.
(2NAd) or more. For example, λd = 0.357 μm, N
When Ad = 0.6, the length LC1 = WC1 = about 0.3 .mu.m.

When the size of the pattern P5 functioning as an auxiliary pattern is larger than the resolution of the photomask inspection apparatus, the photomask inspection can be performed reliably. Therefore, in the inspection, if an auxiliary pattern is not created due to a defect in the photomask 1,
Can be detected as an error. Therefore, according to the second embodiment, the reliability of the photomask 1 having the pattern P5 functioning as an auxiliary pattern can be improved.

FIG. 15 is a conceptual diagram of a photoresist pattern using the photomask 1. The exposure conditions are the same as in the first embodiment. The broken line in FIG. 15 indicates the light transmission region 3 in FIG. In the case of the photomask 1, since the step of the pattern P5 is large, the pattern is overcorrected and the photoresist pattern 4 is narrowed.
T4 occurs, but the constriction NT4 due to the step between the original pattern P1 and the pattern P2 and the constriction NT3 due to the step between the pattern P1 and the pattern P5 are displaced in the horizontal direction of FIG. Lmin can be improved as compared with the case where P5 is not added.

Further, in this case, the photoresist pattern 4 is such that if a straight line disposed so as to pass through the center in the width direction of the pattern P1 is set as the center line of the pattern, the upper and lower sides of the center line correspond to the auxiliary pattern. It is asymmetric at the corresponding location. That is, the pattern P5 as the auxiliary pattern in the second embodiment remains as a part of the photoresist pattern 4.

Such a photomask is, for example, shown in FIG.
The structure shown in FIG. Note that the broken line in FIG. 16 has the same meaning as the broken line in FIG. In FIG. 16, width WC of pattern P5 functioning as an auxiliary pattern of the second embodiment is shown.
1 is made longer than the case shown in FIG. 14 to equal the original step difference between the relatively narrow pattern P1 and the relatively wide pattern P2. In this case, since the number of vertices of the pattern figure can be reduced, there is an advantage that the data amount at the time of designing the mask pattern can be reduced. That is, the pattern data processing of the photomask 1 can be facilitated.

The effect of the auxiliary pattern in the photomask 1 of FIG. 16 will be described with reference to an optical simulation. FIG. 17A is a plan view of a main part of the photomask 1 used for describing the effect of the optical simulation. In the photomask 1, for example, an auxiliary pattern (pattern P5) of the second embodiment is added to a pattern for transferring wirings and dock bones. With reduced values, for example, LC1 = 0.25 μm, WC1 =
0.11 μm (0.55 μm on the photomask 1, which can be inspected). In this case, as shown in FIG. 17B, the constriction of the contour line (outside) at the light intensity of 0.35 is smaller than that without the auxiliary pattern of the above-described technique, and Lmi
n has improved to 0.170um. In addition, a contour line (inside) having a light intensity of 0.49 is also connected. Therefore, it is understood that the use of the photomask 1 according to the second embodiment makes it difficult to disconnect the wiring. Note that the photomask structure in which the light transmitting region and the light shielding region are inverted as shown in FIG. 6 may also be used in the second embodiment.

FIG. 18 shows a layout of a MIS • FET formed using such a photomask 1. The application places of the present invention are the same as those described in FIG. Here, the pattern shapes above and below a virtual straight line passing through the center of the width of the wiring 19 are asymmetric. The other dimensions and structure are the same as those described with reference to FIG. Note that a specific method of manufacturing such a semiconductor device is the same as that of the first embodiment, and a description thereof will be omitted.

As described above, according to the second embodiment, the following effects can be obtained in addition to the effects obtained in the first embodiment.

(1) Since the inspection of the auxiliary pattern added to the photomask 1 can be easily performed,
A highly reliable photomask 1 can be manufactured. Therefore, by manufacturing a semiconductor device using the photomask 1, it is possible to improve the yield and reliability of a highly integrated semiconductor device having a fine pattern.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist thereof. Needless to say,

For example, in the first and second embodiments,
Although the case where the capacitor for storing information is a crown type has been described, the present invention is not limited to this, and various changes can be made. For example, a fin type may be used.

A salicide structure may be employed as the structure of the MIS • FET. That is, MIS-FET
A conductive film such as tungsten silicide may be formed on the upper surface of the source / drain semiconductor region and the upper surface of the gate electrode.

The semiconductor wafer is not limited to a single film of silicon single crystal but can be variously changed.
For example, an epitaxial wafer having a thin (eg, 1 μm or less) epitaxial layer formed on the surface of a silicon single crystal semiconductor substrate, an SOI (Silicon On Insulator) wafer having a semiconductor layer for element formation on an insulating layer, or gallium arsenide As described above, a compound semiconductor wafer may be used.

In the above description, the invention made mainly by the inventor has been described in terms of the DRA which is the field of application which has been the background.
M has been described as being applied to the manufacturing technology, but the present invention is not limited to this. For example, an SRAM (Static R)
andom Access Memory) or flash memory (EE
PROM: Electronically Erasable Programmable ROM)
And the like, and a memory-logic mixed circuit in which a semiconductor memory circuit and a logic circuit are provided on the same semiconductor substrate. Further, the present invention can be applied to a semiconductor device in which a bipolar transistor is provided on a semiconductor substrate.

[0077]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, since the amount of constriction in the vicinity of the connection portion of a pattern having a relatively different width can be reduced, it is possible to reduce the incidence of disconnection failure of the pattern.

(2) According to the above (1), the pattern can be miniaturized, and the integration, function and size of the semiconductor device can be promoted.

(3) According to the above (1), the yield and reliability of the semiconductor device can be improved.

(4) According to the present invention, it is possible to improve the easiness of inspection of the auxiliary pattern added to the photomask, so that a highly reliable photomask can be manufactured.

(5) According to the above (4), by manufacturing a semiconductor device using the photomask, it is possible to improve the yield and reliability of a highly integrated semiconductor device having a fine pattern. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a plan view of a main part of a photomask according to an embodiment of the present invention.

FIG. 2 is a plan view of the concept of a photoresist pattern transferred using the photomask of FIG. 1;

FIG. 3A is a plan view of a main part of a photomask according to a first embodiment for explaining an optical simulation result, and FIG. 3B is an optical simulation using the photomask of FIG. FIG. 9 is an explanatory diagram showing the resulting light intensity distribution.

FIG. 4 is a plan view of a main part of a modified example of the photomask in the first embodiment.

FIG. 5 is a plan view of a main part of a modified example of the photomask in the first embodiment.

FIG. 6 is a plan view of a principal part of a modified example of the photomask in the first embodiment.

FIG. 7 is a fragmentary cross-sectional view of the semiconductor device of the present embodiment during a manufacturing step thereof;

8 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 7;

9 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 8;

10 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 9;

FIG. 11 is a plan view of relevant parts of the semiconductor device according to the first embodiment;

FIG. 12 is an explanatory diagram illustrating an example of an exposure apparatus used in the first embodiment.

FIG. 13 is an explanatory diagram illustrating an example of an exposure apparatus used in the first embodiment.

FIG. 14 is a plan view of a main part of a photomask according to another embodiment of the present invention.

FIG. 15 is a plan view illustrating the concept of a photoresist pattern transferred using the photomask of FIG. 14;

FIG. 16 is a plan view of a main part of a modified example of the photomask according to the second embodiment.

17A is a plan view of a main part of the photomask for explaining an optical simulation result of the photomask having the structure of the present embodiment, and FIG. 17B is a plan view of the main part of the photomask. FIG. 9 is an explanatory diagram showing a light intensity distribution which is an optical simulation result when a photomask is used.

FIG. 18 is a plan view of relevant parts of a semiconductor device according to another embodiment of the present invention;

FIG. 19A is a partial plan view of a photomask pattern of the technique studied by the present inventors, and FIG. 19B is a plan view of the concept of a photoresist pattern obtained by transferring the photomask pattern.

20A is a partial plan view of a photomask pattern according to the technique studied by the present inventors, and FIG. 20B is an explanatory diagram of a light intensity distribution showing an optical simulation result when the photomask pattern is used. It is.

FIG. 21A is a partial plan view of a photomask pattern of another technique studied by the present inventors, and FIG. 21B is a plan view of a concept of a photoresist pattern obtained by transferring the photomask pattern.

22A is a partial plan view of a photomask pattern of the technique of FIG. 21 studied by the present inventors, and FIG. 22B is a light intensity distribution showing an optical simulation result when the photomask pattern is used; FIG.

FIGS. 23A to 23C are partial plan views of photomask patterns of another technique studied by the present inventors.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 photomask 1A mask substrate 2 light-shielding film 3 light-transmitting region 4 photoresist pattern 5 semiconductor substrate 5C semiconductor chip 6 n-type buried well 7NW1, 7NW2 n-well 7PW1, 7PW2 p-well 8 groove-type separation part 8a separation groove 8b Isolation insulating film 9i Gate insulating film 10 Conductive film 10g Gate electrode 11 Cap insulating film 12n n-type semiconductor region 12p p-type semiconductor region 13nn n-type semiconductor region 13pp p-type semiconductor region 14nn n-type semiconductor region 15 to Reference Signs List 17 insulating film 18 plug 19 wiring 19A wiring 19BL bit line 20, 20a, 20b connection hole 21 capacitor 21a lower electrode 21b capacitance insulating film 21c plate electrode 22 insulating film 23 capacitor opening area 24 insulating film 25 connection hole 26 reduction projection exposure apparatus 26a Suction table 26b Axis moving table 26c Y-axis moving table 26d Z-axis moving table 26e Exposure light source 26f Condensing mirror 26g1 Planar reflecting mirror 26g2 Planar reflecting mirror 26h Shutter 26i Fly eye lens 26j Aperture 26k Band pass filter 26m Mask blind 26n Condenser lens 26p Mask holder 26q Reduction projection lens 27 Reduction projection exposure device 27a Slit 27b Mask stage 27c Reduction projection lens 28 Exposure light P1 to P4 Pattern WL Word line Qn N-channel MIS • FET Qp P-channel MIS • FET Qs Memory cell selection MIS • FET

Continuing on the front page (72) Inventor Toshihiko Tanaka 1-280 Higashi-Koigabo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (72) Inventor Katsutaka Kimura 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo F-term in Central Research Laboratory, Hitachi, Ltd. 2H095 BB02 BB36

Claims (9)

[Claims] 1. A method of manufacturing a semiconductor device, wherein a predetermined photoresist pattern is transferred by irradiating a photoresist film on a semiconductor substrate with exposure light emitted from an exposure light source via a photomask, The mask includes (a) a first pattern portion having a relatively narrow width, which is an actual pattern for transferring the predetermined photoresist pattern, and (b) a first pattern portion having the relatively narrow width. (C) constrictions generated on both sides in the width direction of the photoresist pattern corresponding to the first pattern portion are shifted in a direction away from each other;
A method for manufacturing a semiconductor device, comprising: an auxiliary pattern disposed at a corner formed by the first pattern portion and the second pattern portion. 2. A method of manufacturing a semiconductor device in which a predetermined photoresist pattern is transferred by irradiating an exposure light emitted from an exposure light source onto a photoresist film on a semiconductor substrate via a photomask. The mask includes: (a) a first pattern portion having a relatively narrow width, which is an actual pattern for transferring the predetermined photoresist pattern; and (b) a first pattern portion, which is the actual pattern. A second pattern portion formed integrally with the second pattern portion and (c) a corner formed by the first pattern portion and the second pattern portion and sandwiching the first pattern portion; The third placed at the position of
A semiconductor device having a pattern portion and a fourth pattern portion, wherein dimensions of the third pattern portion and the fourth pattern portion along an extending direction of the first pattern portion are changed. Production method. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the dimension in the width direction of the photoresist pattern corresponding to the first pattern portion is λ for the wavelength of the exposure light, NA for the numerical aperture, and NA for the pattern reduction ratio. If K, it is equal to or smaller than λ / (2NA), and the dimensional difference in the extending direction of the first pattern portion between the third pattern portion and the fourth pattern portion is λ / (2NA ·
K) A method for manufacturing a semiconductor device, characterized in that: 4. The method of manufacturing a semiconductor device according to claim 2, wherein said third pattern portion and said fourth pattern portion have a rectangular, triangular or stepped planar shape. Manufacturing method. 5. A method of manufacturing a semiconductor device in which a predetermined photoresist pattern is transferred by irradiating a photoresist film on a semiconductor substrate with exposure light emitted from an exposure light source via a photomask, The mask includes (a) a first pattern portion having a relatively narrow width, which is an actual pattern for transferring the predetermined photoresist pattern, and (b) a first pattern portion having the relatively narrow width. A second pattern portion formed integrally and having a relatively large width; and (c) the first pattern portion and the second pattern portion are formed such that the shape of the photoresist pattern in the width direction is asymmetric. And a supplementary pattern disposed at one corner of the semiconductor device. 6. A method for manufacturing a semiconductor device in which a predetermined photoresist pattern is transferred by irradiating a photoresist film on a semiconductor substrate with exposure light emitted from an exposure light source through a photomask, The mask includes (a) a first pattern portion having a relatively narrow width, which is an actual pattern for transferring the predetermined photoresist pattern, and (b) a first pattern portion having the relatively narrow width. A second pattern portion formed integrally and having a relatively large width; and (c) a fifth pattern portion disposed at one corner formed by the first pattern portion and the second pattern portion. The method of manufacturing a semiconductor device, wherein the photoresist pattern reflects the fifth pattern portion, and the shape of the photoresist pattern in the width direction is asymmetric. 7. The method of manufacturing a semiconductor device according to claim 6, wherein the dimension of the fifth pattern portion is λd / (2NA, where λd is the wavelength and NAd is the numerical aperture of the inspection optical system.
A method for manufacturing a semiconductor device, the method being larger than d). 8. The method for manufacturing a semiconductor device according to claim 5, wherein the width dimension of the photoresist pattern corresponding to the first pattern portion has an exposure wavelength of λ.
A method of manufacturing a semiconductor device, wherein the numerical aperture of an exposure optical system is λ / (2NA) or less, where NA is the numerical aperture. 9. The method of manufacturing a semiconductor device according to claim 1, wherein said predetermined photoresist pattern is a wiring pattern or a gate electrode pattern. Semiconductor device manufacturing method.