JP2000019710A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve resolution of a pattern, without switching apertures, in the case of pattern exposure using oblique lighting. SOLUTION: In a mask 1 for transferring a hole pattern to a photoresist film spread on a semiconductor wafer by exposure using oblique lighting, a pseudo repetition area is formed by providing an anti-phase area 3A, an in-phase half-tone area 3B, and a light-shading area 4 around a real pattern 2H provided for transferring the hole pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a technique for manufacturing a semiconductor integrated circuit device, and more particularly to a technique effective when applied to an exposure technique for transferring a fine pattern.

[0002]

2. Description of the Related Art Along with miniaturization of patterns of elements and wirings constituting a semiconductor integrated circuit device, in an exposure technique for transferring the pattern, a shorter exposure wavelength and a higher NA (numerical aperture) of a projection optical system are used. ), High resolution of the pattern has been realized. However, these techniques alone cannot keep up with the pattern miniaturization speed, and in recent years, various techniques for improving resolution have been developed and applied. Such an exposure technique is described in, for example, Press Journal Co., Ltd., May 20, 1997, “Monthly Semiconductor World”, June 1997 issue.
P124 to P143 (first document), JP-A-6-2425
No. 94 (No. 2) or International Publication No. WO 97 /
46914 (third document).

The first document discloses halftone mask technology and modified illumination technology as weak resolution technologies, and Levenson mask technology and pupil filter technology as strong resolution technologies. In the present circumstances,
By making full use of the resolution improvement technology introduced in the first document according to the target pattern, the practical resolution is improved and the depth of focus is ensured.

The second document discloses a technique in which an auxiliary pattern having the same transmission characteristics as the main pattern is provided in the vicinity of an isolated main pattern in an exposure mask in an exposure technique using modified illumination. .

Further, in the above-mentioned third document, a minimum transmittance portion formed on a photomask for exposure corresponding to a line pattern to be transferred to a semiconductor wafer and having the smallest light transmittance, A structure is disclosed in which a maximum transmittance portion having the largest transmittance and an intermediate transmittance portion formed in an extra region other than those transmittance portions and having a transmittance intermediate between the light transmittances of the transmittance portions are disclosed. ing.

[0006]

However, the present inventor has found that the techniques described in the above documents have the following problems.

That is, in the first document, a Levenson-type mask is introduced as a strong resolution improving technique for a repetitive pattern. The illumination in this case is generally small σ
(Σ is a partial coherence coefficient) illumination is used. As a resolution improvement technology for an isolated pattern used as a pair with this, there is an exposure technology using a reversed-phase halftone mask which is also introduced as a weak resolution improvement technology in the above-mentioned first document. Also in this case, a large effect can be obtained by the small σ illumination.

However, when a Levenson-type mask for a repetitive pattern is used, it is necessary to generate a phase difference of 180 degrees between each light transmitted through each of adjacent openings on the mask. There is a big problem that restrictions are imposed. Further, as described in the above-mentioned first document, various mask structures are introduced, and the restrictions on the phase difference are strict. Due to these problems, the Levenson-type mask for the repetitive pattern is a technique that is applied to a specific use but has no versatility. Therefore, in the case of the above-described technology for improving the resolution, it is not possible to improve the resolution of both the repetitive pattern and the isolated pattern with only one kind of illumination system.
As described in the above-mentioned first document, in order to exert the effect, the aperture of the illumination system is switched according to the pattern to be exposed or the type of the target mask to improve the depth of focus and improve the resolution of the pattern. That is being done. For example, in the first document, a reversed halftone mask technique and a modified illumination technique are used for transferring both a repetitive pattern and an isolated pattern as a technique for improving a weak resolution. I have to switch the aperture to make it work. However, when patterns exposed using greatly different illumination system apertures are superimposed, the superposition accuracy is deteriorated, and the above-mentioned first document shows a maximum of several tens nm or a maximum of 30 nm.
It is described that the accuracy of nm is deteriorated. This deterioration amount is not an allowable amount, but actually lowers the manufacturing yield of the semiconductor integrated circuit device.

Further, the first document describes a problem of an unnecessary pattern which occurs when a reversed-phase halftone mask is used. When a contact hole pattern or the like is exposed even with a normal mask, a light intensity peak is formed on the main surface of the photoresist film at a position corresponding to the main pattern on the mask (hereinafter, referred to as a primary peak). However, in addition, a secondary peak is formed at a position away from the primary peak by a predetermined distance due to a light diffraction phenomenon. Although the secondary peak has a low light intensity, the phase of the light is opposite to that of the primary peak when a small σ (σ is a partial coherence coefficient) illumination or a normal illumination is used as the exposure light. Therefore, when exposing a hole pattern using a reversed-phase halftone mask, the transmitted light of the reversed-phase halftone portion and the secondary peak cause constructive interference, and the unnecessary light intensity exceeds the resist sensitivity, which is unnecessary. There is a problem that the pattern is formed as a resist pattern. This problem is remarkable when two or more continuous contact hole patterns are arranged because each secondary peak overlaps at one place.

[0010] In addition, the first document describes that high resolution can be obtained by using deformed illumination in exposure of a repetitive pattern.
It has been found that the effect of improving the resolution by the modified illumination is small in the portion equivalent to the isolated pattern and the outermost pattern in the repeated pattern.

The second document discloses a method of improving the resolution of both a repetitive pattern and an isolated pattern in an exposure technique using modified illumination. If this technology can be applied practically, it is possible to solve the problem of the deterioration of the pattern overlay accuracy. However, according to the results of the study by the present inventors, in the technique of the second document, the graphic data processing for arranging the auxiliary pattern on the mask becomes complicated as the main pattern becomes finer and denser. Since the problem and its auxiliary pattern have the same transmission characteristics as the main pattern, it is required to be formed extremely fine so as not to be transferred to the photoresist film. ,
It has been found that there is also a situation in which restrictions on the mask production must be generated, and there is a problem that the production process of the mask having the auxiliary pattern is difficult.

Further, in the technique of the third document,
With the above-described mask structure, a sharp light intensity distribution can be obtained at the edge of the line pattern transferred to the photoresist film on the semiconductor wafer, and the resolution of the pattern can be improved. The configuration is different from the exposure technique of the present invention.

It is an object of the present invention to provide a technique capable of improving the resolution of a pattern without switching apertures in pattern exposure using oblique illumination.

Another object of the present invention is to provide a technique capable of reducing unnecessary light intensity in an isolated pattern in pattern exposure using oblique illumination.

Another object of the present invention is to provide a technique capable of improving the resolution of a portion or an outermost pattern which is partially equivalent to an isolated pattern among repetitive patterns.

Another object of the present invention is to provide a technique capable of facilitating graphic data processing of a mask.

Still another object of the present invention is to provide a technique which does not require forming a fine auxiliary pattern on a mask.

Another object of the present invention is to provide a versatile resolution improving technique in pattern exposure using oblique illumination.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0020]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the present invention illuminates a photoresist film on a semiconductor integrated circuit wafer with exposure light using oblique illumination through an exposure mask, so that the photoresist film has an isolated pattern or an isolated pattern equivalent portion. In a method of manufacturing a semiconductor integrated circuit device for exposing a semiconductor device, a semiconductor integrated circuit device using an exposure mask provided with a pseudo repetitive region around a first real transmission region for transferring the isolated pattern or the isolated pattern equivalent portion It is a manufacturing method of.

The following is a brief description of the outline of the invention other than the above divided into sections.

1. The integrated circuit pattern corresponding to the hole pattern on the super-resolution mask is subjected to non-small σ using ultraviolet exposure light.
A method of manufacturing a semiconductor integrated circuit device in which the hole pattern is transferred onto the semiconductor integrated circuit wafer by illuminating the light and projecting the transmitted light through a reduction projection optical system onto a photoresist film on the semiconductor integrated circuit wafer. Wherein the super-resolution mask has the following configuration: (a) a transparent substrate having first and second main surfaces; (b) a first substrate provided on the first main surface of the transparent substrate.
(C) an in-phase halftone having the same phase with respect to the first real transmission region provided around the first real transmission region on the first main surface of the transparent substrate. region.

2. 2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the photoresist film is a positive type.

3. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein the non-small σ illumination is oblique illumination.

4. 3. The method for manufacturing a semiconductor integrated circuit device according to claim 3, wherein the oblique illumination is annular illumination.

5. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein the transmittance of the in-phase halftone region is less than 10%.

6. The non-small illuminating the integrated circuit pattern on the super-resolution mask using ultraviolet exposure light, and the transmitted light is reduced and projected onto the photoresist film on the semiconductor integrated circuit wafer through the reduction projection optical system. In the method of manufacturing a semiconductor integrated circuit device for transferring an integrated circuit pattern onto the semiconductor integrated circuit wafer, the super-resolution mask has the following configuration: (a) a transparent substrate having first and second main surfaces; (b) a first substrate provided on the first main surface of the transparent substrate;
(C) a first light-shielding region provided in a primary proximity area on the first main surface of the transparent substrate with respect to the first actual transmission region; (d) a first light-shielding region of the transparent substrate An in-phase halftone region having the same phase as the first actual transmission region provided around the first light-shielding region on the first main surface.

7. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 6, wherein the integrated circuit pattern is a hole pattern on the semiconductor integrated circuit wafer.

8. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 7, wherein the non-small σ illumination is oblique illumination.

9. The integrated circuit pattern on the super-resolution mask is illuminated using ultraviolet exposure light, and the transmitted light is reduced and projected onto a photoresist film on a semiconductor integrated circuit wafer through a reduction projection optical system, thereby obtaining the integrated circuit pattern. In the method of manufacturing a semiconductor integrated circuit device for transferring a semiconductor device onto a semiconductor integrated circuit wafer, the super-resolution mask has the following configuration: (a) a transparent substrate having first and second main surfaces; A first substrate provided on the first main surface of the transparent substrate;
(C) an anti-phase opposite to the first real transmission area provided in a first-order proximity area on the first main surface of the transparent substrate with respect to the first real transmission area; A phase halftone region; (d) an in-phase halftone region having the same phase as the first real transmission region provided around the anti-phase halftone region on the first main surface of the transparent substrate. .

10. 9. The method for manufacturing a semiconductor integrated circuit device according to claim 9, wherein the illumination is a non-small σ illumination.

11. 11. The method of manufacturing a semiconductor integrated circuit device according to claim 10, wherein the integrated circuit pattern is a hole pattern on the semiconductor integrated circuit wafer.

12. The integrated circuit pattern on the super-resolution mask is illuminated using ultraviolet exposure light, and the transmitted light is reduced and projected onto a photoresist film on a semiconductor integrated circuit wafer through a reduction projection optical system, thereby obtaining the integrated circuit pattern. In the method of manufacturing a semiconductor integrated circuit device for transferring a semiconductor device onto a semiconductor integrated circuit wafer, the super-resolution mask has the following configuration: (a) a transparent substrate having first and second main surfaces; A first substrate provided on the first main surface of the transparent substrate;
(C) an anti-phase opposite to the first real transmission area provided in a first-order proximity area on the first main surface of the transparent substrate with respect to the first real transmission area; (D) 2 relating to the first actual transmission area around the anti-phase halftone area on the first main surface of the transparent substrate;
An in-phase halftone region having the same phase as that of the first real transmission region provided in the next proximity region; and (e) around the in-phase halftone region on the first main surface of the transparent substrate. The provided light shielding area.

13. 13. The method for manufacturing a semiconductor integrated circuit device according to claim 12, wherein the illumination is a non-small σ illumination.

14. 14. The method for manufacturing a semiconductor integrated circuit device according to claim 13, wherein the integrated circuit pattern is a hole pattern on the semiconductor integrated circuit wafer.

15. The non-small illuminating the integrated circuit pattern on the super-resolution mask using ultraviolet exposure light, and the transmitted light is reduced and projected onto the photoresist film on the semiconductor integrated circuit wafer through the reduction projection optical system. In the method of manufacturing a semiconductor integrated circuit device for transferring an integrated circuit pattern onto the semiconductor integrated circuit wafer, the super-resolution mask has the following configuration: (a) a transparent substrate having first and second main surfaces; (b) a first substrate provided on the first main surface of the transparent substrate;
(C) a first light-shielding region provided in a primary proximity area on the first main surface of the transparent substrate with respect to the first actual transmission region; (d) a first light-shielding region of the transparent substrate An in-phase halftone area having the same phase as the first real transmission area provided in a secondary proximity area related to the first real transmission area around the first light shielding area on the first main surface. (E) a second light-shielding region provided around the in-phase halftone region on the first main surface of the transparent substrate.

16. In the above item 15, the non-small σ
A method for manufacturing a semiconductor integrated circuit device, wherein the illumination is oblique illumination.

17. 17. The method of manufacturing a semiconductor integrated circuit device according to claim 16, wherein the integrated circuit pattern is a hole pattern on the semiconductor integrated circuit wafer.

18. The non-small illuminating the integrated circuit pattern on the super-resolution mask using ultraviolet exposure light, and the transmitted light is reduced and projected onto the photoresist film on the semiconductor integrated circuit wafer through the reduction projection optical system. In the method of manufacturing a semiconductor integrated circuit device for transferring an integrated circuit pattern onto the semiconductor integrated circuit wafer, the super-resolution mask has the following configuration: (a) a transparent substrate having first and second main surfaces; (b) a first substrate provided on the first main surface of the transparent substrate;
(C) a light-shielding region provided on an outer edge region of the transparent substrate on the first main surface with respect to the first real transmission region; (d) the first main surface of the transparent substrate An in-phase halftone region having the same phase as the first real transmission region provided between the first real transmission region and the light shielding region.

19. In the above item 18, the non-small σ
A method for manufacturing a semiconductor integrated circuit device, wherein the illumination is oblique illumination.

20. 20. The method of manufacturing a semiconductor integrated circuit device according to claim 19, wherein the integrated circuit pattern is a hole pattern on the semiconductor integrated circuit wafer.

21. 21. The optical mask according to any one of the above items 1 to 20.

22. 21. The method for manufacturing an optical mask according to any one of the above items 1 to 20.

The following is a summary of the other aspects of the invention, divided into sections.

23. In a method of manufacturing a semiconductor integrated circuit device for transferring an isolated pattern to a photoresist film on a semiconductor integrated circuit wafer by irradiating exposure light using non-small σ illumination to the photoresist film on the semiconductor integrated circuit wafer through the mask, Has the following features: (a) a transparent substrate having first and second main surfaces; (b) a light transmitting region for transferring the isolated pattern, A plurality of first real transmission regions provided to be close to each other on one main surface; (c) a first proximity region related to the first real transmission region on the first main surface of the transparent substrate; A first light-shielding region formed integrally with each other adjacent to each other; (d) the first light-shielding region on the first main surface of the transparent substrate;
And the phase of the transmitted light is the same as the phase of the light transmitted through the first real transmission area, and is higher than the light transmittance of the first real transmission area. A first common-mode region having a low light transmittance; (e) a second light-shielding region provided on an outer periphery of the first common-mode region on the first main surface of the transparent substrate.

24. Item 23. The method for manufacturing a semiconductor integrated circuit device according to Item 23, wherein the isolated pattern is a hole pattern.

25. 23. The method of manufacturing a semiconductor integrated circuit device according to the item 23, wherein the size of the first real transmission region of the mask is smaller than the size of the isolated pattern to be transferred to the photoresist film.

26. 23. The method for manufacturing a semiconductor integrated circuit device according to the above item 23, wherein the non-small σ illumination is oblique illumination.

27. In a method of manufacturing a semiconductor integrated circuit device for transferring an isolated pattern to a photoresist film on a semiconductor integrated circuit wafer by irradiating exposure light using non-small σ illumination to the photoresist film on the semiconductor integrated circuit wafer through the mask, Has the following features: (a) a transparent substrate having first and second main surfaces; (b) a light transmitting region for transferring the isolated pattern, A plurality of first actual transmission regions provided so as to be close to each other on the first main surface; (c) the first real transmission regions on the first main surface of the transparent substrate;
Are adjacently formed integrally with each other in the primary proximity region related to the real transmission region, and the phase of the transmitted light is opposite to the phase of the light transmitted through the first real transmission region, and A first reverse phase region having a light transmittance lower than the light transmittance of the first real transmission region; (d) the first reverse phase region on the first main surface of the transparent substrate;
And the phase of the transmitted light is the same as the phase of the light transmitted through the first real transmission region, and the light transmitted through the first real transmission region is (E) a second light-shielding region provided on the first main surface of the transparent substrate on the outer periphery of the first common-mode region.

28. 28. The method for manufacturing a semiconductor integrated circuit device according to the item 27, wherein the isolated pattern is a hole pattern.

29. 28. The method for manufacturing a semiconductor integrated circuit device according to the above item 27, wherein the size of the first real transmission region of the mask is smaller than the size of the isolated pattern to be transferred to the photoresist film.

30. 28. The method for manufacturing a semiconductor integrated circuit device according to the above item 27, wherein the non-small σ illumination is oblique illumination.

31. A semiconductor that transfers a repetitive pattern having an isolated pattern portion or an isolated pattern equivalent portion to the photoresist film by irradiating the photoresist film on the semiconductor integrated circuit wafer with exposure light using non-small σ illumination through a mask. In the method of manufacturing an integrated circuit device, the mask has the following features: (a) a transparent substrate having first and second main surfaces; (b) a light-shielding region for transferring the repetitive pattern. A first actual light-shielding region provided on the first main surface of the transparent substrate; (c) a first real light-shielding region on the first main surface of the transparent substrate.
A first light transmitting region formed in a primary proximity region relating to the actual light shielding region; (d) the first light transmitting region on the first main surface of the transparent substrate;
The light transmitted through the first light transmitting region is provided around the light transmitting region, the transmitted light has the same phase as the light transmitted through the first light transmitting region, and the light transmitted through the first light transmitting region (E) a second light transmitting region provided on the outer periphery of the first common mode region on the first main surface of the transparent substrate.

32. 29. The manufacturing method of a semiconductor integrated circuit device according to the above item 28, wherein the repetition pattern is a line pattern.

33. 29. The method for manufacturing a semiconductor integrated circuit device according to the above item 28, wherein the non-small σ illumination is oblique illumination.

34. A first integrated circuit having a repetitive pattern in a photoresist film by irradiating exposure light emitted from an oblique illumination type exposure light source to a photoresist film on a semiconductor integrated circuit wafer via a first mask. A first exposure step of exposing a pattern, and irradiating a photoresist film on a semiconductor integrated circuit wafer with exposure light emitted from an exposure light source of an oblique illumination method via a second mask, thereby forming the photoresist. A method of manufacturing a semiconductor integrated circuit device having a second exposure step of exposing a second integrated circuit pattern formed of an isolated pattern on a film; wherein the first exposure step and the second exposure step Perform exposure processing without switching the illumination optical system (aperture),
The first mask has the following configuration; (a) a first transparent substrate having first and second main surfaces; and (b) a light-shielding region for transferring the first integrated circuit pattern. A first actual light shielding area provided on the first main surface of the first transparent substrate; (c) provided on the first main surface of the first transparent substrate; A first light transmitting region provided on the outer periphery of the first real light shielding region; the second mask has the following configuration; (d) a second transparent substrate having first and second main surfaces (E) a light transmitting area for transferring the second integrated circuit pattern, wherein the first real transmitting area is provided on the first main surface of the second transparent substrate; A) a pseudo repeating area provided on the main surface of the second transparent substrate around the first real transmission area.

35. In the above paragraph 34, the pseudo repeating region of the second mask has the following configuration: (a). The first real region on the first main surface of the second transparent substrate. A first light-blocking region provided in a primary proximity region related to a transmission region; (b) a first light-blocking region provided around the first light-blocking region on the first main surface of the second transparent substrate; A first in-phase region in which the phase of the transmitted light is the same as the phase of the light transmitted through the first real transmission region and the light transmittance of the first real transmission region is lower than the light transmittance of the first real transmission region.

36. In the above paragraph 34, the pseudo repeating region of the second mask has the following configuration: (a). The first actual transmission on the first main surface of the second transparent substrate. The first provided in the primary proximity region with respect to the region
(B) provided on the first main surface of the second transparent substrate around the first light-shielding region, with respect to the phase of light transmitted through the first real transmission region. A first in-phase region in which the phase of the transmitted light is the same and the light transmittance is lower than the light transmittance of the first real transmission region; (c). A second light-shielding region provided on an outer periphery of the first in-phase region on the main surface of the first light-emitting device;

37. In the above paragraph 34, the pseudo repeating region of the second mask has the following configuration: (a). The first real region on the first main surface of the second transparent substrate. Provided in a primary proximity region for the transmission region,
A first reverse phase region in which the transmitted light has a phase opposite to that of the light transmitted through the first real transmission region and has a light transmittance lower than the light transmittance of the first real transmission region; (b) a light that is provided on the first main surface of the second transparent substrate around the first reverse phase region and that transmits light with respect to the phase of light transmitted through the first real transmission region. Are in-phase, and have a lower light transmittance than the light transmittance of the first real transmission region.

38. In the above paragraph 34, the pseudo repeating region of the second mask has the following configuration: (a). The first real region on the first main surface of the second transparent substrate. Provided in a primary proximity region for the transmission region,
A first reverse phase region in which the transmitted light has a phase opposite to that of the light transmitted through the first real transmission region and has a light transmittance lower than the light transmittance of the first real transmission region; (b) a light that is provided on the first main surface of the second transparent substrate around the first reverse phase region and that transmits light with respect to the phase of light transmitted through the first real transmission region. A first in-phase region having the same phase and having a light transmittance lower than that of the first real transmission region; (c). The first main surface of the second transparent substrate. A first light-shielding region provided on an outer periphery of the first in-phase region.

39. A first integrated circuit having a repetitive pattern in a photoresist film by irradiating exposure light emitted from an oblique illumination type exposure light source to a photoresist film on a semiconductor integrated circuit wafer via a first mask. A first exposure step of exposing a pattern, and irradiating a photoresist film on a semiconductor integrated circuit wafer with exposure light emitted from an exposure light source of an oblique illumination method via a second mask, thereby forming the photoresist. A method of manufacturing a semiconductor integrated circuit device having a second exposure step of exposing a second integrated circuit pattern formed of an isolated pattern on a film; wherein the first exposure step and the second exposure step The exposure processing is performed without switching the illumination optical system (aperture), and the first mask has the following configuration; (a) a first transparent group having first and second main surfaces; (B) a light-shielding area for transferring the first integrated circuit pattern, the first actual light-shielding area provided on the first main surface of the first transparent substrate; A first light transmitting region provided on the first main surface of the first transparent substrate and provided on an outer periphery of the first real light shielding region; (d) a first light transmitting region provided on the first transparent substrate; Is provided on the outer periphery of the first light transmitting region, the transmitted light has the same phase as the light transmitted through the first light transmitting region, and the first light transmitting region has the same phase. A first in-phase region whose light transmittance is lower than the light transmittance of the light transmitting region of the second mask; the second mask has the following configuration; (e) a second having a first and a second main surface. A transparent substrate; (f) a light transmitting region for transferring the second integrated circuit pattern, provided on the first main surface of the second transparent substrate. 1 of the actual transmission region; (g) pseudo-repeat region provided around the actual transmission region on the main surface of the first of the second transparent substrate.

40. 39. In the paragraph 39, the pseudo repeating region of the second mask has the following configuration: (a). The first real region on the first main surface of the second transparent substrate. A first light-blocking region provided in a primary proximity region related to a transmission region; (b) a first light-blocking region provided around the first light-blocking region on the first main surface of the second transparent substrate; A second in-phase region in which the phase of the transmitted light is the same as the phase of the light transmitted through the first real transmission region, and the light transmittance of the first real transmission region is lower than the light transmittance of the first real transmission region.

41. 39. In the paragraph 39, the pseudo repeating region of the second mask has the following configuration; (a). The first actual transmission on the first main surface of the second transparent substrate. The first provided in the primary proximity region with respect to the region
(B) provided on the first main surface of the second transparent substrate around the first light-shielding region, with respect to the phase of light transmitted through the first real transmission region. A first in-phase region in which the phase of the transmitted light is the same and the light transmittance is lower than the light transmittance of the first real transmission region; (c). A second light-shielding region provided on an outer periphery of the first in-phase region on the main surface of the first light-emitting device;

42. 39. In the paragraph 39, the pseudo repeating region of the second mask has the following configuration: (a). The first real region on the first main surface of the second transparent substrate. Provided in a primary proximity region for the transmission region,
A first reverse phase in which the phase of the transmitted light is opposite to the phase of the light transmitted through the first real transmission region, and the light transmittance is lower than the light transmittance of the first real transmission region. An area; (b) provided on the first main surface of the second transparent substrate around the first reverse phase area, with respect to the phase of light transmitted through the first real transmission area; A second in-phase region in which the phase of the transmitted light is the same and the light transmittance is lower than the light transmittance of the first real transmission region.

43. 39. In the paragraph 39, the pseudo repeating region of the second mask has the following configuration: (a). The first real region on the first main surface of the second transparent substrate. Provided in a primary proximity region for the transmission region,
A first reverse phase in which the phase of the transmitted light is opposite to the phase of the light transmitted through the first real transmission region, and the light transmittance is lower than the light transmittance of the first real transmission region. An area; (b) provided on the first main surface of the second transparent substrate around the first reverse phase area, with respect to the phase of light transmitted through the first real transmission area; A second in-phase region in which the phase of the transmitted light is the same and the light transmittance is lower than the light transmittance of the first real transmission region; (c). The first in-phase region of the second transparent substrate A first light-shielding region provided on the outer periphery of the second in-phase region on the main surface.

44. Exposure optics belonging to the same classification in a first exposure step using oblique illumination of a semiconductor integrated circuit pattern having an isolated pattern and a second exposure step using oblique illumination of a semiconductor integrated circuit pattern having a repeating pattern In order to use the system, in the first mask used in the first exposure step, a pseudo repeating region is arranged around a first real transmission region for transferring the isolated pattern.

[0068]

1A and 1B are explanatory views for explaining the principle of oblique illumination as an exposure technique according to an embodiment of the present invention, and FIGS. 2A and 2B. FIG. b) is a graph for explaining the hole diameter calculation method used in the present embodiment, and FIG.
FIG. 4 is a plan view of a principal part of a mask used for evaluating an effect region of a reversed-phase halftone region, FIG. 4 is a graph showing an evaluation result of an effect region of a reversed-phase halftone region, and FIG. FIGS. 6 (a) and 6 (b) are graphs for comparison, and FIGS. 6 (a) and 7 (b) are graphs for comparing unnecessary light intensity ratios.
FIG. 8 is a graph for comparing unnecessary light intensity ratios when a halftone mask is used in an exposure process using oblique illumination, FIG. 8 is an enlarged plan view of a main part of the mask of the present embodiment, and FIG. 8 is a graph for explaining the effect of improving the depth of focus when the mask of FIG. 8 is used. FIGS. 10 to 17 are enlarged cross-sectional views of essential parts during the manufacturing process of the mask of FIG.
FIG. 25 is an enlarged cross-sectional view of a main part in another manufacturing process of the mask in FIG. 8, FIGS. 25 to 32 are enlarged cross-sectional views of a main part in another manufacturing process of the mask in FIG. 8, and FIG. FIG. 34 is an enlarged plan view of a main part of the mask according to the embodiment, FIG. 34 is a graph showing the effect of improving the depth of focus when the mask of FIG. 33 is used, and FIG. 35 is a graph showing the unnecessary light intensity when the mask of FIG. FIG. 36 is an enlarged plan view of a main part of a mask according to another embodiment of the present invention, and FIG. 37 is a graph showing the effect of improving the depth of focus when the mask of FIG. 36 is used.
36 is a graph showing the intensity of unnecessary light when the mask of FIG. 36 is used, FIGS. 39 to 43 are cross-sectional views of main parts during the manufacturing process of the mask of FIG. 36, and FIG. 44 is another embodiment of the present invention. FIG. 45 is an enlarged plan view of a principal part of a certain mask, FIG. 45 is a graph showing the effect of improving the depth of focus when the mask of FIG. 44 is used, and FIG.
6 (a) to 6 (c) are graphs showing unnecessary light intensity when the mask of FIG. 44 is used, FIG. 47 is an enlarged plan view of a main part of a mask according to another embodiment of the present invention, and FIG. a) ~
(C) is a graph showing the effect of improving the depth of focus when the mask of FIG. 44 is used, FIG. 49 is an enlarged plan view of a main part of a mask according to another embodiment of the present invention, and FIGS. c) is a graph showing the effect of improving the depth of focus when the mask of FIG. 49 is used, FIG. 51 is an enlarged plan view of a main part of a mask according to another embodiment of the present invention, and FIG. FIG. 53 (a) is an explanatory view of a unit cell used for creating graphic data.
54C are explanatory views of each layer constituting the unit cell of FIG. 52, FIG. 54 is an enlarged plan view of a main part of a mask according to another embodiment of the present invention, and FIGS. FIG. 59 is an explanatory view of a layer used for creating graphic data, and FIGS.
FIG. 63 is an explanatory view for explaining a method of generating graphic data of a mask of FIG. 7, FIG. 63 is an explanatory view of a pattern overlay displacement preventing effect according to the present embodiment, and FIG. 64 is an exposure apparatus used for exposure processing of the present embodiment. FIGS. 65 and 66 are explanatory views of an exposure light source in the exposure apparatus of FIG. 64, FIG. 67 is an explanatory view of another exposure apparatus used in the exposure processing of this embodiment,
FIG. 68 (a) is an explanatory view of an exposure apparatus studied by the inventor, FIG. 68 (b) is an explanatory view of the exposure apparatus of FIG. 67, and FIGS. 69 to 71 are masks according to another embodiment of the present invention. 72 to 79 are main-portion cross-sectional views of a semiconductor integrated circuit device during a manufacturing process to which the exposure processing according to the embodiment of the present invention is specifically applied.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted. Further, in this specification, when an area is designated, a boundary area of an area theoretically classified as such for the sake of mask creation and design convenience is selected as necessary.

In this specification, the terms “the phase is the same, inverted, or reversed” means that the phase difference is equivalent (including the case where the phase difference is the same except for a difference of 2nπ) and that the phase depth is the same. And an intermediate phase difference shifted to such a degree that there is no problem in the focal position. Generally, the deviation is within a few degrees. The components described in the present embodiment are not necessarily essential unless otherwise specified. Furthermore, the number of each component is not limited to that shown unless otherwise specified.

The following terms are used in this specification.

The primary proximity region (in FIG. 4, for example, 0.25 μm)
Area up to m): An area that contributes primarily to the improvement of resolution (including the depth of focus improvement effect) when the phase is made opposite to the actual aperture.

The secondary proximity region (in FIG. 4, for example, 0.25 μm)
(Area from m to 0.6 μm): An area which contributes to the improvement of resolution when it has the same phase as the actual aperture.

Outer edge region (in FIG. 4, for example, 0.6 μm or more): This is a region which hardly contributes, but exhibits a property similar to that of the primary proximity region, though to a lesser extent.

Normal illumination: Non-deformed illumination, which refers to illumination having a relatively uniform light intensity distribution.

Deformation illumination: illumination with reduced illuminance at the center, including multi-pole illumination such as oblique illumination, annular illumination, quadrupole illumination, and quadrupole illumination, or a super-resolution technique using a pupil filter equivalent thereto. .

Oblique illumination: Illumination with a relatively large amount of illumination components from oblique directions, such as annular illumination, quadrupole illumination, and multipole illumination such as illumination with reduced illuminance at the central portion. Includes super-resolution techniques with equivalent pupil filters.

Small σ illumination: Partial coherence coefficient σ
Is less than 0.45 and the illumination distribution is relatively uniform inside.

Non-small σ illumination: illumination other than the above small σ illumination,
Normal illumination with σ of 0.45 or more and modified illumination without limitation of σ.

Normal mask: An optical mask in which the device pattern area of the mask is composed only of a light-shielding area of 0% transmission and an opening area of almost 100% transmission.

Phase shift mask: An optical mask having a phase shifter region.

Super-resolution technology: An exposure technology using a phase shift mask, or a resolution and depth of focus improvement technology using deformed illumination (including oblique illumination) and a pupil filter.

Super-resolution mask: An exposure technique for improving resolution and depth of focus by introducing a mask structure different from a phase shift mask and a normal mask.

Actual pattern: an integrated circuit pattern such as an opening pattern on a mask, which corresponds to a device pattern actually transferred onto a wafer.

Auxiliary pattern: an integrated circuit pattern such as an opening pattern on a mask which does not correspond to a device pattern actually transferred onto a wafer. In effect, the independent pattern is not transferred onto the wafer.

A phase of an aperture: When a phase difference occurs in the phase of light passing through two openings of a mask or the like, instead of saying the phase difference of the transmitted light, as is used in many optical texts, It shall be described as an attribute of the opening itself.

Halftone region: A region having a transmittance as low as not to expose the photoresist itself, and there is a distinction between the same phase and the opposite phase (inversion). Generally, the transmittance is about 3% to 15%, but a high transmittance halftone area of 20% or more is also possible by using a light shielding area or the like in combination.

Inverted halftone or inverted auxiliary pattern: Generally called halftone phase shift or auxiliary phase shift pattern.

In-phase halftone or in-phase auxiliary pattern: A halftone portion or an auxiliary pattern in which no phase shift member is provided on the mask or a phase difference corresponding to an integral multiple of the exposure wavelength is provided between itself and the main body pattern.
In other words, assuming a plane wave having a wavelength that is perpendicular to the mask and equal to the exposure wavelength, between the light passing through the halftone portion or the auxiliary pattern portion and the light passing through the real pattern portion on the mask, A halftone portion or an auxiliary pattern that is not intended to cause a phase difference or provides a phase difference of an integral multiple of the exposure wavelength.

Light-shielding region: Generally, a region having a transmittance of almost 0% (typically 1% or less), and can be functionally defined as a region having a transmittance lower than that of the halftone region.

Ultraviolet light: In the semiconductor industry, an electromagnetic wave (light) having a wavelength shorter than about the g-line (436 nm) of a mercury lamp and up to about 100 nm in a vacuum ultraviolet region is called ultraviolet light.
Distinguish from visible light and X-ray.

Semiconductor integrated circuit wafer: A substrate on which a semiconductor integrated circuit device is formed, generally made of silicon single crystal. Where necessary, an integrated circuit is formed by forming an epitaxial semiconductor layer, another semiconductor layer, or an insulating layer on an insulator or a semiconductor substrate. In this specification, it is simply called a wafer.

Optical mask: A projection master / mask or reticle generally formed by forming a pattern for shielding light or a pattern for changing the phase of light on a substrate. The term “on the substrate” includes the upper surface of the substrate, the internal region adjacent to the upper surface of the substrate, or the sky region (may be disposed on another substrate adjacent to the upper surface). In this specification, it is simply referred to as a mask.

Hole pattern: A fine hole pattern such as a contact hole or a through-hole having a two-dimensional size equal to or less than the exposure wavelength on the wafer. In general, the shape is a square, a rectangle close to the square, an octagon, or the like on a mask, but is often close to a circle on a wafer.

In the following embodiments, unless otherwise specified, for example, the following conditions were used. Exposure light was i-line of a mercury lamp, wavelength was 365 nm, NA = 0.63, and oblique illumination was annular illumination (0.42 ≦ σ ≦ 0.7) as a representative.
When a small σ illumination is used as a comparison target, σ = 0.
4. When normal illumination was used, σ was set to 0.7. The halftone transmittance was 5% in the case of the hole pattern and 10% or more in the case of the line pattern, regardless of whether the phase was the opposite phase or the same phase. In the case of the hole pattern, the assumed hole diameter after transfer at the time of in-focus was 0.35 μm. The halftone transmittance is, for example, about 13% in the examples of FIGS. 47 and 48, and is, for example, about 70% in the examples of FIGS.

The technical idea of the present invention is that when an isolated pattern is transferred onto a wafer by exposure processing using oblique illumination, an optical mask having a pseudo-repeated region in a region including a real pattern for transferring the isolated pattern. Is used to improve the depth of focus in the transfer of an isolated pattern, as in the transfer of a repetitive pattern using oblique illumination. Thus, the exposure step for transferring the isolated pattern and the exposure step for transferring the repetitive pattern use illumination optical systems (apertures) of the same classification.

First, the principle of oblique illumination will be described with reference to FIG. FIG. 1A shows a case where the irradiation light is perpendicularly incident on the mask. In this case, the 0th-order light component traveling straight and ± 1
The next-order light component contributes to the image formation, but since the 0th-order light component and the ± 1st-order light component have different incident angles with respect to the wafer, the range where the phases are aligned (depth of focus) is limited to a narrow range. On the other hand, FIG. 3B shows the case of oblique illumination, in which only the 0th-order light component and the + 1st-order light component (or only the 0th-order light component and the -1st-order light component) contribute to the image formation. , -1st order light component (+ 1st order light component when an image is formed by the 0th order light component and the -1st order light component) goes out of the optical path and does not form an image. In this case, the zero-order light component and +1
When the incident angle on the wafer with the next light component is equal and the numerical aperture (hereinafter, referred to as NA) is the same, the diffraction angle is twice that in the case of FIG. When the dimensions are the same, the depth of focus is improved because the NA may be half of the case of FIG.

In general, the size of the diffraction angle of the diffracted light depends on the period of the pattern. Therefore, the condition shown in FIG. 3B is limited only to illumination at a specific incident angle with respect to the repetitive pattern. That is, oblique illumination is particularly effective for exposure of a repeated pattern. In addition, the annular illumination among the oblique illuminations has little pattern directivity, and is effective for a pattern in an oblique direction. Oblique illumination was originally introduced as an alternative to the Levenson-type phase shift mask, which was considered to require a long technical development time to make it versatile, and is widely used for exposure of line patterns, which are representative of repeated patterns. Have been. Further, as described in the above-mentioned Document 1, it is known that the performance is improved by a combination with a reversed-phase halftone mask.

Next, a method of calculating the hole diameter of the hole pattern from the light intensity distribution used in the present invention will be described.
The technical concept of the present invention will be described.

For calculating the light intensity distribution on the photoresist surface, a commercially available simulator was used. The exposure wavelength of the exposure apparatus is i-line of a mercury lamp, and the NA of the projection optical system is 0.63.
And FIGS. 2A and 2B show a method for calculating the hole diameter after transfer when the focus at the time of exposure is shifted.

FIG. 2A shows that a normal mask is illuminated with normal illumination (σ
= 0.7) is the light intensity distribution on the photoresist in the in-focus state when exposed using 0.7). The assumed hole pattern diameter is 0.35 μm, and the hole pattern of the mask is 0.35 × 0.35 μm. Since the assumed hole diameter is 0.35 μm, the relative intensity at the position of ± 0.175 μm is 0.248, which is the reference relative intensity under this condition. The hole diameter when defocused by 0.4 μm is calculated from the position where the reference relative intensity is 0.248, and the hole diameter when defocused is 0.413 μm.
Is calculated. As described above, the relative intensity of the portion corresponding to the assumed hole diameter edge of the isolated hole at the time of in-focus is set as the reference relative intensity for each condition, and a position where the same relative intensity is obtained, and the hole diameter is calculated. , Are used herein.

This calculation method is similarly applied to the calculation of the line width of the line pattern, and the line width at the time of defocus is calculated using the relative intensity at the position corresponding to the assumed line width at the time of in focus as the reference relative intensity. You. further,
This calculation method is also applied to a position shift when the projection optical system has an aberration. The relative intensity at the position corresponding to the assumed hole diameter or assumed line width when there is no aberration is defined as the reference relative intensity. When there is aberration, the position of the transfer pattern is shifted from the position of the relative intensity equal to the reference relative intensity. Is calculated.

Next, the evaluation result based on the idea of the technical idea of the present invention, the technical idea of the present invention devised from the evaluation result, and the operation and effect thereof will be described. In this specification, the resolution itself will not be described, but only the depth of focus improvement effect will be described. This is a practical resolution
After all, it is determined by whether or not the depth of focus can withstand the variation in the best imaging position of the exposure device or the step on the substrate on which the pattern is transferred. This is because it indicates that the resolution is also improved.

FIG. 3 is a plan view of a mask 50 used to evaluate the state of resolution when a hole pattern is transferred by oblique illumination. The actual pattern 51 on the mask 50 is, for example, 0.35 μm × 0.35 μm
And the transparent substrate is exposed from the area. The four inverted halftone areas 52 arranged to correspond to the four sides of the real pattern 51 are:
For example, it is formed in a planar rectangular shape of 0.05 μm × 0.35 μm, and has a light transmittance of, for example, 40%. A hatched area other than these is a shielding area 53 that blocks transmission of light as defined by the above-mentioned terms.

FIG. 4 shows the evaluation results of the resolution when the mask 50 is used to perform exposure processing under oblique illumination. The reverse halftone area 2 in the mask 50 is gradually separated from the actual pattern 51. 0 in case
This shows the dependence of the 4 μm defocus hole diameter.
The assumed hole diameter is 0.35 μm, the same as above, and the exposure wavelength
A and the actual pattern size of the mask are the same conditions as above,
Illumination conditions are annular illumination (0.42 ≦ σ) which is representative of oblique illumination.
≤ 0.7). From this dependency, it was found that the following tendency was observed when oblique illumination (particularly, annular illumination) was used.

First, in comparison with the hole diameter at the time of defocusing of 0.4 μm, the hole diameter larger than that of the normal mask, that is, the depth of focus is improved, is that the reverse phase halftone region 52 is formed by the actual pattern. This is only when the light-shielding region 53 having a width of less than about 0.25 μm is disposed between the light-shielding region 51 and the light-shielding region 51. A region where such an effect is obtained is defined as a primary proximity region.

Second, when the reverse phase halftone region 52 is disposed between the actual pattern 51 and the light-shielding region 53 having a width of about 0.25 μm to about 0.95 μm, the reverse halftone area 52 has a thickness of 0.4 μm.
The hole diameter at the time of defocus becomes smaller than that in the case of normal illumination.
Therefore, arranging the in-phase halftone region 52 at this plane position has the opposite effect, and it can be seen that arranging the in-phase halftone region at this position (region) can improve the depth of focus. Such an area was defined as a secondary proximity area.

Third, in a region where the width of the light-shielding region 53 between the real pattern 51 and the reverse halftone region 52 is 0.95 μm or more, the depth of focus is obtained by disposing the reverse halftone region 52 again. To improve. Such an area was defined as an outer edge area.

From these evaluation results, for example, the following technical idea of the present invention is devised. That is, the reverse halftone region and the in-phase halftone region are arranged at appropriate positions and combined, or a 90-degree phase shift halftone region is interposed between the halftone regions.

It is also found that the depth of focus can be improved by using a mask (gradient shifter mask) whose phase difference changes continuously from the center of the actual pattern toward the outside. However, since it is substantially difficult to manufacture a gradient shifter mask, a mask in which a phase difference changes stepwise is used in this embodiment. Also,
If there are too many stages of phase difference, the mask manufacturing process becomes complicated if there are too many stages. Therefore, in this embodiment, the phase difference is one stage, and the vicinity of the actual pattern is in the opposite half-tone region as described later. The outside thereof is an in-phase halftone region, and the transmittance of the halftone region is substantially equal between the opposite-phase / in-phase region. With such a simplified mask structure, a mask that can be actually manufactured is obtained.

Further, even in a mask structure in which the outer in-phase halftone region is wider than the inner in-phase halftone region or a mask structure in which only the in-phase halftone region is arranged around the actual pattern, the depth of focus can be improved. Can be achieved. Further, if a mask structure is used in which a light-shielding region is arranged in the primary proximity region close to the actual pattern, and an in-phase halftone region is arranged outside (the secondary proximity region and the outer edge region),
Further, the depth of focus can be improved. Further, considering that the reverse-phase auxiliary pattern has a width of, for example, 0.05 μm, the light-shielding area is arranged in this area because the outer edge area beyond 1.0 μm is the reverse-phase halftone effect area as described above. If a light-shielding region is arranged in the primary proximity region near the actual pattern, and a light-shielding region in which an in-phase halftone region is arranged in the secondary proximity region and a mixed-type halftone region mask structure, furthermore, The depth of focus can be improved. The effect of these mask structures can be obtained not only in the hole pattern but also in the isolated portion of the line pattern or the above-mentioned repeated end portion in any of the mask structures.

In the above description, the actual pattern on the mask is a light-transmitting area. However, when the actual pattern is a light-shielding area on the mask, the light-transmitting area is placed in a primary proximity area around the actual pattern. Is arranged, and the in-phase halftone area is arranged in the secondary proximity area and the outer edge area, so that the depth of focus can be improved. Further, when the actual pattern is a light-shielding region, a light transmitting region is disposed in the primary proximity region, an in-phase halftone region is disposed in the secondary transmitting region, and a light transmitting region is disposed in the outer edge region. With this structure, the depth of focus can be further improved. The effect of the mask structure when the actual pattern is the light-shielding region can be obtained not only in the hole pattern but also in the isolated portion of the line pattern or the above-mentioned repeated end portion in any mask structure.

Next, other functions and effects of the technical idea of the present invention will be described.

First, in the case of oblique illumination, the zero-order diffracted light component is larger in ratio to the other order components and the contrast is lower than in the case of using other illuminations due to the principle of image formation. There are weak points. For this reason, if exposure is performed using a mask having a real pattern with a small hole diameter, it is considered that the effect of improving the depth of focus is greater when oblique illumination is used than when other illumination is used.

FIG. 5 shows this effect. The hole diameter at the time of defocusing of 0.4 μm when the assumed hole diameter after transfer at the time of in-focus is equal to the hole diameter of the actual pattern on the mask is shown. As a reference, the relative value of the hole diameter at the time of defocusing of 0.4 μm when the hole diameter of the actual pattern of the mask was reduced is shown. In the case of annular illumination, the hole diameter dependence of the actual pattern in the mask of the hole diameter at the time of defocus is larger than the case of small σ illumination, and in the case of annular illumination,
This indicates that the effect of improving the depth of focus can be easily obtained by reducing the hole diameter of the actual pattern in the mask.

When oblique illumination is used, since the unnecessary light intensity ratio, which is the ratio of the relative intensity of the unnecessary light peak portion to the reference relative intensity, is originally small, the hole diameter of the actual pattern of the mask is reduced. However, the effect that the problem of unnecessary pattern formation hardly occurs is also obtained.

FIG. 6 shows the unnecessary light intensity ratio when the normal mask is exposed using oblique illumination and small σ illumination. The unnecessary light intensity ratio is a ratio between the unnecessary light relative intensity and the reference relative intensity. FIG. 6A shows an unnecessary light intensity ratio of an isolated hole pattern, and FIG. 6B shows an unnecessary light intensity on a perpendicular bisector of a line connecting the center of each hole pattern with a continuous hole pattern arranged in one direction. The ratio is shown. In FIG. 6,
Light within the same range as the assumed hole diameter from the center of the hole pattern was deleted as the tail of the primary peak. In the case of the isolated hole pattern, there is no significant difference in the unnecessary light intensity ratio.
However, in the case of a continuous hole pattern, at the time of small σ illumination, the distance from the line connecting the center of the hole pattern is a little less than 0.4 μm.
The secondary peak at a position slightly above 5 μm corresponds to a position overlapping with the secondary peak of the adjacent hole pattern in the case of a continuous hole pattern. In (2), even in the case of the normal mask, there is a peak of unnecessary light exceeding 5% of the intensity ratio, whereas in the case of oblique illumination, there is no particular peak. In addition, when comparing the unnecessary light intensity ratio between the isolated hole pattern and the continuous hole pattern, the small hole σ illumination shows a large increase in the continuous hole pattern, whereas the oblique illumination shows almost no increase. That is, even if the secondary peaks further overlap, in the case of oblique illumination, there is almost no possibility that the unnecessary light intensity ratio increases. This difference is understood because the spatial coherence due to the difference in illumination type is lower in oblique illumination. The advantage of the oblique illumination leads to an advantage in pattern arrangement design that there is almost no restriction in pattern arrangement.

FIG. 7 shows the light intensity distribution when the reverse halftone mask and the in-phase halftone mask are exposed using oblique illumination. FIG. 7 also shows a light intensity distribution when a light-shielding region is arranged near the actual pattern. FIG. 7A shows the relative intensity distribution in three cases. Compared with the case of the reverse halftone, the two types of masks using the in-phase halftone have relative positions of the portions corresponding to the actual pattern. This indicates that the strength has not decreased. This is because, in the reversed-phase halftone mask, the light transmitted through the reversed-phase halftone region and the light transmitted through the real pattern cause destructive interference, so that the relative intensity of the portion corresponding to the real pattern decreases, It is presumed that in the in-phase halftone mask, this destructive interference effect is small. Therefore, in the case of in-phase halftone,
The contrast is also low. FIG. 7B shows a comparison of the unnecessary light intensity ratio excluding the actual pattern portion by transforming the intensity distribution data of FIG. 7A into the intensity ratio divided by the reference relative intensity for each condition. In the case of a reversed-phase halftone mask in which the reference relative intensity is reduced as a result of destructive interference, the intensity of the unnecessary light, which is equivalent in the relative intensity shown in FIG. In the case of an in-phase halftone mask having a small interference effect exceeding
It stays at just over%. As described above, the technical concept of the present invention has two advantages: low spatial coherence of oblique illumination and low destructive coherence in the in-phase halftone region.

Next, a specific structure of the mask in this embodiment will be described. First, a technique for improving the resolution of an isolated hole pattern, which is a representative example of an isolated pattern, using annular illumination, which is a representative example of oblique illumination, will be described. This is because the effect of improving the resolution of a line pattern by oblique illumination is known, and if a method capable of improving the resolution of a hole pattern when oblique illumination is used is shown, it is not necessary to switch the illumination system aperture. This is because it indicates that it is possible to avoid the deterioration of the overlay accuracy of the pattern.

In the first specific example of the mask, as shown in FIG. 8, on the main surface of the mask 1, an actual pattern 2H, a reverse-phase halftone region 3A, an in-phase halftone region 3B and a light-shielding region 4 are formed as shown in FIG. They are arranged stepwise from the center to the outside. That is, the mask 1 has a pseudo repeated region centered on the actual pattern 2H.

The actual pattern 2H at the center of FIG. 1 is a mask pattern for transferring a hole pattern to a photoresist film on a wafer, for example, 0.35 μm × 0.35 μm
Are formed in the shape of a plane square. This actual pattern 2H
Is formed, the transparent substrate of the mask 1ma is exposed, and the transmittance of light passing therethrough is equal to the transmittance of the transparent substrate. The actual pattern 2H is transferred as a substantially planar circular pattern in the photoresist film.
In this case, a positive type is used for the photoresist film (hereinafter, the same applies to a mask for transferring a hole pattern).

The inverted halftone region 3A surrounding the actual pattern 2H is formed by the light transmitted therethrough and the actual pattern 2H.
Is a region where a phase difference of 180 ° is generated between the light and the light transmitted therethrough, and is not particularly limited. For example, the region is formed in the shape of an outer octagonal ring having a width (the width of a relatively wide region) of about 0.3 μm. ing. The constituent material of the reverse halftone film forming the reverse halftone region 3A is not particularly limited, but is, for example, MoSixOyNz. The reversed-phase halftone film does not need to have a single-layer structure.
It may have a two-layer structure with a phase shift film such as CrOxNy or CrFx.

The in-phase halftone region 3B surrounding the anti-phase halftone region 3A is a region where the phase of light transmitted therethrough and the phase of light transmitted through the real pattern 2H are in phase, and are not particularly limited. For example, it is formed in an annular shape of an outer octagon with a width (width of a relatively wide area) of about 0.7 μm. The in-phase halftone film constituting the in-phase halftone region 3B may be a film obtained by changing the phase shift amount of the above-described one-layer or two-layer reversed-phase halftone film to 360 °, or a single-layer halftone film such as CrNx. But it is good. Further, Cr, MoSix or the like for forming a light shielding film may be thinned.

The light-shielding region 4 surrounding the in-phase halftone region 3B is a region that blocks light transmission as defined by the above-mentioned terms, and is, for example, a single film of Cr.MoSix or Cr or a laminated film of Cr and CrxOy. It is configured. However, the in-phase halftone region 3B may be extended and disposed in the arrangement region of the light shielding region 4 in FIG. 1 instead of the light shielding region 4. In addition, even if the in-phase halftone region is omitted, the reversed-phase halftone region is arranged around the actual pattern, and the light-shielding region is arranged outside the half-tone region, the effect of improving the depth of focus is obtained although the effect is inferior.

FIG. 9 is a graph comparing the depth of focus between the case where the mask 1 is used and the case where a normal inverted halftone mask is used. The same oblique illumination (zonal illumination) is used as the exposure light. The solid line shows the case where the mask of the present embodiment is used, and the broken line shows the case where a normal inverted halftone mask is used. It is understood from FIG. 9 that the use of the mask 1 of the present embodiment makes it possible to improve the depth of focus of the hole pattern even when oblique illumination is used as the exposure light source.

Next, a method for manufacturing the mask 1 will be described. In the first example of the method of manufacturing the mask 1, first, FIG.
As shown in FIG. 0, a mask substrate is prepared in which a light-shielding film 4a is applied on the main surface of a transparent substrate 1S via a reverse halftone film 3A1. Subsequently, as shown in FIG. 11, a photoresist pattern 5a is formed on the light-shielding film 4a so that the formation region of the actual pattern is exposed and the other portions are covered. The exposed light-shielding film 4a and the reversed-phase halftone film 3A1 are removed, and further, the photoresist pattern 5a is removed.
The mask substrate shown in FIG. 12 is obtained. Next, as shown in FIG. 13, a photoresist pattern 5b is formed on the light-shielding film 4a so as to cover the light-shielding region and expose the rest, and then using the photoresist pattern 5b as an etching mask, 4a, and further, the photoresist pattern 5b is removed to obtain a mask substrate shown in FIG. Subsequently, as shown in FIG. 15, a shifter film 3B1 for forming an in-phase halftone region is deposited on the main surface of the transparent substrate 1S. The shifter film 3B1 itself is made of, for example, SiOx.
It is made of a transparent film such as CrOxNy or CrFx having the same transmittance as that of the transparent substrate 1S, and is set so as to generate a phase difference of 180 degrees with respect to the phase of light transmitted through the actual pattern. That is, the in-phase halftone region 3B
(See FIG. 8) has a two-layer structure of the reverse halftone film 3A1 and the shifter film 3B1, and the phase of the light transmitted therethrough is the same as the phase of the light transmitted through the real pattern 2H (see FIG. 8). It is supposed to be. Thereafter, as shown in FIG. 16, a photoresist pattern 5c is formed on the shifter film 3B1 so that the light-shielding region and the in-phase halftone region are covered and the reverse-phase halftone region is exposed. As an etching mask, the exposed shifter film 3B1 is removed, and the photoresist pattern 5c is removed.
Is removed, and as shown in FIG. 17, the actual pattern 2H, the reverse halftone area 3A and the in-phase halftone area 3A are formed.
A mask 1 having B is obtained.

Next, in the second example of the method of manufacturing the mask 1,
First, as shown in FIG. 18, a mask substrate is prepared in which a light-shielding film 4a is applied on the main surface of a transparent substrate 1S via a reversed-phase halftone film 3A1, and a light-shielding region is coated on the light-shielding film 4a. After forming a photoresist pattern 5d exposing the rest, the light-shielding film 4a exposed from the photoresist pattern 5d is removed by using this as an etching mask.
The photoresist pattern 5d is removed to obtain a mask substrate shown in FIG. Subsequently, as shown in FIG. 20, a shifter film 3B1 for forming an in-phase halftone region is deposited on the main surface of the transparent substrate 1S, and thereafter, as shown in FIG. A photoresist pattern 5e is formed such that the reverse-phase halftone region is exposed and the in-phase halftone region and the light-shielding region are covered. Thereafter, using the photoresist pattern 5e as an etching mask, the shifter film 3B1 exposed from the photoresist pattern 5e is removed, and the photoresist pattern 5e is further removed.
The mask substrate shown in FIG. 22 is obtained. At this stage, the reverse pattern halftone film 3A1 is also coated on the area of the actual pattern. Next, as shown in FIG. 23, a photoresist pattern 5f is formed such that the region of the actual pattern is exposed on the main surface of the transparent substrate 1S and covers the reverse halftone region, the in-phase halftone region, and the light shielding region. After that, using this as an etching mask, the reverse halftone film 3A1 exposed therefrom is removed, and further, the photoresist pattern 5f is removed, as shown in FIG. A mask 1 having 3A and the in-phase halftone region 3B is obtained.

Next, in the third example of the manufacturing method of the mask 1,
First, as shown in FIG. 25, on the main surface of the transparent substrate 1S,
Unlike the above-described mask manufacturing example, the in-phase halftone film 3B
A mask substrate on which a light-shielding film 4a is applied via 2 is prepared. Subsequently, as shown in FIG. 26, a photoresist pattern 5g is formed on the light-shielding film 4a so as to cover the light-shielding region and expose the rest, and then the photoresist pattern 5g is exposed from here using this as an etching mask. The light-shielding film 4a is removed, and the photoresist pattern 5g is removed.
Is obtained. Thereafter, as shown in FIG. 28, a shifter film 3A2 is deposited on the main surface of the transparent substrate 1S. The shifter film 3A2 itself is made of, for example, SiOx.Cr.
It is made of a transparent film such as OxNy or CrFx having the same transmittance as that of the transparent substrate 1S, and is set so as to generate a phase difference of 180 degrees with respect to the phase of the light transmitted through the actual pattern. Next, as shown in FIG.
After forming a photoresist pattern 5h covering the actual pattern and the reverse phase halftone region on A2, the photoresist pattern 5h is used as an etching mask.
The shifter film 3A2 exposed therefrom is removed and the photoresist pattern 5h is removed to obtain a mask substrate shown in FIG. At this stage, the in-phase halftone film 3B2 remains. Subsequently, as shown in FIG. 31, after forming a photoresist pattern 5i on the main surface of the transparent substrate 1S such that the actual pattern formation region is exposed, the photoresist pattern 5i is used as an etching mask to expose the shifter film 3A2.
32 by removing the in-phase halftone film 3B2 and the photoresist pattern 5i.
As shown in (1), a mask 1 on which an actual pattern 2H, a reverse halftone region 3A and an in-phase halftone region 3B are formed is obtained. In this case, the reverse halftone area 3A is:
It has a two-layer structure of an in-phase halftone film 3B2 and a shifter film 3A2. The shifter film 3A2 constituting the reverse phase halftone region 3A has a function of inverting the phase of light, and the in-phase halftone film 3B2 has a function of lowering the light transmittance.

In any of the above-described mask manufacturing examples, the area around the actual pattern is formed by a halftone film. Therefore, the light transmittance can be reduced, so that even if it has a certain width, exposure can be performed so that it is not transferred to the photoresist film on the wafer.
In the above example, the minimum processing size of the halftone film is, for example,
It is about 0.3 μm, and if it is about this, processing does not become difficult.

Next, in the second specific example of the mask, FIG.
As shown in FIG.
The in-phase halftone region 3B is arranged over the entire periphery of H, and a pseudo repeated region centering on the actual pattern 2H is formed.

FIG. 34 shows the focus when the mask 1 is used, when the actual pattern size is further reduced by the structure of the mask 1, and when a normal inverted halftone mask is used. It is the graph which compared the depth. The same oblique illumination (zonal illumination) is used as the exposure light. The solid line is the case of the mask 1 and the case where the size of the actual pattern is made finer by the structure of the mask 1, and the broken line is the case where a normal reversed-phase halftone mask is used. This figure 3
4 shows that the depth of focus of the hole pattern can be improved even by using the in-phase halftone mask (mask 1 in FIG. 33). Further, the mask 1 shown in FIG.
Then, even if the hole diameter of the actual pattern 2H of the mask 1 is reduced,
As shown in FIG. 35, since the increase in the unnecessary light intensity ratio is small, the hole diameter of the actual pattern of the mask 1 is changed from 0.35 μm to 0.2 μm.
It can be reduced to 5 μm. In addition, when the hole diameter of the actual pattern is reduced as described above, the depth of focus can be improved as shown in FIG.

The method of manufacturing such a mask 1 is the same as described above, and an in-phase halftone substrate may be used as a mask substrate, or a 360 ° phase shift halftone substrate may be used.

Next, in a third specific example of the mask, FIG.
36, the real pattern 2H, the light-shielding region 4A, and the in-phase halftone region 3B are sequentially arranged stepwise from the center of FIG. A pseudo repeated region is formed.

Light shielding region 4 surrounding actual pattern 2H
A is disposed in the above-described primary proximity region, and is formed in an annular shape of an outer octagon having a width (width of a relatively wide region) of about 0.3 μm, for example. The constituent material of the light-shielding region 4A is the same as that of the above-described light-shielding region 4, and the description is omitted. Note that the outer peripheral shape of the light-shielding region 4A is not limited to the octagonal shape but can be variously changed. For example, even if the outer peripheral shape is a square which is a similar enlarged figure of the actual pattern 2H, there is no problem in the exposure performance.

FIG. 37 shows a case where the mask 1 is used, and FIG.
FIG. 7 is a graph comparing the depth of focus with the case where a normal inverted halftone mask is used. The same oblique illumination (zonal illumination) is used as the exposure light. The solid line is the case where the mask 1 of FIG. 36 is used, and the broken line is the case where the normal inverted halftone mask is used. It can be seen from FIG. 37 that the use of the mask 1 makes it possible to improve the depth of focus of the hole pattern even when oblique illumination is used as the exposure light source. In addition, as shown in FIG. 38, the unnecessary light intensity ratio in the case of using the mask 1 is smaller than that in the case of using the normal reversed-phase halftone mask.

In order to manufacture such a mask 1, first, as shown in FIG. 39, an in-phase halftone film 3B2 is formed on the main surface of a transparent substrate 1S in the same manner as in the third manufacturing method of the mask. A mask substrate having a light-shielding film 4a deposited thereon is prepared. Subsequently, as shown in FIG.
After forming a photoresist pattern 5j on which a region where a real pattern is to be formed is exposed and other regions are covered, the photoresist pattern 5j is used as an etching mask to form a light-shielding film 4a and an in-phase halftone region 3B2 which are exposed therefrom. Then, the photoresist pattern 5j is removed to obtain a mask substrate shown in FIG. Thereafter, as shown in FIG. 42, a photoresist pattern 5k is formed so as to cover the formation region of the actual pattern and the light-shielding region 4A (see FIG. 36) and to expose the rest, and then the photoresist pattern 5k is removed. As an etching mask, the light-shielding film 4a exposed therefrom is removed, and further, the photoresist pattern 5k is removed, as shown in FIG.
The mask 1 on which the actual pattern 2H, the light shielding area 4A and the in-phase halftone area 3B are formed is obtained. The mask 1 is easier to manufacture than the mask 1 shown in FIG. 8 because no reverse halftone film is provided.

In the example of the method of manufacturing the mask 1, the case where the in-phase halftone substrate described in the third manufacturing method of the mask is used as the mask substrate has been described. However, the present invention is not limited to this. The first of the masks
In the same manner as described in the second manufacturing method, the in-phase halftone region 3B may be formed by forming the shifter film 3B1 (see FIGS. 17 and 24) using an inverted-phase halftone substrate.

Next, in the fourth specific example of the mask, FIG.
44, the actual pattern 2H, the light-shielding region 4A, the in-phase halftone region 3B, and the light-shielding region 4 are sequentially arranged from the center of FIG. A pseudo repeating region centering on 2H is formed. The structure of the mask 1 is the same as that of the mask 1 shown in FIG. 8 except that the light-shielding region 4 is arranged in place of the reverse halftone region 3A. Note that the outer and inner peripheral shapes of the in-phase halftone region 3B are not limited to the octagonal shape and can be variously changed. For example, even if the square is a similar enlarged figure of the actual pattern 2H, the exposure performance does not interfere. .

FIG. 45 shows a result obtained by exposing the mask 1 of FIG. 44 by oblique illumination (a relatively thick solid line).
The result obtained by oblique illumination using a mask in which the hole diameter of the actual pattern of the mask 1 of FIG. 44 is reduced (a relatively thin solid line) is shown by small σ illumination using a normal reversed-phase halftone mask. (Dashed line), the result obtained by exposing with a small σ illumination using a mask in which the hole diameter of the actual pattern is enlarged in a normal reversed-phase halftone mask (relatively thick broken line), and the normal FIG. 9 is a graph comparing results (relatively thin broken lines) obtained by exposure using oblique illumination using a reversed-phase halftone mask. It can be seen that the effect of improving the depth of focus is more remarkable when the mask 1 shown in FIGS. 45 to 44 is used than when the inverted halftone mask is exposed by oblique illumination.

FIG. 46 shows that the inverse halftone mask has a small σ
FIG. 44 is a diagram comparing the unnecessary light intensity ratio in the case of performing exposure using illumination with the case of using the mask 1 in FIG. FIG.
(A) shows the case of an isolated hole pattern, and FIG. (B) shows the maximum on the vertical bisector of a line connecting the centers of holes in a one-way continuous hole in which pitch holes twice the assumed hole diameter are arranged. FIG. 3C shows the maximum unnecessary light intensity ratio of the continuous hole in two directions. In this two-way continuous hole, 1
The hole pitch in the direction is twice as large as the assumed hole diameter, and the other is the line connecting the center of the hole and the position giving the maximum unnecessary light intensity on the vertical bisector of the line connecting the centers of the holes in one direction. And the pitch was twice as large as the distance between the holes, and the continuous holes were arranged. FIG.
In Example 6, in Example Condition 1, when exposure processing was performed by oblique illumination (ring zone illumination) using the mask 1 of FIG. 44, Example Condition 2 reduced the hole diameter of the actual pattern of the mask 1 of FIG. When exposure processing is performed by oblique illumination (ring zone illumination) using a mask, the studied technical condition 1 is that when the exposure processing is performed using small σ illumination using a normal reversed-phase halftone mask, the studied technical condition 2 is normally In this case, exposure is performed using small σ illumination using a mask in which the hole diameter of the actual pattern of the reversed-phase halftone mask is enlarged.

When the mask 1 shown in FIG. 44 is used, many of the in-phase halftone regions are deleted due to the continuation of the hole pattern arrangement, but this is a repetitive pattern exhibiting the characteristics of annular illumination. Therefore, there is no concern about deterioration of the exposure performance. From the results shown in FIG. 46, it can be seen that when the reversed-phase halftone mask, which is the study technique, is exposed with small σ illumination, the unnecessary light intensity ratio increases in the continuous hole. When the hole diameter is not enlarged, the intensity ratio becomes 0.9 or more in the continuous holes in two directions, which is close to the light intensity with the edge of the hole pattern. Many parts are dissolved by development, and the remaining film becomes very thin. For this reason, when exposing a reversed-phase halftone mask with small σ illumination, which is a study technique, means for enlarging the hole diameter of the actual pattern in the mask is used.

The unnecessary light intensity ratio in this case is also included in FIG. The condition 2 of the study technique is as shown in FIG.
In the case of the isolated hole pattern, it can be seen that the unnecessary light intensity ratio is lower than that of the mask 1 in FIG. 44 when the hole diameter is reduced. However, in the case of the continuous hole in two directions, as shown in FIG. Due to the high spatial coherence of the illumination, FIG.
The unnecessary light intensity ratio exceeds the case where the hole diameter is reduced in the mask 1 of No. 4. In addition, when the hole diameter of the actual pattern of the mask 1 in FIG. 44 is reduced and the condition 2 of the study technique is compared, the effect of improving the depth of focus shown in FIG. The mask 1 shown in FIG. 44 is superior in the shown unnecessary light intensity ratio. Therefore, it is understood that this embodiment is a very useful resolution improving technique.

The manufacturing process of the mask 1 shown in FIG. 44 is substantially the same as the manufacturing process of the mask 1 shown in FIG. 36, although the area of the in-phase halftone region 3B changes. Also in this case, the width of the light-shielding region 4A near the actual pattern 2H (the width of the relatively wide region) is 0.
About 3 μm, width of in-phase halftone region 3B is 0.7 μm
This is not a difficult level for processing the mask 1. In the case of a continuous hole pattern, there is a possibility that the width of the in-phase halftone region 3B may become extremely narrow. However, this may be erased by enlarging / reducing the graphic data of the mask production in accordance with the mask processing level. However, since the continuous hole pattern has repeatability, it does not lead to deterioration of exposure performance at the time of annular illumination. Also, the actual pattern 2H
Is a light-shielding region 4A, so that a conventional mask correction technique can be applied. Since the in-phase halftone region 3B has a low transmittance and a large area, the tolerance for defects is large.

In the above description, the annular illumination conventionally used in the technology for improving the resolution of the line pattern is a representative example of the isolated pattern in order to prevent the deterioration of the pattern overlay accuracy due to the switching of the illumination system. The case where the present invention is also applied to the exposure of a hole pattern has been specifically described.

In the following, the method for improving the resolution of an isolated pattern in the case of using oblique illumination, which has been clarified in the present invention, is applied to the exposure of a line pattern, and the line is repeatedly arranged (periodically arranged). A technique for improving the resolution performance of an isolated line portion of a pattern or a line pattern at a repeated end (outermost) will be described. As a result, the present invention makes it possible to reinforce the weak points of many of the weak points inherent to oblique illumination, thereby applying a uniform illumination shape and preventing the pattern overlay accuracy from deteriorating. Becomes

First, the case where the actual pattern of the mask for transferring the line pattern is formed of a light transmitting region will be described, and the effect of improving the depth of focus of the isolated line portion or the line at the repetition end will be described. In the following example applied to a line pattern, a fourth specific example of the mask (FIG. 44)
Although the case where the same method as that described above is used will be described, similar effects can be obtained by using the method shown in the first to third specific examples (FIGS. 8, 33 and 36).

That is, in the fifth specific example of the mask according to the present embodiment, as shown in FIG. 47, the outer periphery of each actual pattern 2M is surrounded by the light shielding area 4A on the main surface of the mask 1, and The light shielding area 4 is arranged outside the light shielding area 4A via the in-phase halftone area 3B.

The plurality of actual patterns 2M are mask patterns for transferring a line pattern to a negative photoresist film on a wafer. Each of the plurality of actual patterns 2M is formed in a band shape and is repeatedly arranged in parallel with each other at a predetermined interval. Have been.
The transparent substrate of the mask 1 is exposed in the formation region of the actual pattern 2M, and the transmittance of light transmitted therethrough is equal to the transmittance of the transparent substrate. The actual pattern 2M is transferred as a line pattern similar in shape to the actual pattern 2M in the photoresist film (hereinafter, the same applies to a line pattern transfer mask).

Of the plurality of real patterns 2M, FIG.
The upper and lower portions of the real pattern 2M at the center of the area have no other real pattern 2M around it, and are isolated real pattern portions. Further, the outermost real pattern 2M among the plurality of real pattern 2M groups has no other real pattern on one side, and is substantially equivalent to an isolated real pattern (repeated end). In the case of the mask 1 in FIG.
By the above-described exposure processing using oblique illumination, it is possible to improve the resolution of the isolated real pattern portion and the pattern of the repeated end. Note that the constituent materials, transmittance, dimensions, and the like of the transparent substrate and the light-shielding regions 4 and 4A and the in-phase halftone region 3B that constitute the mask 1 are the same as those of the above-described fourth specific example. It is applied to this fifth example as it is.

FIG. 48 shows the defocus amount dependence of the line width of the line pattern calculated by the same method as the hole diameter calculation method of the hole pattern.
47B shows the line width at the center of the five repetition lines in FIG. 47, FIG. 47B shows the line size at the repeated end portion, and FIG. 47C shows the line width at the isolated line portion. In addition,
In this calculation, the relative exposure intensity at a position corresponding to the assumed line width of the center line in the width direction of the five repetition lines is set as the reference relative intensity. A relatively thin solid line indicates the case where the mask 1 of FIG. 47 is used, and a broken line indicates a normal mask (a normal mask having a mask pattern including a shielding region and a transmission region and having no phase shift film or halftone film). ) Is used.

In FIG. 48, since the annular illumination is used in both the case of using the mask 1 of FIG. 47 and the case of using the normal mask, as shown in FIG. There is almost no difference in the depth of focus in the line, and it is well shown that in the transfer of the repetitive pattern, a large effect of improving the depth of focus can be obtained only by the annular illumination. However, as shown in FIGS. 48 (b) and (c), the depth of focus is attenuated at the repetition end line including the isolated element and at the isolated line portion as compared with the repetition portion. It can be seen that the structure like the mask 1 in FIG. 47 improves the depth of focus even in the region including the isolated element.

Next, in the sixth specific example of the mask according to the present embodiment, the structure is almost the same as that of the fifth specific example. In the fifth specific example, the in-phase halftone region 3
B has the same transmittance as that of the hole pattern, but in the sixth specific example, the in-phase halftone region 3B
The transmittance was higher than that.

This is because, when the transmittance is increased, the unnecessary light intensity ratio increases to form an unnecessary pattern because the reference relative intensity after transfer is low in the hole pattern, whereas the line pattern has a high reference relative intensity. This is because the possibility that an unnecessary pattern is formed is small even if the transmittance is increased. This sixth
In the case of the specific example, the transmittance of the in-phase halftone region 3B is set to 13%, which is more than twice that of the hole pattern. The width of the in-phase halftone region 3B is the same as that of the hole pattern, but is not limited to this. There is no problem even if the width is changed according to the unnecessary light intensity ratio and the depth of focus improvement effect. .

In FIG. 48, the effect of improving the depth of focus in the case of the sixth specific example is also indicated by a relatively thick solid line. The manufacturing process of the mask in this case is the same as that of the fifth specific example, and the sensitivity to the defect in the in-phase halftone region 3B is slightly increased, but the advantage is the same. And
As in the sixth specific example, by selectively using the transmittance of the in-phase halftone region between the hole pattern and the line pattern, a large effect of improving the depth of focus can be obtained at the repeated end portion of the line pattern and the isolated pattern portion. Can be

In the fifth and sixth specific examples, the periphery of the actual pattern 2M of the mask 1 is the light-shielding area 4A. However, this is reversed similarly to the first specific example of the present embodiment. Similar effects can be obtained in the phase halftone region. Further, similarly to the second specific example, a structure in which the in-phase halftone region 3B is entirely provided without providing the light-shielding region 4A around the actual pattern of the mask 1 may be adopted. Further, in the fifth and sixth specific examples, the width of the in-phase halftone region is limited. However, the limitation is removed, a light-shielding region is arranged around the actual pattern of the mask 1, and the in-phase halftone region is further outside. May be arranged.

In the first to sixth specific examples of the present embodiment, the effect of improving the depth of focus (that is, resolution) has been shown when the actual pattern of the mask 1 is a light transmitting region. However, in the transfer of the current line pattern, it is general to use a mask in which the actual pattern of the mask is formed of a light-shielding region. Therefore, the following 7
In the specific examples of the eighth mask and the eighth mask, in the exposure technique using oblique illumination (such as annular illumination), a case will be described in which the actual pattern of the mask is formed of a light-shielding region. In addition,
Unless otherwise stated, the same conditions as those in the first to sixth specific examples are used.

First, a seventh specific example of the mask is a technique for improving the depth of focus using annular illumination when the actual pattern is formed of a light-shielding region, and is basically a diversion of the third specific example. . That is, as shown in FIG.
On the main surface, a real pattern 2M composed of a light-shielding region is arranged, a light-transmitting region 6A having a constant width is arranged so as to surround the periphery thereof, and an in-phase halftone region 3B is arranged outside thereof. ing. Since the in-phase halftone region 3B in this case is originally arranged in a region that becomes a light transmission region, its light transmittance needs to be high, for example, about 70%. In the light transmitting region 6A, the transparent substrate of the mask 1 is exposed, and its light transmittance is equal to the light transmittance of the transparent substrate. In this case, the line pattern is transferred to a positive photoresist film on the wafer.

FIG. 50 shows the effect of improving the depth of focus in this case. 49A shows the line width at the center of the five repetition lines in FIG. 49, FIG. 49B shows the line size at the repetition end, and FIG. Is shown. A relatively thin solid line indicates the case where the mask 1 of FIG. 49 is used, and a broken line indicates a normal mask (a normal mask having a mask pattern including a shielding region and a transmission region and having no phase shift film or halftone film). ) Is used.

In both the case of using the mask 1 of FIG. 49 and the case of using a normal mask, the annular illumination is used.
As shown in FIG. 50 (a), there is almost no difference in the depth of focus in the five lines at the center of the repetition. As shown in (b) and (c), the depth of focus is attenuated in the line at the repetition end including the isolated element and in the isolated line portion as compared with the repetition portion. It can be seen that the structure like the mask 1 in FIG. 49 improves the depth of focus even in a region including the isolated element.

Next, the eighth specific example of the mask is basically a diversion of the fourth embodiment, and as shown in FIG.
The in-phase halftone region 3B is formed in a band-like pattern, and the light transmission region 6B is arranged on the outer periphery thereof. In the seventh specific example, the width of the in-phase halftone region is not limited. However, in the eighth specific example, the width of the in-phase halftone region 3B is limited, and the width is substantially equal to that of the actual pattern 2M. It is about the same as the width. That is, in the eighth specific example, the in-phase halftone region 3B is arranged so that the isolated pattern portion and the repeated end portion also have pseudo repeatability. In this case as well, as shown by the relatively thick solid line in FIG. 50, even better effects can be obtained in the region having the isolated element than in the case of the seventh specific example.

As described above, in the seventh and eighth embodiments, the case where the actual pattern on the mask is formed of the light-shielding region in accordance with the condition widely used has been described. The same effect can be obtained even if it is replaced with a phase halftone region. Further, the in-phase halftone area 3B in the eighth specific example does not necessarily have to be in-phase, and may be replaced with an in-phase halftone area. Further, the light transmittance of the in-phase halftone region 3B is not only selectively used between the hole pattern and the line pattern as described above, but also as shown in the seventh and eighth specific examples, the light transmission region of the actual pattern of the mask is used. By using differently between the light-shielding regions, a large depth of focus improvement effect can be obtained.

In the exposure process using oblique illumination (ring zone illumination), by using the mask 1 shown in the fifth to eighth specific examples, the exposure process of the repetitive pattern by oblique illumination is performed. In this case, it is possible to improve the resolution of the isolated pattern portion and the repetition end portion, which are weak points.

In the exposure processing using oblique illumination of the hole pattern superimposed on the line pattern transferred by the mask 1 shown in the fifth to eighth embodiments, the first to fourth embodiments By using the mask 1 shown in the specific example, the resolution of the hole pattern can be improved, and the illumination of the same shape can be used in the exposure processing of the line pattern and the hole pattern. It is possible to improve the overlay accuracy with the pattern.

Next, the graphic data processing in the pattern design of the mask 1 will be described. The mask 1
With respect to the processing of graphic data for pattern design described above, a unit capable of collectively processing the similar enlargement or reduction of many graphics is called a layer. In other words, when processing of a different enlargement ratio or reduction ratio is required, it is necessary to register a figure in another layer.

First, the graphic data processing method of the mask 1 for hole pattern exposure will be described by taking the graphic data processing method of the mask 1 of the above specific example 4 (FIG. 44) as an example.

The graphic data processing method described here is a method of generating graphic data of the entire mask by repeating the operation of creating a unit cell and automatically attaching the unit cell to the entire surface of the mask. This unit cell includes, for example, an isolated real pattern, an inverted halftone pattern,
It has graphic data such as an in-phase halftone pattern and a halftone pattern arrangement prohibited area.
In the case of this method, when the size or shape of the actual pattern is different, a plurality of isolated unit cells may be created.

The unit cell in the case of the specific example 4 is shown in FIG.
It is shown in FIG. The unit cell UC is shown in FIG.
4 is the same as the pattern plan view of the mask shown in FIG. 4, but the data is divided into layers A to C, and each layer includes the actual pattern data 2HD, the in-phase halftone arrangement prohibited area data 4AD and the in-phase halftone. Pattern data 3BD is stored. The layers A to C are shown in FIGS. 53 (a) to 53 (c), respectively. A shown in FIG.
The layer has actual pattern data 2HD corresponding to the actual pattern.
Is stored. The in-phase halftone arrangement prohibited area data 4AD is stored in the layer B shown in FIG.
Here, for example, figure data of a plane octagon is stored. The in-phase halftone inclusion pattern data 3B including the in-phase halftone area is stored in the C layer shown in FIG.
D is stored. Here, for example, figure data of a plane octagon is stored. In any case, the storage of the graphic data is performed by inputting coordinates. Also, layer A,
The center coordinates of the B layer and the C layer are equal to each other, and the layers can be superposed and arranged.

To arrange an isolated hole pattern,
First, after arranging the actual pattern data 2HD at a desired position in the A layer, the in-phase halftone area arrangement prohibited area data 4AD of the B layer and the in-phase halftone pattern data 3BD of the C layer are additionally attached thereto. Note that the pattern data of the in-phase halftone region is obtained by subtracting the in-phase halftone placement prohibited area data 4AD from the in-phase halftone inclusion pattern data 3BD.

FIG. 54 is an enlarged plan view of a main part of the mask 1 when a plurality of hole patterns arranged at predetermined intervals are formed. On the right side of FIG. 54, an actual pattern 2H for transferring an isolated hole pattern is arranged. On the left side of FIG. 54, a plurality of actual patterns 2H for transferring a hole pattern are arranged relatively close to each other, and light-shielding regions 4A near each of them are connected to each other. In addition, the actual pattern 2H arranged on the rightmost side of the actual patterns 2H arranged close to each other is slightly apart from the other actual patterns 2H in the group, and the adjacent light-shielding area 4A Is separated from the adjacent light shielding area 4A. Further, when the mask having such a structure is expressed by the structure of the first specific example, the reversed halftone region 3A is arranged instead of the light shielding region 4A.

Actual pattern data of such a mask 1
55 to 57 show the in-phase halftone arrangement prohibited area data and the in-phase halftone inclusion pattern data. A plurality of A-layer actual pattern data 2HD are arranged at predetermined intervals corresponding to the arrangement of hole patterns. The in-phase halftone arrangement prohibited area data 4AD of the B layer is arranged so as to be connected to each other in the area near the hole pattern. In-phase halftone inclusion pattern data 3BD for layer C
Are also connected to each other in a region near the hole pattern. Also in this case, the center coordinates of the A layer, the B layer, and the C layer are equal to each other, and the layers can be overlapped and arranged.

In the data creation in this case, in the arrangement of the graphics in the B layer and the C layer, the same processing as the so-called logical OR processing is performed without considering the overlapping of the graphics, and the graphic data is created. ing. That is, from layer C to B
When the layers are subtracted, a figure of the in-phase halftone area data 3BD1 as shown in FIG. 58 is obtained. And
The mask 1 may be manufactured by patterning a resist for forming an actual pattern, a resist for forming an in-phase halftone region, and a resist for forming a light-shielding region using these graphic data. As described above, according to the graphic data creation processing using the unit cells, even if the shielding area 4A and the halftone area 3B are not similar to the actual pattern 2H, it is not necessary to perform any human judgment, and the graphic Since the arrangement of the figures can be performed only by the addition and subtraction of, the figure data processing for mask production can be easily automated.

As a result of these automatic processes, an in-phase halftone region that is unacceptably fine in the mask fabrication process may be generated. This location can be automatically detected and erased. Although the exposure performance may be degraded due to the erasure of the in-phase halftone area,
When erasing, it is because the actual patterns are arranged close to each other, that is, the pattern is approaching the repetitive pattern. Since the exposure is performed using the annular illumination, the performance degradation is small. The layer C can also be created by enlarging after copying the layer B. If a combination of both the method and the method using a unit cell is used, graphic data processing for mask production can be performed more easily than when only one method is used. In addition, the graphic data processing method of the mask 1 in the specific examples 1 to 3 is the same as the above method, and the same effect can be obtained in the graphic data processing in this case as well.

Next, the graphic data processing method of the mask 1 for line pattern exposure will be described by taking the graphic data processing method of the mask 1 of the above specific example 5 (FIG. 47) as an example.

The graphic data processing method described here is a method of automatically generating graphic data in an in-phase or in-phase halftone area by enlarging or reducing an actual pattern graphic.

First, as shown in FIG. 59, graphic data of the actual pattern data 2MD is created in the same manner as in the case of creating a normal mask, and this is set as the A layer. Subsequently, the layer obtained by copying the layer A is referred to as a layer B, and the layer B is enlarged by the width of the light shielding area near the actual pattern (so-called blowden processing), and as shown in FIG.
And this is defined as layer B. Then, after copying the layer B, it is enlarged by the width of the in-phase halftone area, and as shown in FIG. 61, the in-phase halftone inclusion pattern data 3BD is created, and this is set as the C layer. Subsequently, when the layer B is subtracted from the layer C, only the figure of the in-phase halftone area data 3BD1 remains as shown in FIG. Also in this case, the center coordinates of the A layer, the B layer, the C layer, and the D layer are equal to each other, and the layers can be overlapped and arranged. In this way, with this graphic data processing method, pattern data can be generated by automatic graphic data processing, as long as a graphic of an actual pattern is created, just as in the case of creating graphic data for normal mask production. It is.

As a result of these automatic processes, an in-phase halftone region that is unacceptably fine in the mask fabrication process may be generated. This point can be automatically detected, and if the graphic data in the in-phase halftone area is reduced by a similar amount by a certain amount and then expanded by the same amount, this point can be deleted. There is a concern that exposure performance may be degraded due to erasure of the in-phase halftone area.
This is because there is an actual pattern in close proximity, that is, the pattern is approaching a repetitive pattern. Since exposure is performed using annular illumination, performance degradation is small. Using these graphic data, a resist pattern for an actual pattern is superimposed on a resist pattern for an in-phase halftone region to manufacture the mask shown in FIG. The graphic data processing method for the mask 1 in the sixth and seventh specific examples is the same as the above method, and in this case, the same effect can be obtained with respect to the graphic data processing.

Like the graphic data processing of the hole pattern and the line pattern as described above, the mask manufacturing graphic data processing of the opposite-phase and in-phase halftone areas of the present invention is performed in the same manner as the normal pattern data of the mask. Is performed, the remaining part can be automatically processed. Therefore, it is easy to manufacture the mask 1 shown in the first to eighth specific examples.

In the following, there is a problem in the technique studied by the present inventor, that is, deterioration of overlay accuracy when patterns exposed using differently classified illumination are overlaid, that is, the present invention has dealt with as a premise. Using the specific example of the above-described mask 1, it is verified that exposure of both the hole pattern and the line pattern with the same classification of illumination can prevent the deterioration of the pattern overlay accuracy. In reality, it is known that when illumination belonging to another classification is used, the amount of aberration of the projection optical system changes, but this is ignored here, and it is thought that it cannot occur in reality, Description will be made on the assumption that the aberration amount of the projection optical system does not depend on the illumination system.

Here, a case will be described in which a line pattern arranged at a standard pitch is used as a base, a hole pattern is superimposed on the line pattern, and the projection optical system has coma. Also, a description will be given of a case where a base line pattern serving as a reference for pattern superposition is formed by exposing a normal mask having an actual pattern formed of a light-shielding region by annular illumination in a mask which is considered to be widely applied.

In this case, the hole pattern to be superimposed on the line pattern is formed by exposing the reversed-phase halftone mask with small σ illumination, and by shading the area around the real pattern shown in the fourth specific example. A mask 1 (see FIG. 44) having an in-phase halftone region on the outside and a light-shielding region on the outside was used for comparison with the case of exposure using annular illumination. FIG. 63 shows the coma aberration dependency of the overlay displacement.

FIG. 63A shows a case where both the line pattern and the hole pattern are isolated. FIG. 2B shows a case where the components are arranged at a standard pitch.
FIG. 3C shows a case where the line patterns are arranged at a standard pitch, and the hole patterns are arranged at a double pitch without changing the hole diameter. Even in the case of a large aberration amount, the position shift amount is small in the embodiment of the present invention.

FIG. 63 shows that even when the illumination system is switched and the aberration amount of the projection optical system is assumed to be constant, it is better to superimpose the patterns using the embodiment of the present invention. Although the amount was shown to be small, this figure itself is not the focus of the present invention. In addition to the effects shown in FIG. 63, the illumination condition can be limited by exposing both main line / hole patterns with the same classification illumination, and the projection optical system at the time of assembling and starting up an exposure apparatus that requires detailed adjustments It is necessary to take into account that the adjustment of the aberration is greatly reduced, the illumination can be adjusted to the same class of illumination, and the aberration itself can be greatly reduced.

Next, an example of an exposure apparatus used in the present embodiment will be described. As shown in FIG. 64, the reduction projection exposure apparatus 7 used in the present embodiment has a suction table 7a for suctioning and holding a semiconductor wafer 8, and in this exposure processing, an exposure operation is performed by a step-and-repeat method. Is made. The suction table 7a is an X-axis moving table 7 that moves in the horizontal direction.
b and the suction table 7a in the horizontal direction at right angles thereto.
Is provided on a Y-axis moving table 7c that moves
It can be moved up and down by the shaft moving table 7d. The exposure light source 7e is, for example, a mercury lamp,
It is assembled to the condenser mirror 7f. Exposure light source 7e
Has an oblique illumination light source shape as shown in FIG. 65 or FIG. FIG. 65 shows the ring illumination 7e1. FIG. 66 shows a four-aperture illumination 7e2. Note that the exposure light source may be replaced by an excimer laser such as KrF or ArF.

In the reduction projection exposure apparatus 7 shown in FIG. 64, the light emitted from the exposure light source is reflected by the plane reflection mirror 7g1.
, A shutter 7h, a fly-eye lens 7i, an aperture 7j, and a band-pass filter 7k. The light transmitted through the fly-eye lens 7i has its partial coherent coefficient (σ value) adjusted by the aperture 7j, and the illumination light other than the exposure light is cut off by the bandpass filter 7k. The exposure light applied to the plane reflection mirror 7g2 is further applied to the mask 1 via a mask blind 7m and a condenser lens 7n. The mask 1 is held by a mask holder 7p. The mask holder 7p can be finely moved in the vertical direction in FIG. In the plane area of the mask 1, the area to be transferred to the semiconductor wafer 8 is set such that the exposure light transmitted through the mask 1 by the mask blind 7m is applied to the photoresist film on the semiconductor wafer via the reduction projection lens 7q. Has become.

The exposure apparatus is not limited to the above-described step-and-repeat type exposure apparatus, but can be variously modified. For example, a step-and-scan type exposure apparatus may be used.

The step-and-scan method transfers a pattern while relatively moving a semiconductor wafer and a mask in opposite directions. That is, as shown in FIG. 67, for example, the exposure light 10 of the reduction projection exposure apparatus 9 is formed on the mask 9 after being formed by the slit 9a. Since the exposure light 10 and the exposure light source are the same as described above, the description is omitted. The mask 1 is held on a mask stage 9b. The exposure light transmitted through the mask 1 is
Irradiation is performed on the photoresist film on the main surface of the semiconductor wafer 8 via the reduction projection lens 9c. In this reduced projection exposure apparatus 9, the mask 1 and the semiconductor wafer 8 are designed to transfer a pattern into the semiconductor chips 11 of the semiconductor wafer while relatively moving in the opposite directions.

The feature of this method is that illumination light formed in a slit shape is used. In a reduced projection exposure apparatus which is not a scanning method, as shown in FIG. 68 (a), it is inscribed in the projection area 12 of the lens. While an exposure area such as a rectangle 13 close to a square is used, in the scanning exposure, a slit-shaped rectangle 14 is an exposure area as shown in FIG.

Next, a specific example of a mask when the mask of this embodiment is applied to an actual semiconductor integrated circuit device will be described with reference to FIG.
This will be described with reference to FIGS.

FIG. 69 shows a DRAM (Dynamic Random Acceses).
FIG. 2 is an enlarged plan view of a main part of the mask 1 in a case where the present invention is applied to a mask for forming an element isolation pattern of a memory (s Memory). FIG. 69 shows only the end of the memory cell array. This mask 1 is a mask to which the eighth specific example is applied.

A plurality of actual patterns 2 arranged on the mask 1
L is an active region of a memory cell (memory cell selection MISF).
This is a pattern corresponding to the source, drain and channel of the ET), and is formed here as a shielding region. In the actual pattern 2L, a convex portion is formed at the center of one long side thereof, and the planar positions of the convex portions are arranged so as to be shifted from each other in the upper and lower adjacent real patterns 2L in FIG.

A light transmitting region 6A having a predetermined width is arranged around the actual pattern 2L so as to be in contact with and surrounds the actual pattern 2L, and an in-phase halftone region 3B having a fixed width and high transmittance is arranged outside the light transmitting region 6A. Further, a light transmission area 6B is disposed outside the light transmission area 6B. Thereby, the depth of focus is improved as compared with the exposure processing using oblique illumination, and the resolution of the fine pattern is improved. In the case of this mask 1,
It is necessary to form the in-phase halftone region 3B slightly smaller than the size of the actual pattern 2L in the mask, but this is shown in the case where the erasure is not performed in the graphic data processing stage for the mask creation.

FIG. 70 is an enlarged plan view of a main part of the mask 1 when the present invention is applied to a mask for forming a gate pattern and an inter-gate wiring pattern of a DRAM. This mask 1 is also a mask to which the eighth specific example is applied. The actual pattern 2M corresponds to the gate pattern and the inter-gate wiring pattern, and is formed in a light-shielding region. Most of the actual pattern 2M constitutes a repeating pattern, and a part thereof is an isolated line portion and a repeating end. The other configuration is the same as that of FIG. 69, and the description is omitted.

Also in this case, the depth of focus is improved by the exposure process using oblique illumination, and the resolution of the fine line pattern is improved. In this case, the in-phase halftone region 3B finer than a certain width in the mask 1 is erased in the graphic data processing stage of the mask manufacturing process, and a pattern layout plan view after the erasure is shown.

In the exposure process using the mask 1 shown in FIGS. 69 and 70, the pattern is transferred to a positive type photoresist film deposited on a semiconductor wafer. Further, although the mask structure of the eighth specific example is applied here, the present invention is not limited to this, and the mask structures of the fifth, sixth, and seventh specific examples may be applied. It is also possible to use a normal mask that is a mask for transfer and that includes a light-shielding region and a transmission region.

FIG. 71 is an enlarged plan view of a main part of the mask 1 when the present invention is applied to a mask for forming a hole pattern for connecting a capacitor of a DRAM and a semiconductor region of a memory cell selection MIS • FET. FIG.
This mask 1 is a mask to which the fourth specific example is applied. A plurality of actual patterns 2H are arranged on the mask 1 at predetermined intervals. This actual pattern 2H corresponds to the above-mentioned hole pattern, and is formed in a light transmitting region. A light shielding area 4A is arranged around each actual pattern 2H. The light-shielding region 4A is connected between adjacent ones. An in-phase halftone region 3B is arranged around the shield region 4A, and further outside the shield region 4A.
Is arranged. In this case as well, the exposure processing using oblique illumination improves the depth of focus and improves the resolution of the fine hole pattern.

In the exposure process using the mask 1 shown in FIG. 71, a pattern is transferred to a positive type photoresist film deposited on a semiconductor wafer. Although the mask structure of the fourth specific example is applied here, the present invention is not limited to this, and the mask structures of the first, second, and third specific examples may be applied.

Next, the DR using the mask 1 as described above is used.
An example of a method for manufacturing an AM will be described in the order of steps with reference to FIGS.

First, as shown in FIG. 72, a p-type semiconductor wafer 8 having a specific resistance of about 10 Ωcm is wet-oxidized at about 850 ° C. to form a thin silicon oxide film 15 having a thickness of about 10 nm on its surface. A silicon nitride film 16 is deposited on the silicon oxide film 15 by a CVD (Chemical Vapor Deposition) method. Subsequently, the silicon nitride film 16
After a positive photoresist film 17a is deposited thereon, a pattern covering the active region is transferred onto the positive photoresist film 17a by an exposure process using the oblique illumination (for example, annular illumination). In this exposure processing, the mask 1 shown in FIG. 69 is used. Thereafter, using the patterned photoresist film 17a as an etching mask, the silicon nitride film 16 exposed therefrom is etched away to form a pattern of the silicon nitride film 16 as shown in FIG.

Next, by using the silicon nitride film 16 as an oxidation-resistant mask, the semiconductor wafer 8 is subjected to a thermal oxidation treatment, thereby forming a field insulating film 18 in the element isolation region of the semiconductor wafer 8 as shown in FIG. Form. Subsequently, after the silicon nitride film and the underlying silicon oxide film are removed by wet etching using hot phosphoric acid, n-type impurities, for example, P (phosphorus) are added to the semiconductor wafer 8 in a region (memory array) where memory cells are to be formed. ) Is ion-implanted to form an n-type semiconductor region 19, and p-type impurities, for example, B (boron) are ion-implanted into a part of the memory array and peripheral circuits (regions where an n-channel MISFET is formed). The well 20 is formed, and an n-type impurity, for example, P is ion-implanted into another part of the peripheral circuit (a region where the p-channel MISFET is formed) to form an n-type well. Then, following this ion implantation, MISF
An impurity for adjusting the threshold voltage of ET, for example, B
F ₂ (boron fluoride)) is ion-implanted into the p-type well 20 and the n-type well. The n-type semiconductor region 19
Are formed to prevent noise from entering the p-type well 20 of the memory array through the semiconductor wafer 8 from an input / output circuit or the like.

Next, after removing the silicon oxide films on the respective surfaces of the p-type well 20 and the n-type well using a HF (hydrofluoric acid) -based cleaning solution, the semiconductor wafer 8 is wet-oxidized at about 850 ° C. A clean gate oxide film 21 having a thickness of about 7 nm is formed on each surface of the mold well 20 and the n-type well.

Although not particularly limited, after the gate oxide film 13 is formed, the semiconductor substrate 1 is heat-treated in an NO (nitrogen oxide) or N ₂ O (nitrogen oxide) atmosphere to form the gate oxide film 21. Nitrogen may be segregated at the interface with the semiconductor wafer 8 (oxynitriding treatment). When the thickness of the gate oxide film 21 is reduced to about 7 nm, distortion generated at the interface between the semiconductor wafer 8 and the semiconductor wafer 8 due to a difference in thermal expansion coefficient becomes apparent, and hot carriers are generated. Nitrogen segregated at the interface with the semiconductor wafer 8 relaxes this distortion,
The above oxynitriding process can improve the reliability of the ultra-thin gate oxide film 21.

Next, a conductor film 22 (22a, 22b) for forming a gate electrode and a cap insulating film 23 are deposited on the gate oxide film 21. The conductor film 22a is made of, for example, low-resistance polysilicon, and the conductor film 22b is made of, for example, a silicide film such as tungsten silicide.
The cap insulating film 23 is made of, for example, a silicon nitride film. Subsequently, a negative photoresist film 17b is deposited on the cap insulating film 23.

Subsequently, the photoresist film 17b has
A pattern that covers the gate pattern and the inter-gate pattern is transferred by the exposure processing using the oblique illumination (for example, annular illumination). In this exposure processing, the mask 1 shown in FIG. 70 is used. Thereafter, using the patterned photoresist film 17b as an etching mask, the cap insulating film 23 and the conductor film 22 exposed therefrom are used.
Is etched to form a pattern of the gate electrode 22G as shown in FIG. The gate electrode 22G forms a part of the memory cell selecting MISFET, and functions as a word line WL in a region other than the active region. The width of the gate electrode 22G (word line WL), that is, the gate length, is a minimum dimension within an allowable range (for example, an allowable range where a short channel effect of the memory cell selecting MISFET can be suppressed and a threshold voltage can be secured to a certain value or more) 0.24 μm)
It consists of. In addition, two adjacent gate electrodes 22G
The interval between (word lines WL) is constituted by the minimum dimension (for example, 0.22 μm) determined by the resolution limit of photolithography. The gate electrode 22G may have a so-called polymetal structure in which a metal film such as tungsten is provided on a low-resistance polysilicon via a barrier metal film such as tungsten nitride or titanium nitride. Gate electrode 22G
When a part of (word line WL) is made of low-resistance metal (W), its sheet resistance can be reduced to about 2 to 2.5 Ω / □, so that word line delay can be reduced. . In addition, since the word line delay can be reduced without backing the gate electrode 14 (word line WL) with an Al wiring or the like, the number of wiring layers formed above the memory cell can be reduced by one.

Next, after removing the photoresist film 17b (see FIG. 75), an n-type impurity, for example, P (phosphorus) is ion-implanted into the p-type well 20 to form a p-type well 20 on both sides of the gate electrode 22G. By forming the n ^- type semiconductor region 24, the memory cell selection MIS
FET Qs is formed.

Subsequently, a silicon nitride film having a thickness of about 50 nm is deposited on the semiconductor wafer 8 by the CVD method, and is etched back by anisotropic dry etching to obtain a silicon nitride film as shown in FIG. Side walls 25 made of a silicon nitride film are formed on the side surfaces of the gate electrode 22G and the word lines WL.

Thereafter, an insulating film 26 made of, for example, a silicon oxide film is deposited on the main surface of the semiconductor wafer 8 by the CVD method, and a negative photoresist film 17 is formed thereon.
c.

Next, the photoresist film 17c has
A pattern in which the connection hole for the capacitor is exposed by the exposure process using the oblique illumination (for example, annular illumination) is transferred. At the time of this exposure processing, the mask 1 shown in FIG. 71 is used. Subsequently, by using the patterned photoresist film 17c as an etching mask, the cap insulating film 26 exposed therefrom is removed by etching to form a connection hole (hole pattern) 27a as shown in FIG. 78. At this time, the hole pattern 27 can be formed in a self-aligned and well-aligned manner by performing the etching process under such etching conditions that the etching selectivity between the silicon oxide film and the silicon nitride film is increased. Thereafter, as shown in FIG.
a, a plug 2 made of, for example, a low-resistance polysilicon film
8a is buried, and a plug 28b made of, for example, a low-resistance polysilicon film is buried in the connection hole 27b formed in the insulating film 26 in the same manner as the connection hole 27a.

Next, after an insulating film 29 made of a silicon nitride film was formed on the insulating film 26, a connection hole 27c was formed in the insulating film 29, and a conductor film for forming a bit line was formed. Thereafter, this is patterned to form a bit line BL. The bit line BL is made of, for example, tungsten or the like, and is connected to the memory cell selection MI through a plug 28b.
It is electrically connected to the semiconductor region 24 of the S-FET Qs. Subsequently, after an insulating film 30 made of, for example, a silicon oxide film is applied so as to cover the bit line BL, a connection hole 27d is formed in the insulating film 30 so that the upper surface of the plug 28a is exposed. Form. Then, after forming an insulating film 31 made of silicon nitride or the like on the insulating film 30, a capacitor 32 for storing information of the DRAM is formed. The capacitor 32 includes a lower electrode 32a, a capacitive insulating film 32b deposited on the surface thereof, and a plate electrode 32c formed thereon. Lower electrode 32a
Is made of, for example, low-resistance polysilicon, and has a plug 28
c, 28a are electrically connected to the semiconductor region 24 of the memory cell selection MIS • FET.

In this embodiment, for example, the following effects can be obtained.

(1) The depth of focus can be improved when an isolated pattern portion or a repeated end portion (repeated pattern equivalent portion) of an isolated pattern or a repeated pattern is transferred by oblique illumination. That is, the resolution of the pattern can be improved.

(2) According to the above (1), an exposure optical system belonging to the same classification can be used in the exposure processing for transferring an isolated pattern and the exposure processing for transferring a repetitive pattern. For this reason, it is possible to avoid deterioration of the pattern overlay accuracy caused by using the exposure optical systems belonging to different categories. In addition, by classifying the illumination for exposing in the fine pattern forming process into the same category,
The aberration adjustment of the projection optical system at the time of startup can be greatly reduced. Further, since the illumination can be adjusted to the same classification illumination, the aberration itself can be greatly reduced.

(3) Since an isolated pattern or an isolated pattern equivalent portion is transferred by using oblique illumination having a small influence without using small σ illumination having strong unnecessary light intensity at the time of exposure, unnecessary pattern transfer is avoided. It is possible to prevent the occurrence of a defect due to the transfer of the unnecessary pattern.

(4) According to the above (1), (2) and (3), miniaturization of an integrated circuit pattern can be promoted, and miniaturization and high performance of a semiconductor integrated circuit device can be promoted. Further, the performance of the semiconductor integrated circuit device can be improved. Further, the yield of the semiconductor integrated circuit device can be improved.

The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say,

For example, in the above embodiment, the case where a KrF excimer laser is used as an exposure light source has been described. However, the present invention is not limited to this.
F excimer laser (wavelength 248 nm), g of mercury lamp
Line (wavelength 436 nm), ArF excimer laser (wavelength 1
93 nm) or an exposure light source having a shorter wavelength than these.

Further, in the above-described embodiment, the case where the semiconductor wafer is constituted by a single silicon single crystal has been described. However, the present invention is not limited to this, and various modifications can be made. In the case of a so-called SOI (Silicon On Insulator) semiconductor wafer, which is provided with a thin semiconductor layer, and a so-called epitaxial wafer, which is provided with a thin epitaxial layer on the surface of a semiconductor substrate manufactured by Czochralski crystal growth method or the like The present invention can also be applied to

In the above description, the invention made mainly by the inventor has been described in terms of the DRA which is the field of application which has been the background.
Although the description has been given of the case where the present invention is applied to the manufacturing technique of the M, the present invention is not limited to this. For example, another memory circuit such as an SRAM or a flash memory (EEPROM) or a logic circuit such as a microprocessor
CD (Charge Coupled Device) and TFT (Thin Film)
Transisitor) It can be applied to a pattern forming technique of a liquid crystal display element and the like.

[0219]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, the depth of focus can be improved when an isolated pattern or an isolated pattern equivalent portion is transferred by oblique illumination. That is, the resolution of the pattern can be improved.

(2) According to the present invention, in the exposure processing for transferring an isolated pattern and the exposure processing for transferring a repetitive pattern, an exposure optical system belonging to the same classification can be used. For this reason, it is possible to avoid the deterioration of the pattern overlay accuracy caused by using the illumination optical systems (apertures) belonging to different classifications. In addition, by classifying the illumination for exposing the fine pattern forming process to the same classification,
The aberration adjustment of the projection optical system at the time of assembling and starting up the exposure apparatus can be greatly reduced. Further, since the illumination can be adjusted to the same classification illumination, the aberration itself can be greatly reduced.

(3) According to the present invention, small σ illumination with strong unnecessary light intensity is not used during exposure, and non-small σ
Since the isolated pattern or the isolated pattern equivalent portion is transferred using illumination, transfer of an unnecessary pattern can be avoided, and occurrence of a defect due to transfer of the unnecessary pattern can be prevented.

(4) According to the above (1), (2) and (3), miniaturization of an integrated circuit pattern can be promoted, and miniaturization and high performance of a semiconductor integrated circuit device can be promoted. Further, the performance of the semiconductor integrated circuit device can be improved. Further, the yield of the semiconductor integrated circuit device can be improved.

(5) According to the present invention, the dimensional accuracy can be relaxed by providing a pseudo repetitive region without providing a fine auxiliary pattern and forming the pseudo repetitive region by a halftone region. Since no problem arises even if the mask is formed to be relatively wide, it is possible to improve the ease of manufacturing the mask.

[Brief description of the drawings]

FIG. 1A is a diagram illustrating a case of an exposure technique using ordinary illumination, and FIG. 1B is an explanatory diagram illustrating a principle of oblique illumination that is an exposure technique according to an embodiment of the present invention.

FIGS. 2A and 2B are graphs for explaining a hole diameter calculation method used in the present embodiment.

FIG. 3 is a plan view of a main part of a mask used for evaluating an effect area of a reverse halftone area.

FIG. 4 is a graph showing an evaluation result of an effect region in a reverse-phase halftone region.

FIG. 5 is a graph comparing the effect of reducing the hole diameter of a mask.

FIGS. 6A and 6B are graphs for comparing unnecessary light intensity ratios.

FIGS. 7A and 7B are graphs for comparing unnecessary light intensity ratios when a halftone mask is used in an exposure process using oblique illumination.

FIG. 8 is an enlarged plan view of a main part of the mask of the present embodiment.

9 is a graph for explaining the effect of improving the depth of focus when the mask of FIG. 8 is used.

FIG. 10 is an enlarged cross-sectional view of a main part during a manufacturing step of the mask in FIG. 8;

11 is an enlarged cross-sectional view of a main part of the mask of FIG. 8 during a manufacturing step following that of FIG. 10;

FIG. 12 is an enlarged cross-sectional view of a main part of the mask of FIG. 8 during a manufacturing step following that of FIG. 11;

FIG. 13 is an enlarged cross-sectional view of a main part of the mask of FIG. 8 during a manufacturing step following that of FIG. 12;

FIG. 14 is an enlarged cross-sectional view of a main part of the mask in FIG. 8 during a manufacturing step following that of FIG. 13;

15 is an enlarged cross-sectional view of a main part of the mask of FIG. 8 during a manufacturing step following that of FIG. 14;

16 is an enlarged cross-sectional view of a main part of the mask of FIG. 8 during a manufacturing step following that of FIG. 15;

17 is an enlarged cross-sectional view of a main part of the mask of FIG. 8 during a manufacturing step following that of FIG. 16;

18 is an enlarged cross-sectional view of a main part during another manufacturing step of the mask in FIG. 8;

FIG. 19 is an enlarged cross-sectional view of a principal part in another manufacturing step of the mask of FIG. 8 subsequent to FIG. 18;

20 is an enlarged fragmentary cross-sectional view of the mask of FIG. 8 during another manufacturing step following that of FIG. 19;

21 is an enlarged cross-sectional view of a principal part in another manufacturing step of the mask of FIG. 8 subsequent to FIG. 20;

FIG. 22 is an enlarged cross-sectional view of a principal part in another manufacturing step of the mask of FIG. 8 subsequent to FIG. 21;

23 is an enlarged cross-sectional view of a principal part in another manufacturing step of the mask of FIG. 8 subsequent to FIG. 22;

24 is an enlarged cross-sectional view of a principal part in another manufacturing step of the mask of FIG. 8 subsequent to FIG. 23;

FIG. 25 is an enlarged cross-sectional view of a main part of still another manufacturing step of the mask in FIG. 8;

26 is an enlarged cross-sectional view of a main part of still another manufacturing step following that of FIG. 25 for the mask of FIG. 8;

FIG. 27 is an enlarged cross-sectional view of a main part of the mask in FIG. 8 during a further manufacturing step following FIG. 26;

FIG. 28 is an enlarged cross-sectional view of a principal part in still another manufacturing step following that of FIG. 27 of the mask of FIG. 8;

FIG. 29 is an enlarged cross-sectional view of a main part of the mask of FIG. 8 during a further manufacturing step following FIG. 28;

30 is an enlarged fragmentary cross-sectional view of the mask of FIG. 8 during a further manufacturing step following that of FIG. 29;

31 is an enlarged cross-sectional view of a main part of still another manufacturing step following that of FIG. 30 for the mask of FIG. 8;

32 is an enlarged cross-sectional view of a main part of still another manufacturing process following the mask 31 of FIG. 8;

FIG. 33 is an enlarged plan view of a main part of another mask of the present embodiment.

FIG. 34 is a graph showing the effect of improving the depth of focus when the mask of FIG. 33 is used.

FIG. 35 is a graph showing an unnecessary light intensity when the mask of FIG. 33 is used.

FIG. 36 is an enlarged plan view of a main part of a mask according to another embodiment of the present invention.

FIG. 37 is a graph showing the effect of improving the depth of focus when the mask of FIG. 36 is used.

FIG. 38 is a graph showing an unnecessary light intensity when the mask of FIG. 36 is used.

39 is a fragmentary cross-sectional view of the mask in FIG. 36 during a manufacturing step thereof;

40 is an essential part cross sectional view of the mask of FIG. 36 during a manufacturing step following FIG. 39;

41 is a fragmentary cross-sectional view of the mask in FIG. 36 during a manufacturing step following that of FIG. 40;

42 is a fragmentary cross-sectional view of the mask in FIG. 36 during a manufacturing step following that of FIG. 41;

43 is an essential part cross sectional view of the mask of FIG. 36 during a manufacturing step following that of FIG. 42;

FIG. 44 is an enlarged plan view of a main part of a mask according to another embodiment of the present invention.

FIG. 45 is a graph showing the effect of improving the depth of focus when the mask of FIG. 44 is used.

FIGS. 46A to 46C are graphs showing unnecessary light intensities when the mask of FIG. 44 is used.

FIG. 47 is an enlarged plan view of a main part of a mask according to another embodiment of the present invention.

48 (a) to (c) are graphs showing the effect of improving the depth of focus when the mask of FIG. 44 is used.

FIG. 49 is an enlarged plan view of a main part of a mask according to another embodiment of the present invention.

50 (a) to 50 (c) are graphs showing the effect of improving the depth of focus when the mask of FIG. 49 is used.

FIG. 51 is an enlarged plan view of a main part of a mask according to another embodiment of the present invention.

FIG. 52 is an explanatory diagram of a unit cell used for creating graphic data of the mask in FIG. 44;

53 (a) to 53 (c) are explanatory diagrams of each layer constituting the unit cell of FIG. 52.

FIG. 54 is an enlarged plan view of a main part of a mask according to another embodiment of the present invention.

FIG. 55 is an explanatory diagram of layers used for creating graphic data of the mask in FIG. 54;

FIG. 56 is an explanatory diagram of another layer used for creating graphic data of the mask in FIG. 54;

FIG. 57 is an explanatory diagram of another layer used for creating graphic data of the mask in FIG. 54;

FIG. 58 is an explanatory diagram of still another layer used for creating graphic data of the mask of FIG. 54;

FIG. 59 is an explanatory diagram of layers for describing a method of creating graphic data of the mask in FIG. 47;

60 is an explanatory diagram of another layer for describing a method of creating the graphic data of the mask in FIG. 47.

FIG. 61 is an explanatory diagram of another layer for describing a method of creating the graphic data of the mask in FIG. 47;

62 is an explanatory diagram of still another layer for describing a method of creating the graphic data of the mask in FIG. 47. FIG.

FIGS. 63 (a) to 63 (c) are diagrams illustrating the effect of preventing a pattern from being misaligned according to the present embodiment.

FIG. 64 is an explanatory diagram of an exposure apparatus used for exposure processing of the present embodiment.

FIG. 65 is an explanatory diagram of an exposure light source in the exposure apparatus of FIG. 64.

FIG. 66 is an explanatory diagram of an exposure light source in the exposure apparatus of FIG. 64.

FIG. 67 is an explanatory diagram of another exposure apparatus used for the exposure processing of the present embodiment.

FIG. 68 (a) is an explanatory view of an exposure apparatus studied by the present inventors, and FIG. 68 (b) is an explanatory view of the exposure apparatus of FIG. 67.

FIG. 69 is an enlarged plan view of a main part of a mask used for exposing an element isolation region according to another embodiment of the present invention.

FIG. 70 is an enlarged plan view of a main part of a mask used for exposing a gate pattern according to another embodiment of the present invention.

FIG. 71 is an enlarged plan view of a main part of a mask used for exposing a hole pattern according to another embodiment of the present invention.

FIG. 72 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step when the exposure processing according to the embodiment of the present invention is specifically applied;

73 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 72 when the exposure processing according to the embodiment of the present invention is specifically applied;

74 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 73 when the exposure processing according to the embodiment of the present invention is specifically applied;

75 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 74 when the exposure processing according to the embodiment of the present invention is specifically applied;

76 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 75 when the exposure processing according to the embodiment of the present invention is specifically applied;

77 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 76 when the exposure processing according to the embodiment of the present invention is specifically applied;

78 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following FIG. 77 in a case where the exposure processing according to the embodiment of the present invention is specifically applied;

79 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 78 to which the exposure processing according to the embodiment of the present invention is specifically applied;

[Explanation of symbols]

Reference Signs List 1 mask (super-resolution mask) 2H actual pattern (first actual transmission area) 2HD actual pattern data 2M actual pattern (first actual transmission area, first actual light-shielded area) 2MD actual pattern data 2L actual pattern (first 3A In-phase halftone area 3B In-phase halftone area 3BD1 In-phase halftone area data 3BD In-phase halftone inclusion pattern data 4 Light-shielding area 4A Light-shielding area 4AD In-phase halftone placement prohibited area data 5a Photoresist pattern 6A, 6B Light transmission area 7 Reduction projection exposure apparatus 7a Suction table 7b X-axis movement table 7c Y-axis movement table 7d Z-axis movement table 7e Exposure light source 7e1 Ring illumination 7e2 Four-aperture illumination 7f Condensing mirror 7g1 Flat reflecting mirror 7g2 Flat reflecting mirror 7h Shutter 7i Fly-eye lens 7j Aperture 7k Dom pass filter 7m Mask blind 7n Condenser lens 7p Mask holder 7q Reduction projection lens 8 Semiconductor wafer 9 Reduction projection exposure apparatus 9a Slit 9b Mask stage 9c Reduction projection lens 10 Exposure light 11 Semiconductor chip 15 Silicon oxide film 16 Silicon nitride films 17a to 17c Photoresist film 18 Field insulating film 19 N-type semiconductor region 20 P-type wafer 21 Gate oxide film 22 Conductive films 22a and 22b for forming gate electrode 23 Cap insulating film 24 n ^- type semiconductor region 25 Side wall 26 Insulating film 27a To 27d connection hole 28a to 28c plug 29 insulating film 30 insulating film 31 insulating film 32 capacitor 32a lower electrode 32b capacitance insulating film 32c plate electrode UC unit cell 50 mask 51 actual pattern 52 Negative phase halftone area 53 Light shielding area

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Shuhei Yamaguchi 3-3-2 Fujibashi, Ome-shi, Tokyo Inside Hitachi Tokyo Electronics Co., Ltd. (72) Shoji Hotta 3--16-3, Shinmachi, Ome-shi, Tokyo Inside Hitachi, Ltd. Device Development Center (72) Inventor Seiichiro Shirai 6-16, Shinmachi, Ome-shi, Tokyo 3 Inside Hitachi, Ltd. Device Development Center (72) Inventor Goichi Yokoyama 6-16, Shinmachi, Ome-shi, Tokyo Katsumi Tsune, Inventor Katsumi Tsune 6-chome, Shinmachi, Ome-shi, Tokyo F-term (reference) 2H095 BA02 BA07 BB02 BB03 5F046 AA25 BA04 BA05 BA08 CB17

Claims (20)

[Claims] 1. An integrated circuit pattern corresponding to a hole pattern on a super-resolution mask is non-small illuminated using ultraviolet exposure light, and the transmitted light is passed through a reduction projection optical system to a photoresist on a semiconductor integrated circuit wafer. In a method for manufacturing a semiconductor integrated circuit device in which the hole pattern is transferred onto the semiconductor integrated circuit wafer by reducing and projecting the film on a film, the super-resolution mask has the following configuration: (B) a first substrate provided on the first main surface of the transparent substrate;
(C) an in-phase halftone having the same phase with respect to the first real transmission region provided around the first real transmission region on the first main surface of the transparent substrate. region. 2. The method according to claim 1, wherein said photoresist film is a positive type. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein the non-small σ illumination is oblique illumination. 4. The method for manufacturing a semiconductor integrated circuit device according to claim 3, wherein said oblique illumination is annular illumination. 5. The method according to claim 4, wherein a transmittance of the in-phase halftone region is less than 10%. 6. A non-small σ illumination of an integrated circuit pattern on a super-resolution mask using ultraviolet exposure light, and the transmitted light is reduced and projected onto a photoresist film on a semiconductor integrated circuit wafer through a reduction projection optical system. In the method of manufacturing a semiconductor integrated circuit device for transferring the integrated circuit pattern onto the semiconductor integrated circuit wafer, the super-resolution mask has the following configuration: (a) first and second main surfaces (B) a first substrate provided on the first main surface of the transparent substrate;
(C) a first light-shielding region provided in a primary proximity area on the first main surface of the transparent substrate with respect to the first actual transmission region; (d) a first light-shielding region of the transparent substrate An in-phase halftone region having the same phase as the first actual transmission region provided around the first light-shielding region on the first main surface. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 6, wherein said integrated circuit pattern is a hole pattern on said wafer. 8. The method according to claim 7, wherein said non-small σ illumination is oblique illumination. 9. An integrated circuit pattern on a super-resolution mask is illuminated with ultraviolet exposure light, and the transmitted light is reduced and projected onto a photoresist film on a semiconductor integrated circuit wafer through a reduction projection optical system. In the method of manufacturing a semiconductor integrated circuit device for transferring the integrated circuit pattern onto the semiconductor integrated circuit wafer, the super-resolution mask has the following configuration: (a) a transparent substrate having first and second main surfaces; (B) a first substrate provided on the first main surface of the transparent substrate;
(C) an anti-phase opposite to the first real transmission area provided in a first-order proximity area on the first main surface of the transparent substrate with respect to the first real transmission area; A phase halftone region; (d) an in-phase halftone region having the same phase as the first real transmission region provided around the anti-phase halftone region on the first main surface of the transparent substrate. . 10. The method according to claim 9, wherein the illumination is a non-small σ illumination. 11. The method according to claim 10, wherein said integrated circuit pattern is a hole pattern on said wafer. 12. An integrated circuit pattern on a super-resolution mask is illuminated with ultraviolet exposure light, and the transmitted light is reduced and projected onto a photoresist film on a semiconductor integrated circuit wafer through a reduction projection optical system. In the method of manufacturing a semiconductor integrated circuit device for transferring the integrated circuit pattern onto the semiconductor integrated circuit wafer, the super-resolution mask has the following configuration: (a) a transparent substrate having first and second main surfaces; (B) a first substrate provided on the first main surface of the transparent substrate;
(C) an anti-phase opposite to the first real transmission area provided in a first-order proximity area on the first main surface of the transparent substrate with respect to the first real transmission area; (D) 2 relating to the first actual transmission region around the anti-phase halftone region on the first main surface of the transparent substrate;
An in-phase halftone region having the same phase as that of the first real transmission region provided in the next proximity region; and (e) around the in-phase halftone region on the first main surface of the transparent substrate. The provided light shielding area. 13. The method according to claim 12, wherein the illumination is a non-small σ illumination. 14. The method according to claim 13, wherein the integrated circuit pattern is a hole pattern on the wafer. 15. An integrated circuit pattern on a super-resolution mask is illuminated non-smallly with ultraviolet exposure light, and the transmitted light is reduced and projected onto a photoresist film on a semiconductor integrated circuit wafer through a reduced projection optical system. In the method of manufacturing a semiconductor integrated circuit device for transferring the integrated circuit pattern onto the semiconductor integrated circuit wafer, the super-resolution mask has the following configuration: (a) first and second main surfaces (B) a first substrate provided on the first main surface of the transparent substrate;
(C) a first light-shielding region provided in a primary proximity area on the first main surface of the transparent substrate with respect to the first actual transmission region; (d) a first light-shielding region of the transparent substrate An in-phase halftone area having the same phase as the first real transmission area provided in a secondary proximity area related to the first real transmission area around the first light shielding area on the first main surface. (E) a second light-shielding region provided around the in-phase halftone region on the first main surface of the transparent substrate. 16. The method according to claim 15, wherein the non-small σ
A method for manufacturing a semiconductor integrated circuit device, wherein the illumination is oblique illumination. 17. The method according to claim 16, wherein the integrated circuit pattern is a hole pattern on the wafer. 18. A non-small illumination of an integrated circuit pattern on a super-resolution mask using ultraviolet exposure light, and the transmitted light is reduced and projected onto a photoresist film on a semiconductor integrated circuit wafer through a reduction projection optical system. In the method of manufacturing a semiconductor integrated circuit device for transferring the integrated circuit pattern onto the semiconductor integrated circuit wafer, the super-resolution mask has the following configuration: (a) first and second main surfaces (B) a first substrate provided on the first main surface of the transparent substrate;
(C) a light-shielding region provided on an outer edge region of the transparent substrate on the first main surface with respect to the first real transmission region; (d) the first main surface of the transparent substrate An in-phase halftone region having the same phase as the first real transmission region provided between the first real transmission region and the light shielding region. 19. The method according to claim 18, wherein the non-small σ
A method for manufacturing a semiconductor integrated circuit device, wherein the illumination is oblique illumination. 20. The method according to claim 19, wherein the integrated circuit pattern is a hole pattern on the wafer.