JP4363012B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to manufacture a semiconductor device in which randomly arranged contact holes and via holes are formed with a fine pattern pitch and a fine size to be miniaturized and integrated. Regarding the method.
[0002]
[Prior art]
With the miniaturization of electronic devices and high integration of integrated circuits, the dimensions of semiconductor design patterns have become shorter than the wavelength of visible light.
Specifically, for example, the gate length of the gate electrode of the MOS transistor has a so-called deep submicron fine width, and a contact hole of a circuit formed by developing a resist applied on the wafer substrate and The via hole pattern is required to further reduce the hole width and the pitch between holes.
[0003]
On the other hand, in a semiconductor device, in order to improve the degree of integration and to process a large amount of data at high speed, a so-called memory cell and logic in which a memory element such as a DRAM and a logic element are simultaneously formed on the same chip, for example. In recent years, the elements are mixedly mounted. In such a semiconductor device, it is necessary to form a dense pattern and a sparse pattern on the same chip. For example, focusing on the contact hole and via hole portions of transistors, the hole patterns of memory elements are arranged densely and regularly, whereas the hole patterns of logic elements are arranged relatively sparsely and randomly.
In a semiconductor device in which a logic element or a logic element and a memory element are mixedly mounted, it is necessary to form contact holes and via holes with random arrangement as described above with good resolution and process margin.
[0004]
However, if the minimum rule approaches the limit of the processing accuracy of a processing device or technology due to miniaturization of the design pattern of the semiconductor device, the processing accuracy of the circuit pattern is lowered, and the circuit pattern cannot be processed as designed.
For example, if the above-mentioned randomly arranged holes are formed on a photomask with the same design width and transferred onto the wafer by exposure and etching using the photomask, the size of the holes formed on the wafer is different. As a result, the characteristics of the semiconductor device vary and the performance and yield as an integrated circuit are reduced.
[0005]
Factors that reduce processing accuracy include, for example, line width variations due to process instability, line width variations on the photomask, and line width variations on the photomask and semiconductor substrate due to dependency on pattern density. Etc. Among them, as a main factor of line width variation due to pattern density dependence, for example, in photolithography, when a mask pattern that has been miniaturized until it approaches the limit resolution of the exposure apparatus is exposed and transferred to a photoresist film or the like So-called optical proximity effect (OPE: Optical Proximity Effect), in which close-in light interferes with each other in fine areas close to each other in fine patterns, the exposure image is distorted, and the mask pattern of the photomask cannot be accurately transferred In addition, when etching, the mask pattern is faithfully transferred to the thin film on the semiconductor substrate by etching the side of the thin film (side etching), etching from below the thin film (undercut), or deposits such as reaction products. There are so-called etching conversion differences. In addition, the effects of the optical proximity effect and the etching conversion difference change depending on the pattern density dependency.
[0006]
Furthermore, in order to form a stepped pattern such as a contact hole or a via hole, it is important to secure not only the resolution but also the depth of focus.
Assuming that the wavelength of light of photolithography is λ and the numerical aperture of the projection optical system of photolithography is (NA), the resolution R of the exposure apparatus is k₁Λ / (NA) and DOF (Depth of Focus) is k₂・ Λ / (NA)²Determined by Where proportional coefficient k₁, K₂Depends on the characteristics of the photolithographic optical system, that is, the exposure apparatus, such as the shape of the light source, the resist sensitivity, the characteristics of the resist process, the characteristics of the light that has passed through the mask pattern, and the pupil function of the objective lens. Currently k₁= 0.5, k₂= Achieved to about 0.5.
As can be seen from the definitions of the resolution R and the depth of focus DOF, the resolution is improved by shortening the wavelength and increasing the numerical aperture. At the same time, the depth of focus DOF rapidly decreases in proportion to the square of (NA). Therefore, conventionally, research has been conducted on how to ensure both resolution and depth of focus when forming a stepped pattern such as a contact hole or a via hole.
Conventionally, in order to form contact holes and via holes with a reduced width and pitch and randomly arranged, a phase shift mask and a two-beam illumination method are used to improve lithography resolution R and depth of focus DOF. Thus, a finer hole is formed. Further, the optical proximity effect correction is added to the above method to form a random hole pattern.
[0007]
A phase shift mask is a photomask that can change the phase of light by providing a transparent thin film (phase shifter) on the mask and delaying the propagation speed of light rays. Using a phase shift mask improves the resolution of photolithography while increasing the depth of focus by using interference between light that has passed through the shifter and whose phase has changed and light that has not passed through the shifter and has not changed phase. Therefore, it can be applied to hole pattern transfer exposure.
[0008]
In addition, the two-beam illumination method is a technique called deformed illumination, which limits the incident angle of light that illuminates a mask or reticle (hereinafter collectively referred to as a reticle) to the reticle, thereby reducing the depth of focus for a fine pattern. Can be secured.
In photolithography, light that irradiates a reticle vertically is irradiated with 0th-order, ± 1st-order, ± 2nd-order ... diffracted light by a fine pattern on the reticle surface to the pupil of the lithography projection optical system. If the second-order and subsequent diffraction lights are set to be cut by the pupil, an image is formed on the wafer by interference of the 0th-order and ± 1st-order diffraction lights, which is so-called three-beam interference.
In the case of light that illuminates the reticle obliquely, either the + 1st order or the −1st order is cut by the pupil, and an image is formed by two-beam interference, which is so-called two-beam interference. The resolution by two-beam interference is higher than that by three-beam interference. Further, since the two-beam interference has a smaller convergence angle of the wavefront on the wafer surface, the obtained depth of focus DOF is also large.
When the modified illumination method is actually used, the image light component due to the three-beam interference is reduced and the two-beam interference component due to the off-axis illumination is increased by shielding the central portion of the light source and limiting the incident angle to the reticle. As a result, if the depth of focus for a fine pattern is ensured, the resolution can be improved and applied to transfer exposure of a hole pattern.
[0009]
Further, when the adjacent patterns are very close to each other on the reticle by the above method, the above-described optical proximity effect (OPE) occurs. In particular, the closer the pattern is, the more prominent the optical proximity effect is and the thinner the line width.
In order to suppress the optical proximity effect and accurately transfer the reticle pattern to the resist film, optical proximity effect correction (OPC: Optical Proximity Correction) is performed. Specifically, in anticipation of the optical proximity effect, correction such as enlargement or reduction of the size of the hole pattern on the reticle is performed in advance, and exposure and transfer to the resist film, thereby forming a dense pattern and a sparse pattern, Holes with almost the same dimensions can be obtained. Since each hole is corrected, even a random pattern can be formed.
In order to perform the optical proximity correction, the amount of correction for the reticle pattern needs to be determined in advance by an experiment or the like for each exposure process of the circuit pattern.
[0010]
Conventionally, holes having fine widths and pitches are randomly arranged by combining the above methods.
However, the conventional method described above has the following drawbacks.
First, when the hole pattern layout is random, it is effective to perform an optical proximity effect in order to obtain a desired hole size. However, correction is made by reducing or expanding the hole size on the reticle. The depth of focus changes at each location.
For example, in order to form a hole having a size of 0.30 μm on the wafer, 0.28 μm in terms of the same magnification on the reticle (actually 1.12 μm for a 4 × mask and 1.4 μm for a 5 × mask) Is preferable. At this time, the exposure optical conditions are NA = 0.55, σ = 0.60 (σ: aperture ratio, or coherence factor, ie, the ratio between the numerical aperture of the illumination optical system and the numerical aperture of the projection optical system). When the resist film thickness is 1.12 μm, the depth of focus DOF is 0.6 μm. However, when the hole size on the reticle is corrected to 0.26 μm or 0.30 μm to correct the optical proximity effect, the DOF becomes about 0.4 μm, which is small. This may reduce the process margin.
[0011]
Further, a halftone phase shift reticle provided with a light transmission part and a semi-light-shielding part has been used for forming a fine hole pattern arranged randomly. When such a phase shift reticle is used to form a fine and dense pattern, a desirable peak (sub-peak) is generated between the light peaks due to the light transmitting portion due to the optical proximity effect. This is a major obstacle to the practical application of halftone phase shift reticles.
In the case of using a halftone phase shift reticle, annular illumination in which the shape of the light source is transformed into an annular shape is used in order to reduce the influence of the sub-peak. However, when forming a fine hole using annular illumination and a halftone phase shift reticle, fine adjustment is necessary so that the annular ratio of the illumination system matches the line width of the hole pattern. A hole may not be formed with a slight defocus. For example, as shown in FIG. 27, when a 0.30 μm hole is exposed and transferred using a halftone phase shift reticle, the best focus condition is compared with the 0.2 μm defocused condition. There are holes that are well formed but crushed under defocus conditions.
[0012]
In addition, when the Levenson phase shift reticle is used, the phase of the diffracted light from the adjacent openings of the reticle is changed by 180 °, so that there is a contradiction in the random hole arrangement that must be the same phase. Occur, that is, phase mismatch occurs. In order to avoid phase mismatch, it is necessary to use a plurality of reticles for one exposure. Further, in the pattern arrangement, there is a drawback that the Levenson phase shift method cannot be used in isolated holes.
[0013]
In the case of using two-beam illumination, a random arrangement includes a layout suitable for two-beam illumination and a layout not suitable for the two-beam illumination. Therefore, a hole layout with an increased process margin and a layout with a reduced process margin are mixed.
Specifically, two-beam illumination is suitable for relatively regular patterns. For regular patterns with periodicity, since diffracted light is generated in a specific direction, the incident angle of the light that illuminates the reticle to the reticle is limited, and the depth of focus for a fine pattern is ensured by two-beam illumination. Can do. As such a relatively regular pattern, for example, a layout having a relatively high density and a periodicity locally (for example, in the range of several tens of μm), and regular “islands” are randomly distributed in a large area. In this case, the layout area may be arbitrary, and the hole is not placed on the lattice point, but the pattern is a layout with a very high density.
[0014]
On the other hand, in the isolated or random pattern, the diffracted light is not generated only in a specific direction, so that the depth of focus does not increase even when the modified illumination technique is used. A hole pattern such as a contact hole is a typical example of such a pattern.
FIG. 28 shows an example in which a 0.30 μm hole is exposed and transferred using a normal reticle in a pattern in which locally dense areas and sparse areas are mixed. Comparing the best focus condition with the 0.2 μm defocused condition, the hole is well formed under the best focus condition, but the width is significantly different under the defocus condition.
[0015]
[Problems to be solved by the invention]
Therefore, when forming a hole pattern having a minute width and pitch randomly arranged, when using the above-described conventional technique, when correcting the optical proximity effect, the manufacturing method is complicated and the optical proximity After effect correction, the depth of focus changes depending on the location, the process margin cannot be ensured by the layout, and if the halftone phase shift reticle and annular illumination are used, the depth of focus will be reduced depending on the layout, and the process margin will be reduced. The two-beam illumination has drawbacks such as a small depth of focus using a reticle and a small process margin.
[0016]
The present invention has been made in view of the above problems, and an object of the present invention is to provide a method for manufacturing a semiconductor manufacturing apparatus that can achieve a reduction in hole width even when the pitch between holes is reduced and has a sufficient process margin. There is.
[0017]
[Means for Solving the Problems]
A method for manufacturing a semiconductor device according to a first aspect of the present invention is a method for manufacturing a semiconductor device in which a plurality of via holes or contact holes (hereinafter simply referred to as holes) are randomly arranged in an insulating film on a lower wiring layer. An auxiliary pattern data generation step for generating auxiliary pattern data that completely includes the design pattern of the plurality of holes according to the design pattern of the plurality of holes and the wiring pattern of the lower layer wiring layer, and the lower layer wiring layer Forming a hole etching mask film on the upper insulating film; and transferring the auxiliary pattern to the hole etching mask film using a photomask prepared from the auxiliary pattern data; Holes having the same width as the plurality of holes are periodically repeated on the plane at the same pitch as the design pitch of the plurality of holes. Using the photomask having the dense hole pattern formed by returning, the dense hole pattern is transferred to the insulating film using the hole etching mask film to which the auxiliary pattern is transferred as an etching stopper, and the desired design pattern Forming a plurality of holes, and embedding a conductive material in the holes formed in the hole forming step to connect to the lower wiring layer.
[0018]
In the auxiliary pattern, the width of the pattern is not less than the design width of the via hole or contact hole. The auxiliary pattern is a slit pattern.
[0019]
The auxiliary pattern data generation step includes a first step of extracting a hole formation region on the design pattern of the plurality of holes and a second step of extracting a wiring formation region on the wiring pattern of the lower wiring layer. And calculating a logical OR of the pattern of the hole forming region and the pattern of the wiring forming region to generate data of the auxiliary pattern.
[0020]
The first step reverses the pattern obtained in the third step, a third step of inverting the design pattern of the plurality of holes and calculating the logical OR of the dense hole pattern and the graphic, In the inverted pattern, in the fourth step in which sizing processing is performed so that adjacent dot patterns are joined, and in the pattern obtained in the fourth step, the pattern width becomes the pattern width of the auxiliary pattern. And a sizing process.
[0021]
Alternatively, in the first step, a sizing process is performed so that adjacent dot patterns are joined in the fifth step of inverting the design pattern of the plurality of holes and the pattern obtained in the fifth step. A sixth step of performing, and a step of performing a sizing process so that the pattern width of the pattern obtained in the sixth step becomes the pattern width of the auxiliary pattern.
The second step further includes a step of inverting the wiring pattern of the lower wiring layer and a step of performing a sizing process so that the width of the inverted wiring pattern becomes the pattern width of the auxiliary pattern.
[0022]
A method of manufacturing a semiconductor device according to a second aspect of the present invention is a semiconductor in which a plurality of via holes or contact holes (hereinafter simply referred to as holes) are randomly arranged in an insulating film between a lower wiring layer and an upper wiring layer. A method of manufacturing an apparatus, comprising: an auxiliary pattern data generation step for generating auxiliary pattern data that completely includes the design pattern of the plurality of holes by using the design pattern of the plurality of holes and the wiring pattern of the upper wiring layer; A step of forming an upper wiring layer etching mask film on the insulating film on the lower wiring layer; a step of transferring a wiring groove pattern of the upper wiring layer to the upper wiring layer etching mask film; An etching mask for holes so as to cover the etching mask film for the upper wiring layer on which the wiring groove pattern of the upper wiring layer is transferred on the insulating film A step of transferring the auxiliary pattern to the hole etching mask film using a photomask prepared from the auxiliary pattern data, and a hole having the same width as the plurality of holes. Using a photomask having a dense hole pattern formed periodically and repeatedly on a plane at the same pitch as the design pitch of a plurality of holes, using the etching mask film for holes to which the auxiliary pattern is transferred as an etching stopper, Transferring the dense hole pattern to the insulating film, and forming a plurality of holes of the desired design pattern.
[0023]
The pattern width of the auxiliary pattern is greater than the design width of the via hole or contact hole. The auxiliary pattern is a slit pattern.
[0024]
After the hole forming step, the step of removing the etching mask film for the hole, and after removing the etching mask film for the hole, the etching mask for the upper wiring layer in which the pattern of the wiring groove of the upper wiring layer is transferred Etching the insulating film using the film as an etching mask, forming a wiring groove in the upper wiring layer, and forming a plurality of holes reaching the lower wiring layer together with the formation of the wiring groove; A step of embedding a conductive material in the wiring trench and the plurality of holes and connecting to the lower wiring layer; a step of planarizing the conductive material; and a step of removing the etching mask film for the upper wiring layer.
[0025]
The auxiliary pattern data generation step includes a first step of extracting a hole formation region on the design pattern of the plurality of holes and a second step of extracting a wiring formation region on the wiring pattern of the upper wiring layer. And calculating a logical OR of the pattern of the hole forming region and the pattern of the wiring forming region to generate data of the auxiliary pattern.
[0026]
The first step reverses the pattern obtained in the third step, a third step of inverting the design pattern of the plurality of holes and calculating the logical OR of the dense hole pattern and the graphic, In the inverted pattern, in the fourth step in which sizing processing is performed so that adjacent dot patterns are joined, and in the pattern obtained in the fourth step, the pattern width becomes the pattern width of the auxiliary pattern. And a sizing process.
[0027]
Alternatively, in the first step, a sizing process is performed so that adjacent dot patterns are joined in the fifth step of inverting the design pattern of the plurality of holes and the pattern obtained in the fifth step. A sixth step of performing, and a step of performing a sizing process so that the pattern width of the pattern obtained in the sixth step becomes the pattern width of the auxiliary pattern.
The second step further includes a step of inverting the wiring pattern of the upper wiring layer, and a step of performing a sizing process so that the width of the inverted wiring pattern becomes the pattern width of the auxiliary pattern.
[0028]
According to the semiconductor device manufacturing method of the first aspect of the present invention, when forming a fine hole pattern randomly arranged on the wiring layer, the random fine hole pattern is directly formed. In addition, an auxiliary pattern that has a line width larger than that of the desired hole and that completely includes the desired hole pattern, and a regular dense hole that is configured by holes having the same width and design pitch as the desired hole pattern. A desired fine random hole pattern can be obtained by sequentially transferring the pattern onto the semiconductor substrate.
[0029]
Specifically, a film that functions as an etching mask film when forming holes is formed in advance, and the auxiliary pattern is transferred to the film. Since the auxiliary pattern completely includes the desired hole pattern, the desired hole pattern is formed in the opening formed on the etching mask film after the auxiliary pattern is transferred.
Subsequently, the dense hole pattern is transferred to the insulating film. At that time, the etching mask film functions as an etching stopper, and the dense hole pattern is transferred only to the opening of the auxiliary pattern on the etching mask film, and etching in a region other than the opening is performed by the etching mask film. Therefore, unnecessary holes are not formed, and only desired holes are formed.
[0030]
As described above, since the desired hole pattern is formed by sequentially transferring the auxiliary pattern and the dense hole pattern onto the semiconductor substrate, the logical OR of the auxiliary pattern and the dense hole pattern is performed. The result of the (OR) operation must be a desired hole pattern. For this reason, the auxiliary pattern is based on the wiring pattern of the wiring layer and the desired hole pattern, and the auxiliary pattern and the dense hole pattern are The result of the graphic logical sum (OR) operation is made to be a desired hole pattern.
[0031]
According to the method for manufacturing a semiconductor device of the second aspect of the present invention, when a fine hole pattern randomly arranged is formed between the lower wiring layer and the upper wiring layer, the first method of the present invention is used. The random fine hole pattern is not directly formed, but the wiring groove pattern of the upper wiring layer has a line width larger than the width of the desired hole, and completely includes the desired hole pattern. A desired fine random hole pattern is obtained by sequentially transferring a regular dense hole pattern constituted by holes having the same width and design pitch as the desired hole pattern onto the semiconductor substrate.
However, since the upper wiring layer is formed after the fine random hole pattern is formed, it is necessary to protect the insulating film between the wiring trenches from being removed when the hole pattern is formed by etching. Therefore, it is necessary to form an etching mask film that protects the inter-groove insulating film of the upper wiring groove prior to the hole forming etching mask film. After the desired hole pattern and upper wiring groove pattern are formed, the etching mask film for the upper wiring layer is removed.
[0032]
In order to generate the auxiliary pattern, first, a region for forming all holes on a desired hole pattern is extracted by a graphic operation, and then a wiring is formed on the wiring pattern of the lower (or upper) wiring layer. Extract regions. Subsequently, the auxiliary pattern can be produced by appropriately enlarging the pattern of the hole formation region and the pattern of the wiring formation region and calculating the logical OR of the two.
[0033]
Therefore, according to the present invention, an auxiliary pattern having a large pattern width that can be formed relatively easily, and a regular dense hole pattern that can be formed relatively easily, avoiding the direct formation of fine random hole patterns. By sequentially transferring the pattern onto the semiconductor substrate and transferring the dense hole pattern, the auxiliary pattern functions as an etching mask, so that a fine, randomly arranged hole pattern with a small pitch that is difficult to form directly can be obtained.
In order to transfer regular dense hole patterns, it is easy to use super-resolution technology, achieve a reduction in hole width, easily reduce the pitch, and form a random fine hole pattern . In addition, since the auxiliary pattern having a large pattern width is transferred, the process margin can be improved.
Furthermore, since a random fine pattern is not directly formed, optical proximity effect correction is not necessary. Therefore, the optical proximity effect correction does not reduce or enlarge the size of the hole on the reticle, the process margin is high, and the manufacturing process is simple.
[0034]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the manufacturing method of the present invention will be described below with reference to the accompanying drawings.
First embodiment
In the present embodiment, an example of a method of generating auxiliary reticle pattern data for forming a contact hole or a via hole will be described.
The auxiliary tick pattern needs to have a pattern width larger than that of the desired hole pattern and completely include the desired hole pattern. With such an auxiliary tickle pattern, a region where a desired hole pattern is formed is covered with a large size, and the region is secured. Therefore, the auxiliary reticle pattern is related to a “hole forming region” including a portion where all desired holes are to be formed.
However, as described above, in order to form the desired hole pattern by transferring the dense hole pattern having the width and the pitch of the desired hole pattern after the auxiliary pattern is transferred, the auxiliary pattern is the same as the dense hole pattern. It is essential that the result of the logical OR (OR) operation is a desired hole pattern. In other words, for the desired hole pattern, the dense hole pattern has a large number of unnecessary holes, so the auxiliary pattern needs to block them so that unnecessary holes on the dense hole pattern are not transferred. . Otherwise, unnecessary holes are formed on the wafer.
[0035]
If the width of the auxiliary reticle pattern is made larger than the width of the desired hole, and the wiring pattern of the wiring layer connected to the hole of the desired pattern is used, the auxiliary reticle pattern satisfying the above conditions can be formed.
A large number of slit-like wiring patterns (or wiring grooves) are arranged in the wiring layer. Two via holes are formed in the insulating layer on the wiring layer at both ends of each slit-like wiring pattern, and are connected to both ends of the slit wiring pattern. Alternatively, a connection hole is formed in the insulating layer inside the both ends of each slit pattern and is connected to the slit pattern.
The holes are not formed because they are insulated by the insulator between the slit patterns. In other words, the holes are formed in the inner region of the wiring pattern.
Therefore, all the desired hole formation areas are extracted, and then the wiring areas are extracted from the wiring pattern and used to eliminate holes in the external area of the wiring pattern from the hole forming area. The auxiliary pattern is obtained.
[0036]
Next, a method for generating auxiliary reticle pattern data will be described with reference to FIGS.
In the specific example described below, the design rule is that the pitch between wiring patterns (semiconductor device design pitch) is 0.40 μm, the line width of the wiring is 0.20 μm, and the hole width is 0.20 μm in units on the wafer. The minimum design grid size is 0.01 μm.
[0037]
From Step 1 to Step 6, processing for a desired hole pattern will be described.
Step 1:
As shown in FIG. 1, the pattern A is a part of a desired hole pattern, and the subsequent processing is limited to the inside of the boundary of the pattern A shown.
First, according to the pattern A, the part which should form a hole is opened, and a design hole pattern (data) is prepared. In pattern A, the white dot pattern is an open hole, the hole width d is 0.20 μm, and the pitch p is 0.40 μm, which is a design rule.
[0038]
Step 2:
As shown in FIG. 1, pattern A is inverted to obtain pattern B.
[0039]
Step 3:
As shown in FIG. 2, a pattern D is obtained by performing a graphic OR (logical sum) operation on the pattern B and the dense hole pattern C.
In the dense hole pattern C, the hole width is 0.20 μm and the hole pitch is 0.40 μm, which is the same as the pattern A. Such holes are periodically repeated two-dimensionally to form a dense hole pattern C.
In the graphic OR (logical sum) operation, the OR of the black dot pattern and the black dot pattern is black, the OR of the black dot pattern and the white dot pattern is black, and the OR of the white dot pattern and the white dot pattern is white. It becomes.
[0040]
Step 4:
As shown in FIG. 3, pattern D is inverted to obtain pattern E.
[0041]
Step 5:
As shown in FIG. 4, the pattern E is enlarged twice and a pattern F is obtained. Specifically, as shown by the pattern E in FIG. 4, the length of each side of each dot of the pattern E is 0.20 μm, and both ends are extended while moving each side in parallel, Continue until 0.40 μm. As a result, adjacent dots in the pattern E are joined together, and the minimum line width of the pattern becomes 0.40 μm.
[0042]
Step 6:
As shown in FIG. 5, the pattern F is subjected to reduction sizing so that the minimum line width is 0.24 μm. Specifically, both ends of the length of each side are reduced while moving each side of each black pattern in the pattern F by 0.08 μm parallel to the inside.
The white portion of the pattern G is a wider hole formation region. Comparing the pattern G and the pattern A, it can be seen that all the holes opened in the pattern A are included in the white portion of the pattern G.
Here, if the graphic OR of the pattern G and the pattern C is performed, the pattern A is obtained. That is, if the pattern C is transferred after the pattern G is transferred, a desired hole pattern (pattern A) is obtained. However, in general, the hole formation region of the pattern G can be further limited by using the wiring pattern or the wiring groove pattern to which the hole of the pattern A is connected.
[0043]
From step 7 to step 9, the process for the wiring pattern or wiring groove pattern will be described.
Step 7:
As shown in FIG. 6, a pattern J obtained by sizing the wiring pattern or the wiring groove pattern H to 0.24 μm is obtained. That is, in the pattern H, both ends are extended while moving each side of each slit pattern having a minimum line width of 0.20 μm parallel to the outside by 0.02 μm. Thus, each slit pattern of the pattern H has the same minimum line width as the pattern G.
[0044]
Step 8:
As shown in FIG. 7, pattern J is inverted to obtain pattern K. The black portion of the pattern K is a region where no hole is formed between the slit-like wiring patterns.
[0045]
Step 9:
As shown in FIG. 8, a pattern L is obtained from the pattern K and the pattern G by a graphic OR operation.
The pattern L is used as auxiliary reticle pattern data for securing a region for forming a hole.
The pattern L is composed of a slit pattern. Since the line widths of the patterns G and K are expanded to 0.24 μm from the hole width (0.20 μm) of the desired pattern A, the slit pattern of the pattern L has a larger hole opening area than the desired hole pattern. As a result, there is no problem even if a positional deviation between the slit pattern of the pattern L and the wiring pattern occurs to some extent, and the process margin is high.
In the slit pattern constituting the pattern L, the size of each slit pattern is 0.24 μm × 0.40 μm, 0.24 μm × 0.56 μm, excluding two 0.24 μm × 0.16 μm slit patterns at the boundary. 0.24 μm × 0.64 μm, and the minimum width of the slit pattern is 0.24 μm, which is larger than the hole width of pattern A of 0.20 μm.
The minimum interval between the slit patterns is 0.16 μm.
[0046]
Step 10:
As described above, after transferring the pattern L as the auxiliary reticle pattern, the pattern C as the dense hole pattern is transferred and the pattern A as the desired hole pattern is formed. The result of the graphic OR operation must be the pattern A. Therefore, in step 10, as shown in FIG. 9, it is possible to verify that pattern A is obtained by performing a pattern OR operation on patterns C and L.
[0047]
According to the present embodiment, an auxiliary pattern is obtained using the obtained desired hole pattern and a wiring pattern or a groove pattern connected to the desired hole pattern, and the result of the auxiliary pattern, the dense hole pattern, and the graphic OR operation is obtained as the desired hole pattern. Since it becomes a pattern, a desired hole pattern can be formed by transferring a dense hole pattern after transferring the auxiliary pattern. Therefore, avoid direct formation of fine random hole patterns, and transfer auxiliary patterns with a large pattern width that can be formed relatively easily and regular dense hole patterns that can be formed relatively easily onto a semiconductor substrate in sequence. Then, by making the auxiliary pattern function as an etching mask when transferring the dense hole pattern, a fine, randomly arranged hole pattern with a small pitch which is difficult to form directly can be obtained. Further, since the pattern width of the auxiliary pattern is increased, the process margin is high.
[0048]
Second embodiment
In this embodiment, another example of a method of generating auxiliary reticle pattern data for forming a contact hole or a via hole will be described with reference to FIGS.
In the specific example described below, which is the same as that of the first embodiment, the pitch between wiring patterns (semiconductor device design pitch) is 0.40 μm, the line width of the wiring is 0.20 μm, and the hole width is 0.1. Assume that the design rule is 20 μm, and the minimum design grid size is 0.01 μm.
[0049]
Step 1:
As shown in FIG. 10, the pattern A is a part of a desired hole pattern.
First, according to the pattern A, the part which should form a hole is opened, and a design hole pattern (data) is prepared. In the pattern A, the white dot pattern is an opened hole, the hole width d is 0.20 μm, and the pitch p is 0.40 μm.
[0050]
Step 2:
As shown in FIG. 10, pattern A is inverted to obtain pattern B.
[0051]
Step 3:
As shown in FIG. 11, pattern B is enlarged twice to obtain pattern M. Specifically, both ends of each dot pattern of the pattern B are extended in parallel to the outside, and both ends are extended until each side reaches 0.40 μm. As a result, the adjacent dot patterns in the pattern B are joined to each other, and the minimum line width of the pattern becomes 0.40 μm.
[0052]
Step 4:
As shown in FIG. 12, pattern M is inverted to obtain pattern N.
[0053]
Step 5:
As shown in FIG. 13, the pattern N is obtained by reducing sizing the pattern N so that the minimum line width is 0.24 μm. Specifically, both ends of the length of each side are reduced while moving each side of the black pattern in pattern N in parallel by 0.08 μm.
The white portion of the obtained pattern O is a wider hole formation region. Comparing the pattern O and the pattern A, it can be seen that all the holes opened in the pattern A are included in the white portion of the pattern O.
Comparing with the pattern G of the first embodiment, it can be seen that the pattern O and the pattern G are different only in the right side and the lower side. Therefore, the pattern O has the same effect as the pattern G.
[0054]
Next, the hole formation region of the pattern O can be further limited by using a wiring pattern or a wiring groove pattern to which the hole of the pattern A is connected.
The processing method of the wiring pattern or the wiring groove pattern is the same as that of the first embodiment. That is, the pattern J obtained by sizing the wiring pattern or the wiring groove pattern H to 0.24 μm is obtained, and the pattern J is inverted to obtain the pattern K.
[0055]
Step 6:
As shown in FIG. 14, a pattern P is obtained from the pattern K and the pattern O by a graphic OR operation.
The pattern P is used as auxiliary reticle pattern data for securing a region for forming a hole.
Compared with the pattern L of the first embodiment, the pattern P and the pattern L are substantially the same, and therefore the pattern P has the same properties and effects as the pattern L.
That is, the pattern P is composed of a slit pattern. Since the line width of the pattern P is expanded to 0.24 μm from the hole width (0.20 μm) of the desired pattern A, the slit opening pattern of the pattern P has a larger hole opening area than the desired hole pattern. Thus, even if a positional deviation between the slit pattern of the pattern P and the wiring pattern occurs to some extent, there is no problem and the process margin is high.
In the pattern P, the minimum width of the slit pattern is 0.24 μm, which is larger than the hole width of the pattern A of 0.20 μm. The minimum interval between the slit patterns is 0.16 μm.
[0056]
Step 7:
As in the first embodiment, as shown in FIG. 15, it is possible to verify that the pattern A is obtained by performing a graphic OR operation on the pattern C and the pattern P.
[0057]
The present embodiment has the same effect as the first embodiment.
[0058]
Third embodiment
In the present embodiment, an example in which the present invention is specifically applied to the manufacture of a semiconductor device will be described. Specifically, a desired hole pattern connected to the wiring layer is formed on the wiring layer having a predetermined pattern.
Similar to the above-described embodiment, in this embodiment, a design rule in which the pitch between wiring patterns is 0.40 μm, the line width of the wiring is 0.20 μm, and the hole width is 0.20 μm in units on the wafer is taken as an example.
As shown in FIG. 16, the semiconductor device of this embodiment has a lower AlCu wiring 1 in advance and silicon oxide (SiO 2).₂There is a base on which an interlayer insulating film 2 made of The AlCu wiring layer 1 has a wiring pattern such as a pattern H. In this embodiment, a method for forming a fine random hole pattern such as the pattern A in the interlayer insulating film 2 will be described. Note that the AlCu wiring layer 1 shown in FIG. 16 (and FIGS. 17, 18, and 19) corresponds to a cross section taken along the broken line on the pattern H in FIG.
In the present invention, the pattern A is not directly used to form a fine random hole pattern such as the pattern A. Instead, for example, the auxiliary reticle pattern composed of the pattern L is transferred to the etching mask film, and the dense hole pattern composed of the pattern C is sequentially transferred to the interlayer insulating film 2 using the etching mask as an etching stopper. A random hole pattern A is formed.
[0059]
First, as shown in FIG. 16A, an amorphous silicon film 3 (amorphous Si: a-Si) is formed on the interlayer insulating film 2 to a thickness of 50 nm by a CVD (Chemical Vapor deposition) method. The amorphous silicon film 3 is used as an etching mask so as not to form unnecessary holes when the dense hole pattern C is transferred.
[0060]
Next, as shown in FIG. 16B, a resist 4 for transferring the auxiliary pattern L is applied on the amorphous silicon film 3. As the resist 4, a resist that is sensitive to the wavelength of a KrF excimer laser used for exposure is applied.
In FIG. 16B, a slit pattern having a cross section along the broken line is transferred onto the pattern L on the right side. In the cross-sectional view of the semiconductor substrate on the left side of FIG. 16B, broken lines and arrows indicate portions that should be exposed to the resist 4 corresponding to the pattern L.
[0061]
Next, as shown in FIG. 17A, the resist 4 is exposed and developed using the auxiliary pattern L as a reticle, and an opening is formed in the resist 4 corresponding to the cross-sectional pattern along the broken line on the right pattern L. do.
Here, a normal reticle made of chromium is used as a reticle that functions as an auxiliary pattern and has a pattern L. Further, exposure is performed using normal illumination with NA = 0.60 using an exposure machine using a KrF excimer laser.
[0062]
Next, as shown in FIG. 17B, the amorphous silicon film 3 is etched using the resist 4 as an etching mask, and corresponds to the pattern of the cross section along the broken line on the pattern L on the right side of FIG. Open to the amorphous silicon film 3. Then, the resist 4 is removed.
[0063]
Next, in FIG. 17C, an antireflection film made of an organic material is applied (not shown). Then, a resist 5 for transferring the pattern A is applied. As the resist 5, a resist that is sensitive to the wavelength of a KrF excimer laser used for exposure is applied.
In FIG. 17C, a cross-sectional pattern along the broken line is transferred to the pattern A on the right side. In the cross-sectional view of the semiconductor substrate on the left side of FIG. 17C, a portion to be exposed to the resist 5 corresponding to the pattern A on the right side is indicated by a broken line and an arrow.
[0064]
Next, as illustrated in FIG. 18A, the resist 5 is exposed and developed using the dense hole pattern C as a reticle, and a pattern having a cross section along the broken line is formed on the resist 5.
The holes constituting the dense hole pattern C have the same hole width as 0.20 μm and the hole pitch of 0.40 μm. Such holes form a pattern C by repeating two-dimensionally periodically.
Here, a halftone phase shift reticle is used for a reticle having a dense hole pattern. The exposure is performed using an exposure machine using a Kr-F excimer laser under the 1/2 annular illumination condition of NA = 0.60 so that an unnecessary pattern due to the sub-peak is not transferred.
As described above, in the present invention, the pattern A is not directly used to form a fine random hole pattern such as the pattern A. Instead, after transferring the auxiliary pattern to the amorphous silicon film 3, the dense hole pattern C is transferred to the interlayer insulating film 2.
As shown in FIG. 18A, since fine holes are densely packed in the pattern C at a fine pitch, more unnecessary openings than holes in the pattern A (portions indicated by arrows and broken lines) are present. Is formed in the resist 5.
[0065]
Next, as shown in FIG. 18B, the interlayer insulating film 3 is etched using the resist 5 and the antireflection film (not shown) as an etching mask to form holes in the interlayer insulating film 3. Then, the resist 5 is removed.
In the step shown in FIG. 18A, unnecessary openings are also formed in the resist 5 at the same time. However, the previously formed amorphous silicon film 3 is etched into the interlayer insulating layer 12 through these unnecessary openings. Blocking and unnecessary holes are not formed in the interlayer insulating layer 2.
[0066]
Next, as shown in FIG. 19A, after the resist 5 is removed, tungsten 6 is connected to the buried underlying AlCu wiring 1 by CVD.
Subsequently, unnecessary tungsten 6 is removed by a CMP (Chemical Mechanical Polishing) method. At this time, the amorphous silicon is also removed.
Here, a fine random hole pattern such as the pattern A connected to the AlCu wiring layer 1 whose wiring pattern is the pattern H was formed.
[0067]
In the present embodiment, the combination of the normal reticle and the normal illumination is used in the process shown in FIG. 17A. However, the combination of the halftone phase shift reticle and the annular illumination can of course form a good pattern. it can.
In the step shown in FIG. 18A, the halftone phase shift reticle and annular illumination are used. However, the present invention is not limited to this, and a good hole pattern can be formed even by a combination of Levenson phase shift and normal illumination. A good hole pattern can also be formed by a combination of normal reticle and four-hole illumination.
Further, when an ArF excimer laser is used, a good hole pattern can be formed even with a combination of a normal reticle and normal illumination in the steps shown in FIGS. 17A and 18A.
[0068]
According to this embodiment, in order to form a fine random hole pattern such as the pattern A, it is not necessary to use the pattern A directly. Instead, for example, when the auxiliary reticle pattern consisting of the pattern L and the dense hole pattern consisting of the pattern C are sequentially transferred and the dense hole pattern is transferred, if the etching mask to which the auxiliary reticle pattern is transferred is used as an etching stopper, A random hole pattern is formed.
In this way, it is possible to avoid forming a minute random hole pattern directly, and to form an auxiliary pattern having a large pattern width that can be formed relatively easily and a regular dense hole pattern that can be formed relatively easily on a semiconductor substrate. Therefore, it is possible to form fine, randomly arranged hole patterns with a small pitch that are difficult to form directly.
[0069]
In order to transfer a regular dense hole pattern, it is easy to use a super-resolution technique, the hole width can be easily reduced, and the pitch can be easily reduced. Further, since the pattern width of the auxiliary pattern is large, the process margin can be improved.
Furthermore, since a random fine pattern is not directly formed, optical proximity correction is unnecessary, the size of the hole is not reduced or enlarged on the reticle, the process margin is not impaired, and the manufacturing process is reduced. Simple.
In addition, since the auxiliary pattern and the dense hole pattern can be easily formed, there is room for selecting a resist material and an illumination method applicable to the formation process, and the process margin can be improved. For example, a combination of a halftone phase shift reticle and annular illumination, a combination of a Levenson phase shift reticle and four-hole two-beam illumination, and the like are possible.
[0070]
Fourth embodiment
This embodiment shows a method of forming a semiconductor device having a fine hole pattern randomly arranged between a lower wiring layer and an upper wiring layer having a predetermined pattern. Similar to the above-described embodiment, in this embodiment, a design rule in which the pitch between wiring patterns is 0.40 μm, the line width of the wiring is 0.20 μm, and the hole width is 0.20 μm in units on the wafer is taken as an example.
As shown in FIG. 20, the semiconductor device according to the present embodiment has a lower Cu wiring 11 in advance and silicon oxide (SiO 2).₂There is a base on which an interlayer insulating film 12 made of In the present embodiment, a method of forming a fine random hole pattern such as pattern A in the interlayer insulating film 12 and further forming an upper wiring layer connected to the Cu wiring 11 through these holes in the interlayer insulating film 12 will be described. To do. The wiring groove pattern of the upper wiring layer is a pattern H. In other words, the present embodiment is an example of a method for forming holes and wiring grooves when multilayer wiring is formed by a so-called dual damascene method.
[0071]
Similar to the third embodiment, in this embodiment, in order to form an upper wiring layer having a fine random hole pattern such as pattern A and a wiring groove pattern such as pattern H, pattern A is directly formed. Do not use. Instead, a wiring groove etching mask film is formed on the interlayer insulating layer 12, and a pattern H to be a wiring groove pattern is transferred to the film, and then a hole etching mask is formed on the interlayer insulating layer 12. Then, for example, the auxiliary reticle pattern made of the pattern L is transferred to the film, and finally, the dense hole pattern made of the pattern C is transferred to the interlayer insulating film 12 by using the above etching mask, so that the fine random pattern is transferred. An upper wiring layer connected to the lower wiring layer through the hole pattern and the holes is formed.
Finally, since the upper wiring layer is formed, it is necessary to protect the insulating film between the wiring grooves from being removed when the hole pattern is formed by etching. Therefore, a film for protecting the insulating film between the upper wiring grooves is formed before etching, and is removed after forming a desired hole pattern and upper wiring groove pattern.
[0072]
First, as shown in FIG. 20A, a silicon nitride film (SiN) 13 is formed to a thickness of 50 nm on the interlayer insulating film 12 on the lower wiring layer 11 by a CVD method. The silicon nitride film 13 is used as an etching mask for forming an upper wiring groove.
Next, as shown in FIG. 20B, a resist 14 for transferring the wiring groove pattern H is applied on the silicon nitride film 13. As the resist 14, a resist that is sensitive to the wavelength of a KrF excimer laser used for exposure is applied.
In FIG. 20B, the groove pattern having a cross section along the broken line is transferred to the pattern H on the right side. A broken line and an arrow in the cross-sectional view of the semiconductor substrate on the left side of FIG. 20B indicate a region to be exposed on the resist 14 in order to form a wiring groove corresponding to the cross-sectional pattern in the right diagram. In the wiring groove pattern H, the black pattern is a portion for forming a groove.
The cross-sectional view of the semiconductor substrate shown in FIG. 20 corresponds to the cross section taken along the broken line in the pattern diagram on the right side of FIG.
[0073]
Next, as shown in FIG. 21A, the resist 14 is exposed and developed using the wiring groove pattern H as a reticle, and a portion of the resist 14 corresponding to the wiring groove is removed.
Here, a halftone phase shift reticle is used for a reticle that functions as a wiring groove pattern and has a pattern H. Further, exposure is performed using a half annular illumination with NA = 0.60 using an exposure machine using a KrF excimer laser.
[0074]
Next, as shown in FIG. 21B, the silicon nitride film 13 is etched using the resist 14 as an etching mask, and corresponds to the wiring groove pattern in the section along the broken line on the pattern H on the right side of FIG. Then, the silicon nitride film 13 is opened. Then, the resist 14 is removed.
[0075]
Next, as shown in FIG. 22A, an amorphous silicon film 15 is formed on the interlayer insulating film 12 to a thickness of 50 nm by the CVD method so as to cover the etched silicon nitride film 13. The amorphous silicon film 15 is used as an etching mask so as not to form unnecessary holes when the dense hole pattern C is transferred.
[0076]
Next, as shown in FIG. 22B, a resist 16 for transferring the auxiliary pattern L is applied on the amorphous silicon film 15. As the resist 16, a resist that is sensitive to the wavelength of a KrF excimer laser used for exposure is applied.
In FIG. 22B, a slit pattern having a cross section along the broken line is transferred onto the pattern L on the right side. In the cross-sectional view of the semiconductor substrate on the left side of FIG. 22 (b), the broken line and the arrow indicate the portion that should be exposed to the resist 16 according to the pattern L.
[0077]
Next, as shown in FIG. 23A, the resist 16 is exposed and developed using the auxiliary pattern L as a reticle, and an opening is formed in the resist 16 corresponding to the cross-sectional pattern along the broken line on the right pattern L. do.
Here, a normal reticle made of chromium is used as a reticle that functions as an auxiliary pattern and has a pattern L. Further, exposure is performed using normal illumination with NA = 0.60 using an exposure machine using a KrF excimer laser.
[0078]
Next, as shown in FIG. 23B, the amorphous silicon film 15 is etched using the resist 16 as an etching mask, and corresponds to the pattern of the cross section along the broken line on the pattern L on the right side of FIG. Open to the amorphous silicon film 15. Then, the resist 16 is removed.
[0079]
Next, as shown in FIG. 24A, an antireflection film made of an organic material is applied (not shown). Then, a resist 17 for transferring the pattern A is applied. As the resist 17, a resist that is sensitive to the wavelength of a KrF excimer laser used for exposure is applied.
In FIG. 24A, the pattern of the cross section along the broken line is transferred to the pattern A on the right side. In the cross-sectional view of the semiconductor substrate on the left side of FIG.
[0080]
Next, as shown in FIG. 24B, the resist 17 is exposed and developed using the dense hole pattern C as a reticle, and a pattern having a cross section along the broken line is formed on the resist 17.
The holes constituting the pattern C have the same hole width as that of the pattern A with a hole width of 0.20 μm and a hole pitch of 0.40 μm. Such holes form a pattern C by repeating two-dimensionally periodically.
Here, a halftone phase shift reticle is used for a reticle having a dense hole pattern. The exposure is performed using an exposure machine using a Kr-F excimer laser under the 1/2 annular illumination condition of NA = 0.60 so that an unnecessary pattern due to the sub-peak is not transferred.
As described above, in the present invention, the pattern A is not directly used to form a fine random hole pattern such as the pattern A. Instead, after the auxiliary pattern is transferred to the amorphous silicon film 15, the dense hole pattern C is transferred to the interlayer insulating film 12.
As shown in FIG. 24B, since fine holes are densely packed in the pattern C at a fine pitch, more unnecessary openings than holes in the pattern A (portions indicated by arrows and broken lines) are present. Is formed in the resist 17.
[0081]
Next, as shown in FIG. 24C, the interlayer insulating film 12 is etched using the resist 17 and the antireflection film (not shown) as an etching mask to form holes 18 in the interlayer insulating film 12. Then, the resist 17 is removed.
In the step shown in FIG. 24B, unnecessary openings are also formed in the resist 17 at the same time. However, the previously formed amorphous silicon film 15 is etched into the interlayer insulating layer 12 through these unnecessary openings. Blocking and unnecessary holes are not formed in the interlayer insulating layer 12.
[0082]
Next, in FIG. 25A, the resist 17 is removed.
[0083]
Next, as shown in FIG. 25B, a resist 19 is applied. The resist 19 is used to protect the holes 18 when the amorphous silicon film 15 is removed by etching in the next CMP process.
[0084]
Next, as shown in FIG. 25C, CMP is performed to remove the resist 19 and the amorphous silicon film 15. Then, the resist 19 in the hole 18 is also removed.
[0085]
Next, as shown in FIG. 26A, the entire surface of the interlayer insulating film 12 is etched using the silicon nitride film 13 as an etching mask so that the hole 18 can be connected to the underlying Cu wiring 11 and the wiring groove 20 Is formed on the surface of the interlayer insulating film 12.
Here, since the silicon nitride film 13 is formed in advance and the wiring groove pattern of the pattern H is formed on the silicon nitride film 13, the silicon nitride film 13 protects the insulating film between the wiring grooves as an etching mask. Thereby, a desired hole pattern and wiring groove pattern can be formed by the method of the present invention.
[0086]
Next, as shown in FIG. 26B, after forming a liner layer (not shown) in the wiring groove 20 on the surface of the interlayer insulating layer 12, a conductive material 21 made of, for example, Cu is deposited by, for example, a plating method. To do.
[0087]
Next, as shown in FIG. 26C, unnecessary Cu is removed by a CMP method. At this time, unnecessary silicon nitride film 13 is simultaneously removed by CMP.
Here, the upper wiring layer 21 in which the wiring groove pattern is the pattern H, which is connected to the lower Cu wiring layer 11 through the randomly arranged fine holes such as the pattern A, was formed.
[0088]
In the present embodiment, the halftone phase shift reticle and annular illumination are used in the process shown in FIG. 21A, but other combinations, for example, a combination of Levenson phase shift and normal illumination may be used. good. In addition, although the combination of the normal reticle and the normal illumination is used in the process shown in FIG. 23A, a pattern can be formed satisfactorily with the combination of the halftone phase shift reticle and the annular illumination. In the step shown in FIG. 24B, a halftone phase shift reticle and annular illumination are used. However, the present invention is not limited to this, and a good hole pattern can be formed even by a combination of Levenson phase shift and normal illumination. A good hole pattern can also be formed by a combination of normal reticle and four-hole illumination.
Further, when an ArF excimer laser is used, a good hole pattern can be formed even with a combination of a normal reticle and normal illumination in the steps shown in FIGS. 23 (a) and 24 (b).
[0089]
According to the present embodiment, fine holes randomly arranged like the pattern A are formed on the lower wiring layer, and the wiring groove like the pattern H connected to the lower wiring layer through these holes. In order to form an upper wiring layer having a pattern, it is not necessary to use the pattern A directly. Instead, the auxiliary reticle pattern composed of the pattern H and the pattern L, for example, is transferred to form a two-layer etching mask film, and the dense hole pattern composed of the pattern C is formed using the two-layer etching mask. By transferring to the interlayer insulating film 12, a fine random hole pattern and an upper wiring layer connected to the lower wiring layer through these holes are formed.
Thus, even if it is a fine random hole pattern between the multilayer wiring layers, it can be formed, and it is relatively easy to avoid forming such a fine random hole pattern directly. By transferring the auxiliary pattern with a large pattern width that can be easily formed and the regular dense hole pattern that can be formed relatively easily onto the semiconductor substrate in sequence, it is possible to form fine randomly arranged pitches that are difficult to form directly. A small hole pattern can be formed.
Other effects are the same as those of the third embodiment.
[0090]
Although the present invention has been described based on the preferred embodiments, the present invention is not limited to the embodiments described above, and various modifications can be made without departing from the gist of the present invention.
The method for generating auxiliary pattern data described in the first and second embodiments is a specific example, and modifications to these examples are possible.
[0091]
In the third and fourth embodiments, the case of one and two wiring layers has been described as an example. However, the present invention can also be applied to a case of three or more layers.
For example, in an LSI logic device, when the first three of the wiring layers having a five-layer metal structure are configured with a design rule having a pitch of 0.40 μm, the present invention is applied to the first three layers, The multilayer wiring layer can be manufactured by a damascene method.
For example, for simplicity, the first contact hole layer and wiring layer, the second via hole layer and wiring layer, and the third via hole layer and wiring layer have the same pattern. Assume that pattern H is obtained. Then, both the three-layer hole and the wiring layer can be formed by the method of the fourth embodiment. If the above-described pattern L is used as the auxiliary pattern and the above-described pattern C is used as the dense hole pattern, the reticle including the pattern H, the pattern L, and the pattern C is used as the first contact hole layer, the second via hole layer, and the third pattern. Commonly used for the via hole layer. Therefore, even when the present invention is applied to three layers, only one reticle increases.
[0092]
【The invention's effect】
According to the present invention, in order to form a fine hole pattern randomly arranged on the wiring layer, the random fine hole pattern is not directly formed, but an auxiliary pattern having a large pattern width and a regular dense hole pattern are formed. Using this, the auxiliary pattern that can be formed relatively easily and the dense hole pattern that can be formed relatively easily are sequentially transferred onto the semiconductor substrate to obtain a fine hole pattern with a small random pitch that is difficult to form directly. It is done.
To transfer regular dense hole patterns, it is easy to use super-resolution technology, the hole width can be easily reduced, and the pitch can be easily reduced, which makes it easy to pattern random fine holes Can be formed. In addition, since the auxiliary pattern having a large pattern width is transferred, the process margin can be improved.
Further, since a random fine pattern is not directly formed, optical proximity effect correction is not necessary, and therefore the optical proximity effect correction does not reduce or enlarge the size of the hole on the reticle, and the process margin is high. The manufacturing process is simple.
In addition, since the auxiliary pattern and the dense hole pattern can be easily formed, there is room for selecting a resist material and an illumination method applicable to the formation process, and the process margin can be improved.
Therefore, according to the present invention, for example, in a semiconductor device such as a logic device or a device in which logic and a memory such as DRAM are mixedly mounted, randomly arranged contact holes and via holes are formed with a fine pattern pitch and a fine size. The semiconductor device can be easily formed, and further miniaturization and integration of the semiconductor device can be achieved. In addition, it is very useful because it improves the performance and yield of the integrated circuit.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining graphic operations for generating auxiliary pattern data in a method of manufacturing a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a diagram for explaining a graphic operation for generating auxiliary pattern data in the semiconductor device manufacturing method according to the first embodiment of the present invention, following FIG. 1;
FIG. 3 is a diagram for explaining a graphic operation for generating auxiliary pattern data in the method for manufacturing a semiconductor device according to the first embodiment of the present invention, following FIG. 2;
FIG. 4 is a diagram for explaining a graphic operation for generating auxiliary pattern data in the semiconductor device manufacturing method according to the first embodiment of the present invention, following FIG. 3;
FIG. 5 is a diagram for explaining a graphic operation for generating auxiliary pattern data in the semiconductor device manufacturing method according to the first embodiment of the present invention, following FIG. 4;
FIG. 6 is a diagram for explaining a graphic operation for generating auxiliary pattern data in the semiconductor device manufacturing method according to the first embodiment of the present invention, following FIG. 5;
FIG. 7 is a diagram for explaining a graphic operation for generating auxiliary pattern data in the semiconductor device manufacturing method according to the first embodiment of the present invention, following FIG. 6;
FIG. 8 is a diagram for explaining graphic calculation for generating auxiliary pattern data in the method for manufacturing a semiconductor device according to the first embodiment of the present invention, following FIG. 7;
FIG. 9 is a diagram for explaining a graphic operation for generating auxiliary pattern data in the method for manufacturing a semiconductor device according to the first embodiment of the present invention, following FIG. 8;
FIG. 10 is a diagram for explaining a graphic operation for generating auxiliary pattern data in the semiconductor device manufacturing method according to the second embodiment of the present invention;
FIG. 11 is a diagram for explaining a graphic operation for generating auxiliary pattern data in the method for manufacturing a semiconductor device according to the second embodiment of the present invention, following FIG. 10;
FIG. 12 is a diagram for explaining a graphic operation for generating auxiliary pattern data in the method for manufacturing a semiconductor device according to the second embodiment of the present invention, following FIG. 11;
FIG. 13 is a diagram for explaining a graphic operation for generating auxiliary pattern data in the semiconductor device manufacturing method according to the second embodiment of the present invention, following FIG. 12;
FIG. 14 is a diagram for explaining graphic calculation for generating auxiliary pattern data in the method for manufacturing a semiconductor device according to the second embodiment of the present invention, following FIG. 13;
FIG. 15 is a diagram for explaining a graphic operation for generating auxiliary pattern data in the method for manufacturing a semiconductor device according to the second embodiment of the present invention, following FIG. 14;
FIG. 16 is a schematic cross-sectional view for explaining the method for manufacturing a semiconductor device according to the third embodiment of the present invention.
FIG. 17 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device according to the third embodiment of the present invention following FIG. 16;
FIG. 18 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device according to the third embodiment of the present invention following FIG. 17;
FIG. 19 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device according to the third embodiment of the present invention following FIG. 18;
FIG. 20 is a schematic cross-sectional view for explaining the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention.
FIG. 21 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention following FIG. 20;
FIG. 22 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention following FIG. 21;
FIG. 23 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention following FIG. 22;
FIG. 24 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention, following FIG. 23;
FIG. 25 is a schematic cross-sectional view for explaining the manufacturing method of the semiconductor device according to the fourth embodiment of the present invention, following FIG. 24;
FIG. 26 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention following FIG. 25;
FIG. 27 is a diagram showing an example of a problem of a method for forming fine hole patterns randomly arranged using the conventional technique, (a) is a hole pattern formed under best focus conditions; Indicates a hole pattern formed under the condition of 0.2 μm defocusing.
FIG. 28 is a diagram showing another example of a problem of a method of forming fine hole patterns randomly arranged using the conventional technique, (a) is a hole pattern formed under the best focus condition; ) Shows a hole pattern formed under the condition of 0.2 μm defocusing.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Lower layer wiring layer, 2 ... Interlayer insulating film, 3 ... Etching mask for holes, 4 ... Resist, 5 ... Resist, 6 ... Tungsten, 11 ... Lower layer wiring layer, 12 ... Interlayer insulating film, 13 ... Etching mask for wiring layers , 14 ... resist, 15 ... hole etching mask, 16 ... resist, 17 ... resist, 18 ... hole, 19 ... resist, 20 ... wiring groove, 21 ... upper wiring layer, d ... hole width, p ... inter-hole pitch.

Claims (13)

  By disposing a plurality of via holes or contact holes (hereinafter simply referred to as holes) in an insulating film on a lower wiring layer in a first direction and a second direction orthogonal to the first direction, a semiconductor Process for manufacturing equipment
  It has
  The manufacturing process of the semiconductor device is as follows:
  An etching mask layer processing step of processing the etching mask film formed on the insulating film into an auxiliary pattern;
  A resist film processing step of processing the resist film formed on the insulating film into a dense hole pattern;
  A hole forming step of forming the plurality of holes by etching the insulating film using the etching mask film of the auxiliary pattern and the resist film of the dense hole pattern as a mask;
  Have
  The dense hole pattern is:
  A portion where the plurality of holes are formed in the design pattern of the plurality of holes is open, the opening portion has the same width as the design width of the hole of the design pattern, and the plurality of opening portions are the The first direction and the second direction are repeatedly arranged at the same pitch as the design pitch of a plurality of holes in the design pattern via a non-opening portion,
  The auxiliary pattern is
  A portion where the plurality of holes are formed in the design pattern is open, and the opening portion is wider than the design width of the hole of the design pattern in the first direction and the second direction, and the design A first pattern having a minimum line width narrower than twice the width;
  A portion where the lower wiring layer is formed is opened in the wiring pattern of the lower wiring layer, and the opening portion is smaller than the design width of the hole of the design pattern in the first direction and the second direction. A second pattern which is wide and has a minimum line width equal to the minimum line width of the opening portion of the first pattern;
  Is generated by performing a logical OR operation between
  A graphic OR operation between the auxiliary pattern and the dense hole pattern results in the design pattern.
  A method for manufacturing a semiconductor device.   A first pattern generating step for generating the first pattern;
  A second pattern generation step of generating the second pattern;
  An auxiliary pattern generation step of generating the auxiliary pattern by performing a graphic OR operation between the first pattern and the second pattern;
  It has
  The first pattern generation step includes
  A first step of preparing the design pattern;
  A second step of inverting an opening portion in which the plurality of holes are formed in the design pattern and a non-opening portion other than the opening portion;
  A third step of performing a graphic OR operation between the pattern generated by the inversion in the second step and the dense hole pattern;
  A fourth step of inverting the opening portion and the non-opening portion for the pattern generated by performing the graphic OR operation in the third step;
  A fifth step of performing a sizing process that doubles the width of the non-opening portion of the pattern generated by the inversion in the fourth step in the first direction and the second direction;
  The minimum line width of the non-opening portion of the pattern generated by performing the sizing process in the fifth step is wider than the design width of the hole in the design pattern in the first direction and the second direction. A sixth step of generating the first pattern by performing a sizing process for reducing a non-opening portion of the pattern generated in the fifth step;
  Including
  The second pattern generation step includes
  Until the minimum line width of the non-opening portion in which the lower wiring layer is formed in the wiring pattern is the same as the minimum line width of the first pattern, the non-opening portion of the wiring pattern is moved in the first direction and the first direction. A seventh step of carrying out a sizing process that extends in the second direction;
  An eighth step of generating the second pattern by inverting the opening portion and the non-opening portion of the pattern generated by performing the sizing process in the seventh step;
  Including
  In the etching mask film processing step, the etching mask film is processed into the auxiliary pattern generated in the auxiliary pattern data generation step.
  A method for manufacturing a semiconductor device according to claim 1.   A first pattern generating step for generating the first pattern;
  A second pattern generation step of generating the second pattern;
  An auxiliary pattern generation step of generating the auxiliary pattern by performing a graphic OR operation between the first pattern and the second pattern;
  It has
  The first pattern generation step includes
  A first step of preparing the design pattern;
  A second step of inverting an opening portion in which the plurality of holes are formed in the design pattern and a non-opening portion other than the opening portion;
  A third step of performing a sizing process that doubles the width of the non-opening portion of the pattern generated by the reversal in the second step in the first direction and the second direction;
  A fourth step of inverting the opening portion and the non-opening portion for the pattern generated by performing the sizing process in the third step;
  In order that the minimum line width of the non-opening portion of the pattern generated by the inversion in the fourth step exceeds the design width of the hole of the design pattern in the first direction and the second direction. A fifth step of generating the first pattern by performing a sizing process for reducing a non-opening portion of the pattern generated in the fourth step;
  The second pattern generation step includes
  Until the minimum line width of the non-opening portion in which the lower wiring layer is formed in the wiring pattern is the same as the minimum line width of the first pattern, the non-opening portion of the wiring pattern is moved in the first direction and the first direction. A sixth step of carrying out a sizing process that spreads in the second direction;
  A seventh step of generating the second pattern by inverting the opening portion and the non-opening portion of the pattern generated by performing the sizing process in the sixth step;
  Including
  In the etching mask film processing step, the etching mask film is processed into the auxiliary pattern generated in the auxiliary pattern data generation step.
  A method for manufacturing a semiconductor device according to claim 1.   A step of burying a conductive material in the hole formed in the insulating film and connecting to the lower wiring layer
  Further having
  A method for manufacturing a semiconductor device according to claim 1.   The auxiliary pattern is a slit pattern.
  A method for manufacturing a semiconductor device according to claim 1.   The etching mask film is an amorphous silicon film,
  A method for manufacturing a semiconductor device according to claim 1.   A plurality of via holes or contact holes (hereinafter simply referred to as holes) are randomly arranged in the insulating film on the lower wiring layer in the first direction and the second direction orthogonal to the first direction, and then in the holes. A step of manufacturing a semiconductor device by forming an upper wiring layer connected to the lower wiring layer
  It has
  The manufacturing process of the semiconductor device is as follows:
  A first etching mask film processing step of processing the first etching mask film formed on the insulating film into a wiring groove pattern of the upper wiring layer;
  A second etching mask film processing step of processing the second etching mask film formed on the insulating film into an auxiliary pattern;
  A resist film processing step of processing the resist film formed on the insulating film into a dense hole pattern;
  Using the second etching mask film of the auxiliary pattern and the resist film of the dense hole pattern as a mask, the insulating film is etched and the second etching mask film and the resist film are removed, and then the wiring groove Forming a hole and a wiring groove of the upper wiring layer in the insulating film by etching the insulating film using the first etching mask film of the pattern as a mask;
  Have
  The dense hole pattern is:
  A portion where the plurality of holes are formed in the design pattern of the plurality of holes is open, the opening portion has the same width as the design width of the hole of the design pattern, and the plurality of opening portions are the The first direction and the second direction are repeatedly arranged at the same pitch as the design pitch of a plurality of holes in the design pattern via a non-opening portion,
  The auxiliary pattern is
  A portion where the plurality of holes are formed in the design pattern is open, and the opening portion is wider than the design width of the hole of the design pattern in the first direction and the second direction, and the design A first pattern having a minimum line width narrower than twice the width;
  A portion where the lower wiring layer is formed is opened in the wiring pattern of the lower wiring layer, and the opening portion is smaller than the design width of the hole of the design pattern in the first direction and the second direction. A second pattern which is wide and has a minimum line width equal to the minimum line width of the opening portion of the first pattern;
  Is generated by performing a logical OR operation between
  A graphic OR operation between the auxiliary pattern and the dense hole pattern results in the design pattern.
  A method for manufacturing a semiconductor device.   A first pattern generating step for generating the first pattern;
  A second pattern generation step of generating the second pattern;
  An auxiliary pattern generation step of generating the auxiliary pattern by performing a graphic OR operation between the first pattern and the second pattern;
  It has
  The first pattern generation step includes
  A first step of preparing the design pattern;
  A second step of inverting an opening portion in which the plurality of holes are formed in the design pattern and a non-opening portion other than the opening portion;
  A third step of performing a graphic OR operation between the pattern generated by the inversion in the second step and the dense hole pattern;
  A fourth step of inverting the opening portion and the non-opening portion for the pattern generated by performing the graphic OR operation in the third step;
  A fifth step of performing a sizing process that doubles the width of the non-opening portion of the pattern generated by the inversion in the fourth step in the first direction and the second direction;
  The minimum line width of the non-opening portion of the pattern generated by performing the sizing process in the fifth step is wider than the design width of the hole in the design pattern in the first direction and the second direction. A sixth step of generating the first pattern by performing a sizing process for reducing a non-opening portion of the pattern generated in the fifth step;
  Including
  The second pattern generation step includes
  Until the minimum line width of the non-opening portion in which the lower wiring layer is formed in the wiring pattern is the same as the minimum line width of the first pattern, the non-opening portion of the wiring pattern is moved in the first direction and the first direction. A seventh step of carrying out a sizing process that extends in the second direction;
  An eighth step of generating the second pattern by inverting the opening portion and the non-opening portion of the pattern generated by performing the sizing process in the seventh step;
  Including
  In the etching mask film processing step, the etching mask film is processed into the auxiliary pattern generated in the auxiliary pattern data generation step.
  A method for manufacturing a semiconductor device according to claim 7.   A first pattern generating step for generating the first pattern;
  A second pattern generation step of generating the second pattern;
  An auxiliary pattern generation step of generating the auxiliary pattern by performing a graphic OR operation between the first pattern and the second pattern;
  It has
  A first step of preparing the design pattern;
  A second step of inverting an opening portion in which the plurality of holes are formed in the design pattern and a non-opening portion other than the opening portion;
  A third step of performing a sizing process that doubles the width of the non-opening portion of the pattern generated by the reversal in the second step in the first direction and the second direction;
  A fourth step of inverting the opening portion and the non-opening portion for the pattern generated by performing the sizing process in the third step;
  In order that the minimum line width of the non-opening portion of the pattern generated by the inversion in the fourth step exceeds the design width of the hole of the design pattern in the first direction and the second direction. A fifth step of generating the first pattern by performing a sizing process for reducing a non-opening portion of the pattern generated in the fourth step;
  The second pattern generation step includes
  Until the minimum line width of the non-opening portion in which the lower wiring layer is formed in the wiring pattern is the same as the minimum line width of the first pattern, the non-opening portion of the wiring pattern is moved in the first direction and the first direction. A sixth step of carrying out a sizing process that spreads in the second direction;
  A seventh step of generating the second pattern by inverting the opening portion and the non-opening portion of the pattern generated by performing the sizing process in the sixth step;
  Including
  In the etching mask film processing step, the etching mask film is processed into the auxiliary pattern generated in the auxiliary pattern data generation step.
  A method for manufacturing a semiconductor device according to claim 7.   Removing the first etching mask film after the hole forming step;
  Having
  A method for manufacturing a semiconductor device according to claim 7.   A step of forming the upper wiring layer by embedding a conductive material in the wiring groove and the hole and then planarizing the conductive material.
  Having
  A method for manufacturing a semiconductor device according to claim 10.   The auxiliary pattern is a slit pattern.
  A method for manufacturing a semiconductor device according to claim 11.   The first etching mask film is a silicon nitride film;
  The second etching mask film is an amorphous silicon film;
  A method for manufacturing a semiconductor device according to claim 7.

Images