CN215418179U - Semiconductor structure - Google Patents

Abstract

The utility model discloses a semiconductor structure, which comprises a plurality of wiring patterns arranged on a substrate, and a merged pattern arranged between the adjacent wiring patterns, wherein the merged pattern comprises a first outer line section, a middle line section and a second outer line section which are sequentially arranged and connected with each other along a first direction, and the end surface of the first outer line section, the end surface of the middle line section and the end surface of the second outer line section are staggered with each other along the first direction.

Description

Semiconductor structure

Technical Field

The utility model relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure adopting a double patterning technology.

Background

In the fabrication of integrated circuits, photolithography (photolithography) is an indispensable technology, and at the technology node of 32nm and below, the resolution index required by photolithography is beyond the limit capability of the existing photolithography tools. Therefore, Double Patterning Technology (DPT), which can increase the minimum pattern distance on the existing photolithography tool, has become a solution for 32nm to 22nm line width technology. The DPT technology is to decompose and split a set of high-density circuit pattern into two or more sets of circuit patterns with lower density, then respectively manufacture photomasks, successively complete corresponding exposure and etching processes, and finally combine and form the initially required high-density pattern.

However, since the DPT technique has to go through multiple exposure steps, overlay control and alignment have been a concern of the DPT technique, and the problem of overlay control and alignment is more prominent when the high-density circuit pattern is decomposed into two or more sets of circuit patterns with lower density. When the DPT technology is overlapped incorrectly or aligned inaccurately, the circuit patterns are broken or connected, which causes serious open circuit or short circuit problems.

Therefore, there is still a need for a method of fabricating a semiconductor layout and a semiconductor structure fabricated using the same that overcomes the above-mentioned problems.

SUMMERY OF THE UTILITY MODEL

The utility model provides a semiconductor structure, a manufacturing method thereof and a method for manufacturing a semiconductor layout, which aim to solve the problems of disconnection, connection and the like in the conventional double patterning technology.

According to an embodiment of the present invention, there is provided a semiconductor structure including a substrate, a plurality of wiring patterns provided on the substrate, and a merged pattern provided between the adjacent wiring patterns, wherein the merged pattern includes a first outer line segment, a middle line segment, and a second outer line segment that are sequentially arranged and connected to each other along a first direction, and an end surface of the first outer line segment, an end surface of the middle line segment, and an end surface of the second outer line segment are offset from each other along the first direction.

According to an embodiment of the present invention, a method for fabricating a semiconductor structure is provided, which includes providing a layout, wherein the layout includes a plurality of connection patterns and at least one pattern to be cut; decomposing the layout into a plurality of first connecting line patterns and a plurality of second connecting line patterns which are alternately arranged, wherein the pattern to be cut is arranged between the two adjacent first connecting line patterns and second connecting line patterns; cutting the pattern to be cut into a cut portion and a corresponding portion; forming a layout composed of the plurality of first wiring patterns and the cut portions on a first photomask; forming a layout formed by the plurality of second wiring patterns and the corresponding parts on a second photomask; providing a substrate on which a target layer is disposed; and transferring the layout of the first photomask and the layout of the second photomask into the target layer to form a plurality of connection patterns and a merged pattern, wherein the outline of the merged pattern is defined by the cut portion and the corresponding portion, the merged pattern comprises two oppositely-arranged end faces, and each end face comprises a recessed area and a protruding area.

According to an embodiment of the present invention, a method for fabricating a semiconductor layout is provided, which includes providing a layout, wherein the layout includes a plurality of wiring patterns and at least one pattern to be cut; decomposing the layout into a plurality of first connecting line patterns and a plurality of second connecting line patterns which are alternately arranged, wherein the pattern to be cut is arranged between the two adjacent first connecting line patterns and second connecting line patterns; cutting the pattern to be cut into an original cut portion and an original counterpart, wherein a boundary line is included between the original cut portion and the original counterpart; moving the boundary line of the original cut portion to form a modified cut portion, wherein the modified cut portion has an area larger than the area of the original cut portion; and forming the plurality of first wiring patterns and the corrected cutting portions on a photomask.

According to the method for fabricating a semiconductor layout provided by an embodiment of the present invention, a pattern to be cut with a large width is cut into an original cut portion and an original corresponding portion, and an intersection line between the original cut portion and the original corresponding portion is moved to generate a modified cut portion and a modified corresponding portion with a large area, then the modified cut portion and the modified corresponding portion are respectively formed on two photomasks, and the layout of the two photomasks is transferred into a target layer, so that a merged pattern of a semiconductor structure is formed, which is defined by the cut portion and the corresponding portion, and it can be ensured that no disconnection occurs between two outer line segments of the merged pattern corresponding to the cut portion and the corresponding portion, so as to improve the reliability of the formed semiconductor structure. The semiconductor structure, the manufacturing method thereof and the method for manufacturing the semiconductor layout can effectively and reliably manufacture circuit patterns with high density and large size difference of partial patterns on the premise of not increasing the process complexity.

Drawings

Fig. 1 is a schematic plan view of a layout for fabricating a semiconductor structure according to an embodiment of the present invention.

FIG. 2 is a schematic plan view of an exploded layout for fabricating a semiconductor structure according to an embodiment of the present invention.

Fig. 3 is a schematic plan view of another exploded layout for fabricating a semiconductor structure according to an embodiment of the present invention.

Fig. 4 to 8 are schematic cross-sectional views of stages of a method for fabricating a semiconductor structure according to an embodiment of the utility model.

Fig. 9 is a schematic plan view of a semiconductor structure according to an embodiment of the utility model.

Fig. 10 is a schematic plan view of a semiconductor structure according to another embodiment of the utility model.

Wherein the reference numerals are as follows:

100 semiconductor structure

101 substrate

103 diffusion barrier layer

105 target layer

106 patterned target layer

107 protective layer

109 lower mask layer

110 mask pattern

111 upper mask layer

112 mask pattern

113 photoresist bottom layer

114 partial graphic

115 photo resist intermediate layer

116 merging patterns

117 bottom antireflective coating

119 patterned photoresist layer

121 photoresist bottom layer

123 intermediate layer of photoresist

125 patterned photoresist layer

126 partial graphic

130 wiring pattern

131 first wiring pattern

132 second wiring pattern

133 merging patterns

133-1 first outside line segment

133-2 second outside line segment

133-3 middle line segment

133E end face

133-1E end face

133-2E end face

133-3E end face

135 contact structure

137 space of the motor

200 layout

200-1 decomposition layout

200-2 decomposition layout

210 wiring pattern

211 first connection line pattern

212 second wiring pattern

213 pattern to be cut

213-1 original cutting part

213-1A end face

213-2 original counterpart

213-2A end face

213S bevel edge

213L boundary line

214-1 modified cutting section

214-1A end face

214-2 modified counterpart

214-2A end face

P1, P2 and P3 spaces

Detailed Description

For a better understanding of the present invention, preferred embodiments will be described in detail below. Preferred embodiments of the present invention are illustrated by reference numerals in the figures. Furthermore, technical features in different embodiments described below may be replaced with, recombined with, or mixed with each other to constitute another embodiment without departing from the spirit of the present invention.

Referring to fig. 1, fig. 1 is a schematic plan view of a layout 200 for fabricating a semiconductor structure according to an embodiment of the utility model. As shown in fig. 1, the layout 200 may be a layout of a metal interconnection layer used for manufacturing a semiconductor device (e.g., a memory device such as a dynamic random access memory or a static random access memory), such as a layout of a zeroth metal layer (M0) and a first metal layer (M1), but is not limited thereto. The layout 200 includes a plurality of link patterns 210 and at least one pattern 213 to be cut, the plurality of link patterns 210 may be decomposed into a plurality of first link patterns 211 and a plurality of second link patterns 212 which are arranged alternately, and the pattern 213 to be cut is disposed between two adjacent first link patterns 211 and second link patterns 212. The plurality of first link patterns 211 and the plurality of second link patterns 212 are alternately arranged along a first direction (e.g., x-direction shown in fig. 1) and each extend along a second direction (e.g., y-direction shown in fig. 1) perpendicular to the first direction, along which the pattern to be cut 213 also extends. It is to be noted that some of the first wiring pattern 211 and the second wiring pattern 212 may not extend along the second direction, but the first wiring pattern 211 and the second wiring pattern 212 may each be regarded as extending substantially along the second direction as a whole.

According to the embodiment of the present invention, the minimum pattern distance of the layout 200 violates the predetermined rule of the photolithography process, that is, the pitch P1 between the adjacent first link pattern 211 and the second link pattern 212, and the pitch P2 between the adjacent first link pattern 211 and the pattern 213 to be cut, and the pitch P3 between the adjacent second link pattern 212 and the pattern 213 to be cut violates the predetermined rule of the photolithography process. When the layout 200 violates the predetermined rule, the corresponding pattern formed on the photomask may generate a significant light diffraction phenomenon during the photolithography process, and thus the pattern may not be faithfully transferred to the semiconductor wafer. In one embodiment, the minimum pattern distance of the layout 200 is, for example, 52nm, that is, the pitch P1 between the first link pattern 211 and the second link pattern 212 may be 52nm, and the pitch P2 between the pattern 213 to be cut and the adjacent first link pattern 211, and the pitch P3 between the pattern 213 to be cut and the adjacent second link pattern 212 may also be 52 nm. In addition, the width of the pattern to be cut 213 is greater than the width of each of the first link patterns 211 and the second link patterns 212 along the first direction. In an embodiment, the width of the pattern to be cut 213 may be 2 to 3 times the width of the first link pattern 211 and the width of the second link pattern 212.

According to an embodiment of the present invention, the pattern 213 to be cut may be cut into the original cut portion 213-1 and the original corresponding portion 213-2, and the original cut portion 213-1 and the original corresponding portion 213-2 include a boundary line 213L therebetween, wherein the original cut portion 213-1 is adjacent to the second wiring pattern 212, and the original corresponding portion 213-2 is adjacent to the first wiring pattern 211. Further, as shown in fig. 1, at least one top corner of the pattern 213 to be cut is truncated (or regarded as being truncated) so that the top corner becomes the oblique side 213S. The pattern 213 to be cut having the oblique sides 213S may increase the distance between the corners of the pattern 213 to be cut and the adjacent first connection line pattern 211, thereby reducing the possibility of interconnection between the pattern formed by the pattern 213 to be cut and the adjacent connection line pattern after the photolithography process, and preventing or reducing the occurrence of short circuits between the formed circuit patterns. In one embodiment, all four corners of the pattern 213 to be cut may be cut to generate four oblique edges, so that the distance between the four corners of the pattern 213 to be cut and the adjacent first connection line pattern 211 and the adjacent second connection line pattern 212 is increased, and it is further ensured that no short circuit occurs between the formed circuit patterns.

Next, the first wiring pattern 211, the second wiring pattern 212, the original cut portion 213-1, and the original counterpart 213-2 described above may be decomposed (deconstructed) into different layouts, resulting in the layouts shown in fig. 2 and 3. In addition, the layouts shown in FIGS. 2 and 3 are only exemplary, and the patterns in these layouts may be further modified (e.g., optical proximity correction) such that the pattern profiles before and after the modification are different from each other.

Referring to fig. 2, fig. 2 is a schematic plan view of an exploded layout 200-1 for fabricating a semiconductor structure according to an embodiment of the utility model. As shown in FIG. 2, the exploded layout 200-1 includes a plurality of first link patterns 211 and modified cut portions 214-1, wherein the modified cut portions 214-1 are formed by moving the boundary line 213L of the original cut portion 213-1, an end surface 213-1A of the original cut portion 213-1 away from the boundary line 213L is fixed and does not move, and the boundary line 213L is moved in a direction closer to the original corresponding portion 213-2 along the first direction to produce the end surface 214-1A of the modified cut portion 214-1, and the area of the modified cut portion 214-1 is formed to be larger than the area of the original cut portion 213-1. In an embodiment, the ratio between the area of the modified cut portion 214-1 and the area of the original cut portion 213-1 may be 1.05 to 1.50.

Referring to fig. 3, fig. 3 is a schematic plan view of another exploded layout 200-2 for fabricating a semiconductor structure according to an embodiment of the utility model. As shown in FIG. 3, the decomposed layout 200-2 includes a plurality of second connection line patterns 212 and modified corresponding portions 214-2, wherein the modified corresponding portions 214-2 are formed by moving the boundary lines 213L of the original corresponding portions 213-2, an end surface 213-2A of the original corresponding portions 213-2 away from the boundary lines 213L is fixed and does not move, and the boundary lines 213L are moved in a direction closer to the original cut portions 213-1 along the first direction to generate the end surfaces 214-2A of the modified corresponding portions 214-2, and the area of the formed modified corresponding portions 214-2 is larger than the area of the original corresponding portions 213-2. In one embodiment, the ratio between the area of the modified counterpart 214-2 and the area of the original counterpart 213-2 may be 1.05 to 1.50.

According to the embodiment of the present invention, it is not limited to moving the boundary line 213L of the original cutting portion 213-1 in FIG. 2 and moving the boundary line 213L of the original corresponding portion 213-2 in FIG. 3, but only the boundary line 213L of the original cutting portion 213-1 may be moved without moving the boundary line 213L of the original corresponding portion 213-2 according to the actual requirement; or only the boundary line 213L of the original corresponding portion 213-2 is moved, and the boundary line 213L of the original cutting portion 213-1 is not moved.

According to an embodiment of the present invention, a decomposed layout 200-1 including a plurality of first wiring patterns 211 and modified cut portions 214-1 is formed on at least one photomask, and another decomposed layout 200-2 including a plurality of second wiring patterns 212 and modified corresponding portions 214-2 is formed on another at least one photomask. In addition, the decomposed layout 200-1 and the other decomposed layout 200-2 can be further modified (e.g., optical proximity correction) according to actual requirements before being fabricated on different photomasks.

Next, referring to fig. 4 to 8, fig. 4 to 8 are schematic cross-sectional views of various stages of a method for manufacturing a semiconductor structure according to an embodiment of the utility model. First, as shown in fig. 4, a substrate 101 is provided, and the substrate 101 may be a silicon substrate, a silicon-on-insulator (SOI) substrate, or other semiconductor substrate. A diffusion barrier layer 103, a target layer 105, a passivation layer 107, a lower mask layer 109, an upper mask layer 111, a photoresist bottom layer 113, a photoresist intermediate layer 115, and a bottom anti-reflective coating (BARC) 117, and a patterned photoresist layer 119 are sequentially deposited on the substrate 101. In one embodiment, the material of the diffusion barrier layer 103 is, for example, titanium nitride (TiN), tantalum nitride (TaN), or other suitable diffusion barrier material, which can be used to prevent metal atoms in the upper layer from diffusing into the lower layer. The target layer 105 is, for example, a conductive layer, which may be a metal layer, a metal alloy layer, or a combination thereof, such as a tungsten layer, and the target layer 105 is subsequently patterned by a photolithography process to form a conductive line pattern. The protection layer 107, which may be a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, or combinations thereof, covers the target layer 105 to protect the underlying target layer 105 during the photolithography process. The material of the lower mask layer 109 is, for example, amorphous silicon, and the patterns of the decomposition layout 200-1 and the decomposition layout 200-2 are subsequently transferred to the lower mask layer 109 through a photolithography process. The material of the upper mask layer 111 is, for example, silicon oxide, and the pattern of one of the decomposition layout 200-1 and the decomposition layout 200-2 is subsequently transferred to the upper mask layer 111 through a photolithography process. The material and etch rate of the lower mask layer 109 will preferably be different from the material and etch rate of the upper mask layer 111. The photoresist bottom layer 113 may be a spin-on carbon (SOC) layer that provides a relatively flat surface for photoresist deposited or coated thereon to facilitate subsequent exposure and development processes. The intermediate layer 115 may be silicon oxynitride, and a bottom anti-reflective coating (BARC) 117 is disposed below the patterned photoresist layer 119 to reduce light reflected between the photoresist and the substrate 101 during the exposure process.

According to an embodiment of the present invention, the pattern of one of the decomposition layout 200-1 and the decomposition layout 200-2, such as the decomposition layout 200-1 formed on a photomask, is transferred to the photoresist layer through an exposure and development process to form the patterned photoresist layer 119 shown in FIG. 4. In one embodiment, a positive photoresist may be used, and the pattern of the patterned photoresist layer 119 formed corresponds to the pattern of the decomposed layout 200-1 on the photomask. However, a negative photoresist may be used according to actual needs. Then, referring to fig. 4 and 5, a pattern of the patterned photoresist layer 119 is transferred to the lower upper mask layer 111 using an etching process to form a mask pattern 112, as shown in fig. 5. In one embodiment, the mask pattern 112 is also patterned as the decomposed layout 200-1 on the photomask, including a plurality of first line patterns 211 and modified cut portions 214-1.

Next, as shown in fig. 6, a photoresist bottom layer 121 and a photoresist intermediate layer 123 are sequentially deposited on the mask pattern 112 and the lower mask layer 109, and a patterned photoresist layer 125 is formed, wherein the photoresist bottom layer 121 may be an Organic Dielectric Layer (ODL) 121 to provide a flat surface for depositing or coating a photoresist thereon, and the photoresist intermediate layer 123 may be a spin-on hard-mask and anti-reflection layer (SHB) containing silicon. According to an embodiment of the present invention, the pattern of the other of the decomposition layout 200-1 and the decomposition layout 200-2, e.g., the decomposition layout 200-2 formed on another photomask, is transferred to the photoresist layer via an exposure and development process to form the patterned photoresist layer 125 shown in FIG. 6. In one embodiment, a positive photoresist may be used, and the pattern of the patterned photoresist layer 125 is formed to correspond to the pattern of the decomposed layout 200-2 on another photomask, including the plurality of second line patterns 212 and the modified corresponding portions 214-2.

According to an embodiment of the present invention, the portion of the pattern 114 in the mask pattern 112 corresponds to the modified cut portion 214-1 in the decomposed layout 200-1, and the portion of the pattern 126 in the patterned photoresist layer 125 corresponds to the modified cut portion 214-2 in the decomposed layout 200-2. Since the side of the partial pattern 114 in the mask pattern 112 and the side of the partial pattern 126 in the photoresist layer 125 may partially overlap in a direction perpendicular to the substrate 101, when the partial pattern 114 and the partial pattern 126 are subsequently transferred to the underlying lower mask layer 109 by an etching process, the corresponding pattern formed in the lower mask layer 109 may be regarded as a pattern in which the partial pattern 114 and the partial pattern 126 are merged with each other.

Then, referring to fig. 6 and 7, the pattern of the patterned photoresist layer 125 is transferred to the lower mask layer 109 below together with the pattern of the mask pattern 112 by using an etching process to form another mask pattern 110, as shown in fig. 7. The pattern of the mask pattern 110 may correspond to a pattern combined by the decomposed layout 200-1 on one photomask and the decomposed layout 200-2 on another photomask, and the combined pattern includes a pattern combined by the plurality of first link patterns 211, the plurality of second link patterns 212, and the modified cut portion 214-1 and the modified corresponding portion 214-2. As shown in fig. 7, the merged pattern 116 in the mask pattern 110 is a pattern combined by the corrected cut portion 214-1 and the corrected corresponding portion 214-2. Ideally, the top profile of the merged pattern 116 would be similar to the profile of the pattern 213 to be cut in fig. 1, however, in practice, the top profile of the merged pattern 116 would be different from the profile of the pattern 213 to be cut in fig. 1.

Referring to fig. 7 and 8, the pattern of the mask pattern 110 is transferred to the target layer 105 by an etching process to form a patterned target layer 106 on the substrate 101, such as the semiconductor structure 100 shown in fig. 8, in an embodiment, a portion of the diffusion barrier layer 103 underlying the patterned target layer 106 is also patterned together. According to an embodiment of the present invention, the patterned target layer 106 includes a plurality of connection patterns 130 and a merged pattern 133. Ideally, the top profile of the merged pattern 133 would be similar to the profile of the pattern 213 to be cut in fig. 1, however, in practice, the top profile of the merged pattern 133 would be different from the profile of the pattern 213 to be cut in fig. 1.

Referring to fig. 9, which is a schematic plan view of a semiconductor structure according to an embodiment of the present invention, as shown in fig. 9, the semiconductor structure 100 may be a top view of fig. 8, which includes a plurality of connection patterns 130 and a merged pattern 133 disposed on a substrate 101, and the patterned target layer 106 of fig. 8 includes the plurality of connection patterns 130 and the merged pattern 133 shown in fig. 9. In an embodiment, the semiconductor structure 100 may be a partial structure of a semiconductor memory device, the substrate 101 includes a plurality of active regions (not shown), and the plurality of wiring patterns 130 are a plurality of conductive line patterns, each of which is electrically connected to each of the active regions. The plurality of wiring patterns 130 include a plurality of first wiring patterns 131 and a plurality of second wiring patterns 132, and the plurality of first wiring patterns 131 and the plurality of second wiring patterns 132 are alternately arranged along a first direction (e.g., the x direction shown in fig. 9). The merged pattern 133 is disposed between the adjacent plurality of link patterns 130, that is, the merged pattern 133 is disposed between the adjacent first link pattern 131 and second link pattern 132. Further, each of the wiring patterns 130 and the merged pattern 133 extends along a second direction (e.g., y-direction shown in fig. 9) perpendicular to the first direction.

According to an embodiment of the present invention, the outline of the merged pattern 133 is defined by the cut part 213-1 and the corresponding part 213-2 of fig. 1, the merged pattern 133 includes a first outer line segment 133-1, a middle line segment 133-3, and a second outer line segment 133-2 that are sequentially arranged and connected to each other along the first direction, a long axis of the first outer line segment 133-1, a long axis of the middle line segment 133-3, and a long axis of the second outer line segment 133-2 are parallel to each other, and the first outer line segment 133-1 is disposed adjacent to the second line pattern 132, and the second outer line segment 133-2 is disposed adjacent to the first line pattern 131. In one embodiment, the length of the first outer line segment 133-1 is not equal to the length of the second outer line segment 133-2, and the width of the merging pattern 133 is greater than the width of each first line pattern 131 and the width of each second line pattern 132. In addition, the end 133-1E of the first outside line segment 133-1, the end 133-3E of the middle line segment 133-3, and the end 133-2E of the second outside line segment 133-2 are offset from each other along the first direction such that the one end 133E of the merged pattern 133 includes a recessed region corresponding to the end 133-3E of the middle line segment 133-3 and a protruding region corresponding to the end 133-1E of the first outside line segment 133-1 and the end 133-2E of the second outside line segment 133-2. The merged pattern 133 further includes another end surface disposed opposite to the end surface 133E in the second direction, and similarly, the other end surface also includes a recessed region and a protruding region similar to the end surface 133. Further, the recessed regions and the protruding regions of both end surfaces of the merged pattern 133 include curved surfaces, respectively.

In addition, the semiconductor structure 100 further includes a contact structure 135 disposed on the patterned target layer 106, wherein the contact structure 135 overlaps the merged pattern 133 in a third direction (e.g., a z-direction shown in fig. 9), and the third direction is perpendicular to the surface of the substrate 101. The contact structure 135 may be a conductive structure that may be electrically connected to other structures above it, such as an interconnect structure, in addition to the merged pattern 133 below it. Since the width of the merged pattern 133 carrying the contact structure 135 is greater than the width of each of the first link patterns 131 and the width of each of the second link patterns 132, it is cut into two parts, i.e., the original corresponding part and the original cut part, at the time of the decomposed layout, and the two parts are formed on different photomasks, respectively. When the photolithography process is performed, if an overlay error or an alignment inaccuracy occurs, the merged patterns for carrying the contact structures may be separated from each other, resulting in an open circuit or a short circuit of the formed circuit.

Fig. 10 is a schematic plan view of a semiconductor structure according to another embodiment of the present invention. The structure of fig. 10 is similar to the structure shown in fig. 9, with the main difference being that the merged pattern 133 of fig. 10 includes at least one void, for example, two voids 137. The gap 137 may be located between the first outboard line segment 133-1 and the second outboard line segment 133-2 such that the intermediate line segment 133-3 located between the first outboard line segment 133-1 and the second outboard line segment 133-2 is non-continuously distributed in the second direction (e.g., the y-direction shown in fig. 9). Since there has been a correction of the layout pattern corresponding to the first and second outer line segments 133-1 and 133-2 (increasing the area of the layout pattern) in the exploded layouts 200-1 and 200-2 in fig. 2 and 3, the first and second outer line segments 133-1 and 133-2 are not completely separated by the gap 137 even if an overlay error or an alignment inaccuracy occurs in the photolithography process. In addition, since the contact structure 135 is formed later than the merged pattern 133, when at least a portion of the contact structure 135 overlaps the void 137, a portion of the contact structure 135 may also be filled into the void 137 to increase a contact area between the contact structure 135 and the merged pattern 133.

According to an embodiment of the present invention, when fabricating the semiconductor layout, the boundary line 213L between the original counterpart 213-2 and the original cut portion 213-1 of the pattern to be cut 213 is moved such that the area of the modified counterpart 214-2 is larger than the area of the original counterpart 213-2, the area of the modified cut portion 214-1 is also larger than the area of the original cut portion 213-1, and there is an intermediate overlap region between the modified counterpart 214-2 and the modified cut portion 214-1, so that when fabricating the merged pattern 133 using the modified counterpart 214-2 and the modified cut portion 214-1, reliability of the merged pattern 133 to carry the contact structure 135 can be ensured. Therefore, according to the method for manufacturing the semiconductor layout and the method for manufacturing the semiconductor structure, the manufactured semiconductor structure can improve the reliability of the electrical connection between the formed circuit conducting wire and the contact pad under the condition that the distance between the adjacent connecting line patterns and the pattern to be cut violate the preset rule of the photoetching process, and no additional photoetching process step is needed.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A semiconductor structure, comprising:

a substrate;

a plurality of wiring patterns disposed on the substrate; and

and a merged pattern disposed between the adjacent connection line patterns, wherein the merged pattern includes a first outer line segment, a middle line segment, and a second outer line segment that are sequentially arranged and connected to each other along a first direction, and end surfaces of the first outer line segment, the middle line segment, and the second outer line segment are offset from each other along the first direction.

2. The semiconductor structure of claim 1, wherein the semiconductor structure is part of a semiconductor memory device, wherein:

the substrate comprises a plurality of active regions; and

the plurality of wiring patterns are a plurality of wiring patterns, and the wiring patterns are respectively electrically connected with the active regions.

3. The semiconductor structure of claim 1 wherein said merged pattern has at least one void, said void being located between said first outside line segment and said second outside line segment.

4. The semiconductor structure of claim 3, further comprising a contact structure partially overlapping said void.

5. The semiconductor structure of claim 1, wherein the merged pattern comprises two end faces oppositely disposed in a second direction, each end face comprising a recessed region and a protruding region, wherein the second direction is perpendicular to the first direction.

6. The semiconductor structure of claim 4, wherein the recessed region and the protruding region each comprise a curved surface.

7. The semiconductor structure of claim 1, wherein said wiring patterns comprise a plurality of first wiring patterns and a plurality of second wiring patterns, wherein said plurality of first wiring patterns and said plurality of second wiring patterns are disposed on said substrate and are alternately arranged along said first direction.

8. The semiconductor structure of claim 7,

the first outer line segment is arranged adjacent to the second line pattern; and

the second outer line segment is arranged adjacent to the first connection line pattern, wherein the length of the first outer line segment is not equal to the length of the second outer line segment.

9. The semiconductor structure of claim 7, wherein a width of said merged pattern is greater than a width of each of said first wiring patterns and each of said second wiring patterns.

10. The semiconductor structure of claim 9, further comprising a contact structure overlapping the merged pattern in a third direction, wherein the third direction is perpendicular to the surface of the substrate.

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