KR100516748B1 - Micro pattern formation method of semiconductor device - Google Patents
Micro pattern formation method of semiconductor device Download PDFInfo
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- KR100516748B1 KR100516748B1 KR10-1998-0058639A KR19980058639A KR100516748B1 KR 100516748 B1 KR100516748 B1 KR 100516748B1 KR 19980058639 A KR19980058639 A KR 19980058639A KR 100516748 B1 KR100516748 B1 KR 100516748B1
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- 238000000034 method Methods 0.000 title claims abstract description 46
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 230000007261 regionalization Effects 0.000 title description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 38
- 229910052751 metal Inorganic materials 0.000 claims abstract description 38
- 239000002184 metal Substances 0.000 claims abstract description 38
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 20
- 239000010410 layer Substances 0.000 claims description 29
- 239000011229 interlayer Substances 0.000 claims description 9
- 230000004888 barrier function Effects 0.000 claims description 8
- 238000009792 diffusion process Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 5
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 238000000206 photolithography Methods 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 230000010354 integration Effects 0.000 abstract description 3
- 239000006117 anti-reflective coating Substances 0.000 abstract 1
- 238000002310 reflectometry Methods 0.000 abstract 1
- 239000010408 film Substances 0.000 description 120
- 229910052814 silicon oxide Inorganic materials 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
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Abstract
본 발명은 반도체소자의 미세패턴 형성방법에 관한 것으로서, 고집적 소자의 금속배선 형성공정에서 원자외선(deep ultra violet, DUV)을 광원으로 이용한 노광공정시 TiN/W막 적층구조를 반사방지막(Antireflective Coating layer, ARC)으로 사용함으로써 감광막 패턴을 형성하기 위한 노광공정시 상기 감광막 패턴의 전 지역에 동일한 에너지량을 흡수하도록하여 금속층의 고반사율에 의한 나칭(noching) 등으로 패턴이 훼손되는 것을 방지하여 프로파일이 우수한 감광막 패턴을 형성할 수 있게 하여 미세패턴의 형성을 가능하게 하고, 상기 금속층과의 식각선택비 차이를 이용하여 하드마스크로서의 역할을 행함으로써 소자의 단차를 감소시켜 후속 사진식각공정을 용이하게 하고 그로 인한 반도체소자의 고집적화를 가능하게 하는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a fine pattern of a semiconductor device, wherein an antireflective coating is applied to a TiN / W layer stack structure during an exposure process using deep ultra violet (DUV) as a light source in a metal wiring formation process of a highly integrated device. layer, ARC) to absorb the same amount of energy in the entire area of the photoresist pattern during the exposure process to form the photoresist pattern, thereby preventing the pattern from being damaged due to noching due to the high reflectivity of the metal layer. It is possible to form this excellent photoresist pattern, thereby enabling the formation of a fine pattern, and serves as a hard mask by using the difference in etching selectivity with the metal layer, thereby reducing the step height of the device to facilitate the subsequent photolithography process. And thereby high integration of semiconductor devices.
Description
본 발명은 반도체소자의 미세패턴 형성방법에 관한 것으로, 특히 금속배선 형성공정시 TiN/W막의 적층구조를 반사방지막으로 형성하여 안정적이고 재현성있는 미세패턴을 형성하는 방법에 관한 것이다.The present invention relates to a method for forming a fine pattern of a semiconductor device, and more particularly, to a method for forming a stable and reproducible fine pattern by forming a stacked structure of a TiN / W film as an anti-reflection film during a metal wiring formation process.
최근의 반도체 장치의 고집적화 추세는 미세 패턴 형성 기술의 발전에 큰 영향을 받고 있으며, 반도체 장치의 제조 공정 중에서 식각 또는 이온주입 공정 등의 마스크로 매우 폭 넓게 사용되는 감광막 패턴의 미세화가 필수 요건이다.The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, are essential in the manufacturing process of semiconductor devices.
상기 감광막 패턴의 분해능(R)은 축소노광장치의 광원의 파장(λ) 및 공정 변수(k)에 비례하고, 노광 장치의 렌즈 구경(numerical aperture:NA, 개구수)에 반비례한다.The resolution R of the photoresist pattern is proportional to the wavelength λ of the light source of the reduction exposure apparatus and the process variable k, and inversely proportional to the lens aperture (NA, numerical aperture) of the exposure apparatus.
[R=k*λ/NA, R=해상도, λ=광원의 파장, NA=개구수][R = k * λ / NA, R = resolution, λ = wavelength of light source, NA = number of apertures]
여기서, 상기 축소노광장치의 광분해능을 향상시키기 위하여 광원의 파장을 감소시키게 되며, 예를 들어 파장이 436 및 365㎚인 G-라인 및 i-라인 축소노광장치는 공정 분해능이 각각 약 0.7, 0.5㎛ 정도가 한계이고, 0.5㎛ 이하의 미세 패턴을 형성하기 위해 파장이 작은 원자외선(deep ultra violet, 이하 DUV 라 함), 예를 들어 파장이 248㎚인 KrF 레이저나 193㎚인 ArF 레이저를 광원으로 사용하는 노광 장치를 이용하거나, 공정 상의 방법으로는 노광마스크를 위상 반전 마스크를 사용하는 방법과, 이미지 콘트라스트를 향상시킬 수 있는 별도의 박막을 웨이퍼 상에 형성하는 씨.이.엘.(contrast enhancement layer: 이하 CEL이라 함) 방법이나 두층의 감광막 사이에 에스.오.지.(spin on glass: SOG) 등의 중간층을 개재시킨 삼층레지스트(Tri layer resist: 이하 TLR 라 함) 방법 또는 감광막의 상측에 선택적으로 실리콘을 주입시키는 실리레이션 방법 등이 개발되어 분해능 한계치를 낮추고 있다.Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of about 0.7 and 0.5, respectively. In order to form a fine pattern of 0.5 μm or less, a wavelength of about 1 μm or less is used for deep ultra violet (hereinafter referred to as DUV), for example, a KrF laser having a wavelength of 248 nm or an ArF laser having 193 nm. The exposure apparatus used in the above, or in the process method, the exposure mask using a phase reversal mask, and the C. E. (contrast) for forming a separate thin film on the wafer to improve the image contrast enhancement layer (hereinafter referred to as CEL) method, or a tri-layer resist (hereinafter referred to as TLR) method or a photosensitive film interposed between two layers of photosensitive films such as spin on glass (SOG). It developed a method such as silica illustration of selectively implanting silicon in the upper side may lower the resolution limit.
일반적으로 반도체제조 공정의 리소그래피 공정은 노광마스크의 광차단막 패턴 밀도에 따라 이를 통과하는 빛의 회절 정도 및 근접 패턴을 통과한 빛과의 간섭 등에 의해 동일한 크기의 패턴에서도 실제 웨이퍼에 형성되는 패턴의 크기가 달라지는 현상이 발생한다. 상기와 같은 문제점을 개선하기 위하여 반사방지막을 사용하고 있으며, 상기 반사방지막은 증착 조건 등의 방법에 의하여 굴절율(refractive index)의 실수(n) 및 허수(k), 반사율(reflectance, R) 등과 같은 광학 상수값을 얻을 수 있는 실리콘 옥시나이트라이드(silicon oxynitride, SiOxNy) 막이 사용되고 있으며, 주로 플라즈마 화학기상증착(plasma enhanced chemical vapor deposition, 이하 PE-CVD 라 함)방법으로 형성한다.In general, the lithography process of the semiconductor manufacturing process is the size of the pattern formed on the actual wafer even in the same size pattern due to the diffraction degree of the light passing through it and the interference with the light passing through the proximity pattern according to the light blocking film pattern density of the exposure mask. The phenomenon occurs. In order to improve the above problems, an anti-reflection film is used, and the anti-reflection film has a real index (n), an imaginary number (k), and a reflectance (R) of the refractive index by a method such as deposition conditions. Silicon oxynitride (SiO x N y ) films which can obtain optical constant values are used, and are mainly formed by plasma enhanced chemical vapor deposition (hereinafter referred to as PE-CVD).
또한, 소자가 고집적화 되어감에 따라 도전배선들의 직경은 작아지고, 높이가 증가하여 에스펙트비(aspect ratio)가 증가한다. 따라서, 식각마스크로 감광막만을 사용하여 도전배선들을 식각하기 위하여 상기 감광막을 점점 더 두껍게 형성해야 되기 때문에 하드마스크를 이용하여 식각공정을 실시하기도 한다.In addition, as the device becomes more integrated, the diameters of the conductive wires become smaller, and the height increases, thereby increasing the aspect ratio. Therefore, in order to etch the conductive wires using only the photoresist layer as an etching mask, the photoresist layer needs to be formed thicker and thicker, so that an etching process may be performed using a hard mask.
이하, 첨부된 도면을 참고로 하여 종래기술에 대하여 설명한다.Hereinafter, with reference to the accompanying drawings will be described in the prior art.
도 1 은 종래기술에 따른 반도체소자의 미세패턴 형성방법을 도시한 단면도이고, 도 2 는 종래기술에 의해 SiON막을 금속배선의 하드마스크로 사용하는 경우 감광막에 흡수되는 에너지량을 도시한 그래프도이다.1 is a cross-sectional view illustrating a method for forming a micropattern of a semiconductor device according to the prior art, and FIG. 2 is a graph showing the amount of energy absorbed in the photosensitive film when the SiON film is used as a hard mask of a metal wiring according to the prior art. .
먼저, 워드라인, 비트라인 및 캐패시터와 같은 소정의 하부구조물이 형성되어 있는 반도체기판(11) 상부에 금속배선 콘택으로 예정되는 부분을 노출시키는 금속배선 콘택홀이 구비된 층간절연막(12)을 형성한다. First, an interlayer insulating layer 12 having a metal wiring contact hole exposing a portion intended as a metal wiring contact is formed on the semiconductor substrate 11 on which predetermined substructures such as word lines, bit lines, and capacitors are formed. do.
다음, 층간절연막 상부에 Ti막(13)과 제1TiN막(14)을 순차적으로 형성한다. 이때, 상기 Ti막(13)과 제1TiN막(14)은 확산방지막으로 사용된다.Next, the Ti film 13 and the first TiN film 14 are sequentially formed on the interlayer insulating film. At this time, the Ti film 13 and the first TiN film 14 are used as a diffusion barrier.
그 다음,상기 제1TiN막(14) 상부에 금속층으로 Al막(15)을 형성한다.Next, an Al film 15 is formed as a metal layer on the first TiN film 14.
다음, 상기 Al막(15) 상부에 제2TiN막(16), 플라즈마-산화막(plasma enhanced -oxide, 17) 및 SiON막(18)을 순차적으로 형성한다. 이때, 상기 제2TiN막(16) 및 SiON막(18)은 반사방지막으로 사용되고, 상기 플라즈마-산화막(17)은 하드마스크로 사용된다. Next, a second TiN film 16, a plasma enhanced-oxide 17, and a SiON film 18 are sequentially formed on the Al film 15. In this case, the second TiN film 16 and the SiON film 18 are used as an antireflection film, and the plasma-oxide film 17 is used as a hard mask.
그 다음, 상기 SiON막(18) 상부에 DUV용 감광막(19)을 형성하고, 금속배선 마스크를 이용한 사진식각공정으로 금속배선으로 예정되는 부분을 보호하는 감광막 패턴을 형성한다.Next, a DUV photosensitive film 19 is formed on the SiON film 18, and a photosensitive film pattern is formed to protect a portion intended for metal wiring by a photolithography process using a metal wiring mask.
다음, 상기 감광막 패턴을 식각마스크로 사용하여 상기 SiON막(18) 및 플라즈마-산화막(17)을 패터닝하고, 상기 감광막 패턴을 제거한다.Next, the SiON film 18 and the plasma-oxide film 17 are patterned using the photoresist pattern as an etching mask, and the photoresist pattern is removed.
그 다음, 상기 SiON막(18) 패턴 및 플라즈마-산화막(17) 패턴을 식각마스크로 사용하여 상기 제2TiN막(16), Al막(15), 제1TiN막(14) 및 Ti막(13)을 식각한다. Next, the second TiN film 16, the Al film 15, the first TiN film 14, and the Ti film 13 using the SiON film 18 pattern and the plasma-oxide film 17 pattern as an etching mask. Etch
상기와 같은 종래기술에 따른 반도체소자의 미세패턴 형성방법은, 금속배선형성공정에서 반도체소자가 고집적화되어 감에 따라 애스팩트비가 증가하여 감광막 및 절연막을 이용한 하드마스크를 식각마스크로 사용하여 금속배선을 형성하기 위해서는 상기 감광막과 절연막의 두께를 높게 형성해야 한다. 또한, 도 2 에 도시된 바와 같이 DUV를 광원으로 사용하는 감광막을 사용하는 경우 TiN막은 반사방지막으로서의 역할을 충분히 하지 못하기 때문에 SiON막을 사용하여 상기 TiN막을 보완하였으나 상기 SiON막이 약 300Å 두께일때 반사방지막으로서 역할을 하고, 제거공정시 별도의 식각장비를 필요로 하여 공정이 복잡해지는 문제점이 있다. In the method of forming a micropattern of a semiconductor device according to the related art, the aspect ratio increases as the semiconductor device is highly integrated in the metal wiring forming process, and the metal wiring is formed by using a hard mask using a photosensitive film and an insulating film as an etching mask. In order to form, the thickness of the photosensitive film and the insulating film must be formed high. In addition, when using a photosensitive film using a DUV as a light source as shown in FIG. 2, since the TiN film does not sufficiently function as an anti-reflection film, the TiN film was supplemented using a SiON film, but the anti-reflection film was about 300 Å thick. It serves as a problem, and requires a separate etching equipment during the removal process has a problem that the process is complicated.
본 발명은 상기한 문제점을 해결하기 위하여, DUV를 광원으로 사용하는 감광막을 이용하여 금속배선을 형성하는 경우에 금속층 상부에 W막을 형성하고, 반사방지막인 TiN막을 형성한 다음, 감광막 패턴을 형성함으로써 상기 TiN막의 역할을 보완하고, 금속층과의 식각선택비를 증가시켜 원하는 형태의 감광막 패턴을 얻을 수 있고, 그에 따른 반도체소자의 특성 및 신뢰성을 향상시키는 반도체소자의 미세패턴 형성방법을 제공하는데 그 목적이 있다. In order to solve the above problems, in the case of forming a metal wiring by using a photosensitive film using DUV as a light source, a W film is formed on the upper metal layer, a TiN film as an antireflection film is formed, and then a photosensitive film pattern is formed. The purpose of the present invention is to provide a method of forming a micropattern of a semiconductor device, which complements the role of the TiN film and increases an etching selectivity with a metal layer to obtain a photoresist pattern having a desired shape, thereby improving characteristics and reliability of the semiconductor device. There is this.
상기 목적을 달성하기 위해 본 발명에 따른 반도체소자의 미세패턴 형성방법은, In order to achieve the above object, the method of forming a fine pattern of a semiconductor device according to the present invention,
소정의 하부구조물이 형성되어 있는 반도체기판 상부에 금속배선 콘택으로 예정되는 금속배선 콘택홀이 구비된 층간절연막을 형성하는 공정과,Forming an interlayer insulating film having a metal wiring contact hole, which is intended as a metal wiring contact, on the semiconductor substrate on which a predetermined substructure is formed;
상기 층간절연막 상부에 확산방지막과 금속층을 형성하는 공정과,Forming a diffusion barrier film and a metal layer on the interlayer insulating film;
상기 금속층 상부에 상기 금속층과 식각선택비 차이를 갖고 반사방지막 기능을 하는 W막을 형성하는 공정과,Forming a W film having an etch selectivity difference with the metal layer and acting as an anti-reflection film on the metal layer;
상기 W막 상부에 반사방지막인 TiN막을 형성하는 공정과,Forming a TiN film as an anti-reflection film on the W film;
상기 TiN막 상부에 금속배선으로 예정되는 부분을 보호하는 감광막 패턴을 형성하는 공정과,Forming a photoresist pattern on the TiN film to protect a portion of the TiN film;
상기 감광막 패턴을 식각마스크로 사용하여 상기 W막과 TiN막을 패터닝하는 공정과,Patterning the W film and the TiN film by using the photoresist pattern as an etching mask;
상기 감광막 패턴을 제거하는 공정과,Removing the photoresist pattern;
상기 W막과 TiN막 패턴을 식각마스크로 사용하여 상기 금속층 및 확산방지막을 식각하는 공정을 포함하는 것을 특징으로 한다.And etching the metal layer and the diffusion barrier layer by using the W film and the TiN film pattern as an etching mask.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 3 은 본 발명에 따른 반도체소자의 미세패턴 형성방법을 도시한 단면도이다. 3 is a cross-sectional view illustrating a method of forming a fine pattern of a semiconductor device according to the present invention.
먼저, 워드라인, 비트라인 및 캐패시터와 같은 소정의 하부구조물이 형성되어 있는 반도체기판(21) 상부에 금속배선 콘택으로 예정되는 부분을 노출시키는 금속배선 콘택홀이 구비된 층간절연막(22)을 형성한다. First, an interlayer insulating layer 22 having a metal wiring contact hole exposing a portion intended as a metal wiring contact is formed on the semiconductor substrate 21 on which predetermined substructures such as word lines, bit lines, and capacitors are formed. do.
다음, 층간절연막 상부에 Ti막(23)과 제1TiN막(24)을 순차적으로 형성한다. 이때, 상기 Ti막(23)은 200 ∼ 500Å 두께로 형성하고, 상기 제1TiN막(24)은 200 ∼ 700Å 두께로 형성되며, 확산방지막으로 사용된다.Next, the Ti film 23 and the first TiN film 24 are sequentially formed on the interlayer insulating film. At this time, the Ti film 23 is formed to a thickness of 200 ~ 500Å, the first TiN film 24 is formed to a thickness of 200 ~ 700Å, it is used as a diffusion barrier film.
그 다음,상기 제1TiN막(24) 상부에 금속층으로 Al막(25)을 3500 ∼ 4500 Å두께 형성한다. Next, an Al film 25 is formed on the first TiN film 24 with a metal layer of 3500 to 4500 mm thickness.
다음, 상기 Al막(25) 상부에 W막(26)과 제2TiN막(27)을 순차적으로 형성한다. 이때, 상기 W막(26)은 100 ∼ 1000Å 두께로 형성되고, 반사방지막인 상기 제2TiN막(27)의 기능을 보완하는 동시에 상기 Al막(25)의 식각공정시 하드마스크로도 사용된다. 상기 W막(26)은 100Å 정도의 두께로 상기 Al막(25)을 4000Å 까지 식각하는데 하드마스크로서 역할이 가능하다.Next, a W film 26 and a second TiN film 27 are sequentially formed on the Al film 25. At this time, the W film 26 is formed to a thickness of 100 ~ 1000Å, and complements the function of the second TiN film 27, which is an antireflection film, and is also used as a hard mask during the etching process of the Al film 25. The W film 26 may serve as a hard mask to etch the Al film 25 to 4000 mW with a thickness of about 100 mW.
그 다음, 상기 제2TiN막(27) 상부에 감광막(28)을 900 ∼1100Å 두께로 형성하고, 금속배선 마스크를 이용한 사진식각공정으로 금속배선으로 예정되는 부분을 보호하는 감광막(28) 패턴을 형성한다. Next, a photoresist layer 28 is formed on the second TiN film 27 to a thickness of 900 to 1100 Å, and a photoresist layer 28 pattern is formed to protect a portion intended for metal wiring by a photolithography process using a metal wiring mask. do.
다음, 상기 감광막(28) 패턴을 식각마스크로 사용하여 상기 제2TiN막(27)과 W막(26)을 식각한 후, 상기 감광막(28) 패턴을 제거한다. 이때, 상기 제2TiN막(27)은 염소가스 분위기에서 식각하고, 상기W막(26)은 불소가스 분위기에서 식각한다. Next, the second TiN film 27 and the W film 26 are etched using the photoresist 28 pattern as an etching mask, and then the photoresist 28 pattern is removed. In this case, the second TiN film 27 is etched in a chlorine gas atmosphere, and the W film 26 is etched in a fluorine gas atmosphere.
그 다음, 상기 제2TiN막(27)과 W막(26)을 식각마스크로 사용하고, 염소가스 분위기에서 상기 Al막(25), 제1TiN막(24) 및 Ti막(23)을 식각하여 금속배선을 형성한다. 이때, 상기 W막(26)과 Al막(25)이 1 : 30 ∼ 1 : 100 정도의 식각선택비를 갖도록 한다. Then, the second TiN film 27 and the W film 26 are used as an etching mask, and the Al film 25, the first TiN film 24, and the Ti film 23 are etched in a chlorine gas atmosphere. Form the wiring. In this case, the W film 26 and the Al film 25 have an etching selectivity of about 1:30 to 1: 100.
도 4 는 본 발명에 의해 W을 금속배선을 반사방지막 및 하드마스크로 사용하는 경우 감광막에 흡수되는 에너지량을 도시한 그래프도로서, 상기 Al막(24) 상부에 W막(26)을 형성한 경우 상기 감광막(28) 패턴에 흡수되는 에너지량을 나타낸다.FIG. 4 is a graph showing the amount of energy absorbed by the photosensitive film when W is used as the anti-reflection film and the hard mask according to the present invention, wherein the W film 26 is formed over the Al film 24 In this case, the amount of energy absorbed in the photoresist layer 28 pattern is represented.
상기 W막(26)의 두께가 약 180Å 이상인 경우 상기 감광막(28) 패턴에 흡수되는 에너지량이 전 지역에서 동일한 것을 알 수 있다. 이는 상기 W막(26)이 상기 제2TiN막(27)의 반사방지막 기능을 보완하여 상기 Al막(25)이 안정한 형태로 패터닝되도록 한다.When the thickness of the W film 26 is about 180 kW or more, it can be seen that the amount of energy absorbed by the photosensitive film 28 pattern is the same in all regions. This allows the W film 26 to complement the anti-reflection film function of the second TiN film 27 so that the Al film 25 is patterned in a stable form.
상기한 바와같이 본 발명에 따른 반도체소자의 미세패턴 형성방법은, 고집적 소자의 금속배선 형성공정에서 DUV를 광원으로 이용한 노광공정시 TiN/W막 적층구조를 반사방지막으로 사용함으로써 감광막 패턴을 형성하기 위한 노광공정시 상기 감광막 패턴의 전 지역에 동일한 에너지량을 흡수하도록하여 금속층의 고반사율에 의한 나칭 등으로 패턴이 훼손되는 것을 방지하여 프로파일이 우수한 감광막 패턴을 형성할 수 있게 하여 미세패턴의 형성을 가능하게 하고, 상기 금속층과의 식각선택비 차이를 이용하여 하드마스크로서의 역할을 행함으로써 소자의 단차를 감소시켜 후속 사진식각공정을 용이하게 하고 그로 인한 반도체소자의 고집적화를 가능하게 하는 이점이 있다.As described above, in the method of forming a fine pattern of a semiconductor device according to the present invention, a photosensitive film pattern is formed by using a TiN / W film stack as an antireflection film during an exposure process using a DUV as a light source in a metal wiring forming step of a highly integrated device. During the exposure process, the same amount of energy is absorbed in the entire area of the photoresist pattern, thereby preventing the pattern from being damaged by the nagging due to the high reflectance of the metal layer, thereby forming a photoresist pattern having excellent profile, thereby forming a fine pattern. And by using the difference in the etching selectivity with the metal layer as a hard mask by reducing the step of the device has the advantage of facilitating subsequent photolithography process and thereby high integration of the semiconductor device.
도 1 은 종래기술에 따른 반도체소자의 미세패턴 형성방법을 도시한 단면도.1 is a cross-sectional view showing a method for forming a fine pattern of a semiconductor device according to the prior art.
도 2 는 종래기술에 의해 PE-SiON막을 금속배선의 하드마스크로 사용하는 경우 감광막에 흡수되는 에너지량을 도시한 그래프도.FIG. 2 is a graph showing the amount of energy absorbed in the photosensitive film when the PE-SiON film is used as a hard mask for metal wiring according to the prior art; FIG.
도 3 은 본 발명에 따른 반도체소자의 미세패턴 형성방법을 도시한 단면도. 3 is a cross-sectional view showing a method for forming a fine pattern of a semiconductor device according to the present invention.
도 4 는 본 발명에 의해 W을 금속배선을 반사방지막 및 하드마스크로 사용하는 경우 감광막에 흡수되는 에너지량을 도시한 그래프도. 4 is a graph showing the amount of energy absorbed in the photosensitive film when W is used as the anti-reflection film and the hard mask according to the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
11, 21 : 반도체기판 12, 22 : 층간절연막11, 21: semiconductor substrate 12, 22: interlayer insulating film
13, 23 : Ti막 14 : 제1TiN막13, 23: Ti film 14: first TiN film
15, 25 : Al막 16, 27 : 제2TiN막15, 25: Al film 16, 27: second TiN film
17 : PE-산화막 18 : SiON막17: PE-oxide film 18: SiON film
19, 28 : 감광막 26 : 텅스텐막19, 28: photosensitive film 26: tungsten film
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|---|---|---|---|---|
| JPH0529476A (en) * | 1991-04-26 | 1993-02-05 | Mitsubishi Electric Corp | Wiring connection structure of semiconductor device |
| JPH0669122A (en) * | 1992-05-28 | 1994-03-11 | Nec Corp | Fabrication of semiconductor device |
| KR980005523A (en) * | 1996-06-27 | 1998-03-30 | 김주용 | METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR |
| KR19980060584A (en) * | 1996-12-31 | 1998-10-07 | 김영환 | Metal wiring formation method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0529476A (en) * | 1991-04-26 | 1993-02-05 | Mitsubishi Electric Corp | Wiring connection structure of semiconductor device |
| JPH0669122A (en) * | 1992-05-28 | 1994-03-11 | Nec Corp | Fabrication of semiconductor device |
| KR980005523A (en) * | 1996-06-27 | 1998-03-30 | 김주용 | METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR |
| KR19980060584A (en) * | 1996-12-31 | 1998-10-07 | 김영환 | Metal wiring formation method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100727439B1 (en) | 2005-03-22 | 2007-06-13 | 주식회사 하이닉스반도체 | Method for forming interconnection line |
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