KR100347246B1 - Fabricating method of semiconductor device - Google Patents

Abstract

The present invention relates to a method of fabricating a semiconductor device, by using a silicon oxide film formed during the silylation process in a via contact forming process as an etching mask, the photoresist film and the low dielectric film can be continuously etched, and a conventional hard mask is not used. Therefore, the process can be simplified and the cost can be reduced. In particular, the silicide process is applied to the fine pattern forming process of the metal layer to improve process margins such as depth of focus (DOF) and energy latitude (EL), and to form photoresist patterns. It is a technology that stabilizes the process by forming a pattern without being affected by the lower step.

Description

Fabrication method of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, by applying a silylation process in a via contact forming process, a photoresist film and a low dielectric material are dry etched at the same time to form a via contact hole, thereby performing a simple and stable process. The present invention relates to a method for manufacturing a semiconductor device.

The recent trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, are essential in the manufacturing process of semiconductor devices.

The resolution R of the photoresist pattern is proportional to the wavelength λ of the light source of the reduction exposure apparatus and the process variable k, and inversely proportional to the lens aperture (NA, numerical aperture) of the exposure apparatus.

[R = k * λ / NA, R = resolution, λ = wavelength of light source, NA = number of apertures]

Here, the wavelength of the light source is reduced in order to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of about 0.7 and 0.5, respectively. In order to form a fine pattern of 0.5 μm or less, a wavelength of about 1 μm or less is used for deep ultra violet (hereinafter referred to as DUV), for example, a KrF laser having a wavelength of 248 nm or an ArF laser having 193 nm. The exposure apparatus used in the above, or in the process method, the exposure mask using a phase reversal mask, and the C. E. (contrast) for forming a separate thin film on the wafer to improve the image contrast enhancement layer (hereinafter referred to as CEL) method, or a tri-layer resist (hereinafter referred to as TLR) method or a photosensitive film interposed between two layers of photosensitive films such as spin on glass (SOG). It developed a method such as silica illustration of selectively implanting silicon in the upper side may lower the resolution limit.

In general, the lithography process of the semiconductor manufacturing process is the size of the pattern formed on the actual wafer even in the same size pattern due to the diffraction degree of the light passing through it and the interference with the light passing through the proximity pattern according to the light blocking film pattern density of the exposure mask. The phenomenon occurs. In order to improve the above problems, an anti-reflection film is used, and the anti-reflection film has a real index (n), an imaginary number (k), and a reflectance (R) of the refractive index by a method such as deposition conditions. Silicon oxynitride (SiO _x N _y ) films which can obtain optical constant values are used, and are mainly formed by plasma enhanced chemical vapor deposition (hereinafter referred to as PE-CVD).

In addition, as the device becomes more integrated, the diameters of the conductive wires become smaller, and the height increases, thereby increasing the aspect ratio. Therefore, in order to etch the conductive wires using only the photoresist layer as an etching mask, the photoresist layer needs to be formed thicker and thicker, so that an etching process may be performed using a hard mask.

Hereinafter, a method of manufacturing a semiconductor device according to the related art will be described with reference to the accompanying drawings.

1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

An interlayer insulating film 13 is formed on the semiconductor substrate 11 on which a predetermined lower structure is formed and planarized.

Next, a metal wiring 15 such as tungsten or aluminum is formed on the interlayer insulating film 13.

Next, a low dielectric film 17 and a hard mask thin film 19 are formed on the metal wiring 15. The hard mask thin film 19 is formed of a material having a high dielectric constant such as a nitride film. (See Figure 1A)

Next, a photoresist pattern 21 is formed on the hard mask thin film 19 to expose a portion to be contacted. (See FIG. 1B)

Next, the thin film for hard mask 19 is etched using the photoresist pattern 21 as an etching mask, and the photoresist pattern 21 is removed.

Next, the low dielectric layer 17 is etched using the photoresist pattern 21 as an etch mask to form a via contact hole exposing the metal line 15.

Thereafter, a conductive layer is formed over the entire surface, and a via contact 23 filling the via contact hole is formed by performing an entire surface etching or CMP process. (See FIG. 1C)

As described above, in the method of manufacturing a semiconductor device according to the prior art, since the photoresist film used as an etching mask must be thickened in order to secure a constant etching selectivity during the etching process of the thin film for a hard mask, the consumption of the photoresist film is increased. In order to pattern the thin film for the hard mask, a complicated process of several steps must be performed, which requires a lot of processing time, thereby reducing the throughput per hour. In addition, a thin film such as a nitride film used as a hard mask has a problem of lowering the operation speed of the device because a low capacitance cannot be obtained in spite of a reduction in design rules in the metallization forming process due to high dielectric constant.

In order to solve the above problems of the prior art, a silicon oxide film is formed on the surface of the photoresist film by applying a silylation process without using a hard mask, and then using the silicon oxide film as an etching mask. It is an object of the present invention to provide a method for manufacturing a semiconductor device that simplifies the process by continuously etching the low dielectric film in the same equipment.

1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

<Description of Signs of Major Parts of Drawings>

11, 41: semiconductor substrate 13, 43: interlayer insulating film

15, 45: metal wiring 17, 47: low dielectric film

19: thin film for hard mask 21, 50: photosensitive film pattern 48: low dielectric film pattern 49: photosensitive film

23, 57: via contact 51: exposure mask

55 silicon oxide film 53 silylated photosensitive film

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention,

Forming an interlayer insulating film on the semiconductor substrate on which a predetermined lower structure is formed;

Forming a metal wiring on the interlayer insulating film;

Forming a low dielectric film and a silicide photosensitive film on the metal wiring;

Exposing a surface of the photosensitive film using a via contact mask using an exposure mask;

A siliculation process of drying the photoresist in two steps to change the non-exposed portion into a silicon oxide film on the surface of the photoresist;

And etching the photoresist film and the low dielectric film using the silicon oxide film as an etching mask to form a contact hole exposing the metal wiring.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A and 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

First, an interlayer insulating layer 43 is formed on the semiconductor substrate 41 on which a predetermined lower structure is formed and planarized, and then a metal wiring 45 is formed on the interlayer insulating layer 43. The metal wire 45 is formed of a metal thin film such as tungsten (W) or aluminum (Al).

Next, a low dielectric film 47 is applied on the metal wiring 45 in a multilayer of 1000 to 30000 Å thick. The low dielectric film 47 may be an organic low dielectric film such as polyarylene ether, polyimide or polybenzocyclobutene, or an inorganic low dielectric film or silsesquioxane-based inorganic material containing silicon or these It is formed into a mixture of

Among the low dielectric films 47, the organic low dielectric film is propylene glycol, dimethyl ether hexahexanone, isobutyl methyl ketone, 2-heptanone, 3-heptanone, 4-heptanone, cyclopentanone, 2 Ketone solvents such as methylcyclopentanone, 3-methylcyclopentanone, 2-methylcyclohexanone, 3-methylcyclohexanone, and 2,4-dimethylpentanone and ethyl lactate, 2- It is formed using methoxyethyl acetate or a commonly used organic solvent.

Then, the low dielectric film 47 is cured at 50 to 600 ° C. for 30 seconds to 120 minutes, and the low dielectric film 47 is prevented from splitting two to five times during the curing process. Curing process is performed by gradually raising the temperature to 600 ° C, the process temperature.

Next, a photosensitive film 49 is applied on the low dielectric film 47 to a thickness of 5000 to 30000 kPa.

Thereafter, the photosensitive film 49 is soft baked at a temperature of 90 to 180 ° C. for 30 to 300 seconds to remove the solvent in the photosensitive film 49.

Next, the photoresist film 49 is exposed using a via contact mask that exposes a portion intended to be a via contact as an exposure mask. The exposure process is carried out using ArF, DUV, E-beam, ion beam or X-ray as the light source. (See Figure 2A)

Next, the exposed photosensitive film 49 is presilylation bake.

Next, the photosensitive film 49 is hexamethyldisilazane, tetramethyldisilazane, bisdimethylamino dimethylsilane, bisdimethylamino methylsilane, dimethylsilyl dimethylamine, dimethylsilyl diethylamine, trimethylsilyl dimethylamine, trimethylsilyl Silylation in the liquid phase or gas phase is carried out using a silylation agent having an N-Si bond such as diethylamine, dimethylamino pentamethyldisilane, or the like. The said silylation process is performed for 30 to 300 second at 90-250 degreeC.

Thereafter, the photosensitive film 49 is subjected to primary dry development using a mixed gas containing fluorine-based, chlorine-based, and oxygen-based gases, and the primary dry developing step is performed for 1 to 100 seconds.

Subsequently, the secondary dry development step using the mixed gas containing the oxygen-based and carbon dioxide-based gas is performed for the photosensitive film 49 for 10 to 500 seconds. The secondary dry development process is carried out in a 10 to 80% transient etching process.

The non-exposed portion of the photosensitive film 49 is silized by the primary dry development process and the secondary dry development process, and the silylated photosensitive film 53 is changed to the silicon oxide film 55.

Next, using the silicon oxide film 55 as an etching mask, the photosensitive film 49 and the low dielectric film 47 are etched in-situ to expose the metal wiring 45 to expose the photosensitive film pattern 50. ) And a low dielectric film pattern 48 are formed.

Next, a metal layer (not shown) is formed over the entire surface, and then the metal layer is etched by a full surface etching or chemical mechanical polishing process to form a via contact 57 filling the contact hole.

In addition, a line / space may be formed by the above process.

As a first embodiment of the present invention, after forming a polyarylene ether-based organic low dielectric on the metal wiring to a thickness of 5000 kPa, it is cured at 400 ℃ for 60 minutes. Thereafter, a silicication photoresist is applied on the low dielectrics to a thickness of 7000 kPa. Then, the silylation photoresist is softbaked at 130 ° C. for 90 seconds.

Next, presilylation bake is performed at 170 ° C. for 150 seconds through exposure.

Next, the upper layer of the photoresist is silylated using tetramethyl disilazane, which is a gas phase silylation agent. After the silylated wafer is patterned using a mixed gas of prorin, oxygen, or chlorine, at this time, the lower organic low dielectric is etched in the same chamber by using the formed silicon oxide film as an etch stop layer.

As a second embodiment of the present invention, an inorganic low dielectric of polysilsesquioxane type is formed on the metal wiring to a thickness of 7000 kPa, and then cured at 600 ° C for 30 minutes. Thereafter, a silicication photoresist is applied on the low dielectrics to a thickness of 7000 kPa. Then, the silylation photoresist is softbaked at 130 ° C. for 90 seconds.

Next, presilylation bake is performed at 170 ° C. for 150 seconds through exposure.

Next, the upper layer of the photoresist is silylated using tetramethyl disilazane, which is a gas phase silylation agent. After the silylated wafer is patterned using a mixed gas of prorin, oxygen, or chlorine, at this time, the lower organic low dielectric is etched in the same chamber by using the formed silicon oxide film as an etch stop layer.

As a third embodiment of the present invention, after forming a polyimide-based organic low-k dielectric with a thickness of 5000 kPa on a metal wiring, curing is performed at 450 ° C. for 60 minutes. Thereafter, a silicication photoresist is applied on the low dielectrics to a thickness of 7000 kPa. Then, the silylation photoresist is softbaked at 130 ° C. for 90 seconds.

Next, presilylation bake is performed at 170 ° C. for 150 seconds through exposure.

Next, the upper layer of the photoresist is silylated using tetramethyl disilazane, which is a gas phase silylation agent. After the silylated wafer is patterned using a mixed gas of prorin, oxygen, or chlorine, at this time, the lower organic low dielectric is etched in the same chamber by using the formed silicon oxide film as an etch stop layer.

As a fourth embodiment of the present invention, after forming a butene-based organic low dielectric with 5000 kW thick on a metal wire, curing is performed at 400 ° C. for 60 minutes. Thereafter, a silicication photoresist is applied on the low dielectrics to a thickness of 7000 kPa. Then, the silylation photoresist is softbaked at 130 ° C. for 90 seconds.

Next, presilylation bake is performed at 170 ° C. for 150 seconds through exposure.

Next, the upper layer of the photoresist is silylated using tetramethyl disilazane, which is a gas phase silylation agent. The silylated wafer is patterned using a mixed gas of prorin, oxygen or chlorine, and the lower organic low dielectric material is etched in the same chamber by using the silicon oxide film formed in the process as an etch stop layer.

As described above, in the method for manufacturing a semiconductor device according to the present invention, since the photoresist film and the low dielectric film can be etched continuously by using the silicon oxide film formed during the silylation process as an etching mask, the conventional hard mask is not used. The process can be simplified and the cost can be reduced.In particular, the silicide process is applied to the fine pattern forming process of metal wiring to improve the process margins such as depth of focus (DOF), EL, and the like. There is an advantage of stabilizing the process by forming a pattern without being affected.

Claims (13)

Forming an interlayer insulating film on the semiconductor substrate on which a predetermined lower structure is formed; Forming a metal wiring on the interlayer insulating film; Forming a low dielectric film and a silicide photosensitive film on the metal wiring; Exposing a surface of the photosensitive film using a via contact mask using an exposure mask; A siliculation process of drying the photoresist in two steps to change the non-exposed portion into a silicon oxide film on the surface of the photoresist; And forming a contact hole for exposing the metal wiring by etching the photosensitive film and the low dielectric film using the silicon oxide film as an etching mask. The method of claim 1, The metal wiring is a semiconductor device manufacturing method, characterized in that formed by a metal layer such as tungsten, aluminum. The method of claim 1, The low dielectric film may be an organic low dielectric film such as polyarylene ether, polyimide, polybenzocyclobutene, or an inorganic low dielectric film of silsesquioxane or an inorganic material containing silicon, or a combination of the above materials. Forming a semiconductor device, characterized in that formed. The method according to claim 1 or 3, The low-dielectric film is a semiconductor device manufacturing method, characterized in that to form a 1000 to 30000 Å thickness in a multi-layer. The method of claim 1, The low dielectric film is propylene glycol, dimethyl ether cyclohexanone, isobutyl methyl ketone, 2-heptanone, 3-heptanone, 4-heptanone, cyclopentanone, 2-methylcyclopentanone, 3 Ketone solvents such as methylcyclopentanone, 2-methylcyclohexanone, 3-methylcyclohexanone, 2,4-dimethylpentanone or ethyl lactate, 2-methoxyethyl acetate or commonly used Method for manufacturing a semiconductor device, characterized in that formed using the organic solvent as a coating solvent. The method of claim 1, The low dielectric film is formed and then cured at 50 to 600 ° C. for 30 seconds to 120 minutes. The method of claim 6, In the curing process, the process temperature is raised to 600 ℃ over 2 to 5 times stepwise manufacturing method of a semiconductor device. The method of claim 1, The photosensitive film is formed to a thickness of 5000 ~ 30000 다음 and then softbaked for 30 to 300 seconds at a temperature of 90 ~ 180 ℃. The method of claim 1, The exposure process is a method of manufacturing a semiconductor device, characterized in that performed using ArF, DUV, E-beam, ion beam or X-ray as a light source. The method of claim 1, The silylation process is hexamethyldisilazane, tetramethyldisilazane, bisdimethylamino dimethylsilane, bisdimethylamino methylsilane, dimethylsilyl dimethylamine, dimethylsilyl diethylamine, trimethylsilyl dimethylamine, trimethylsilyl diethylamine And a silylation agent having an N-Si bond, such as dimethylamino pentamethyldisilane, in a liquid phase or in a gas phase. The method of claim 1, The silylation process is carried out for 30 to 300 seconds at 90 to 250 ℃ manufacturing method of a semiconductor device. The method of claim 1, The dry development process is performed for 1 to 100 seconds using a mixed gas containing a fluorine-based, chlorine-based and oxygen-based gas, and then 10 to 500 seconds using a mixed gas containing an oxygen-based or carbon dioxide-based gas. A method of manufacturing a semiconductor device, comprising: performing a secondary dry development step in a 10 to 80% transient etching process. The method of claim 1, The manufacturing method of the semiconductor device is a semiconductor device manufacturing method, characterized in that applied to the process of forming a line / space pattern in addition to the via contact.