JP2001326173A - Pattern-forming method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pattern-forming method which reduces the number of defects formed in a resist film to provide a satisfactory yield, in lithography using a short-wavelength light source. SOLUTION: In a process of forming a resist thin film on a substrate to be processed, a resist film of 0.3 μm or smaller is formed by the film formation in two or more steps.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a pattern forming method using a projection exposure apparatus, and more particularly to a pattern forming method suitable for a MOS semiconductor device and a method of manufacturing the same.

[0002]

2. Description of the Related Art In the manufacture of semiconductor devices, as a technique for forming a pattern that achieves both high integration of circuits and high throughput,
An optical lithography technique using far ultraviolet light such as an ArF excimer laser having a wavelength of 193 nm is used. In this method, light that has passed through a mask pattern is projected and exposed on a resist film formed on a substrate to be processed through a projection optical system, and is developed to form a pattern.

In order to improve the resolution of a transfer pattern,
The light source wavelength has been shortened, and the wavelength is 157 nm.
The introduction of an F ₂ excimer laser is also being studied. At a wavelength of about 170 nm or less, the absorption of the resist material increases, and it is necessary to reduce the resist film thickness in order to transfer a pattern.

As a method of forming the resist film, a spin coating method, a chemical vapor deposition (CVD) method, and the like are known. Various resist pattern forming methods including the above method are discussed in, for example, "Resist Material / Process Technology" (published by Technical Information Association, 1994).

[0005]

However, the prior art has a problem that the yield decreases because the number of defects in the resist increases as the thickness of the resist decreases. In addition, there has been a problem that the size of the resist pattern fluctuates due to the defect in the resist film, and the performance of the manufactured semiconductor device is deteriorated.

An object of the present invention is to provide a pattern forming method which can reduce the number of defects formed in a resist film and has a good yield. Another object of the present invention is to prevent performance degradation of a semiconductor device by using a pattern forming method for reducing the number of defects in a resist film.

[0007]

The object of the present invention is to form a resist thin film on a substrate to be processed, a step of selectively irradiating the film with an energy beam such as light, and a method of forming the exposed portion or the unexposed portion. A pattern forming method including a step of selectively removing, comprising a step of forming a resist film having a total thickness of 0.3 μm or less on a substrate to be processed by forming a film two or more times. Is achieved by

The above process will be described with reference to FIG. When a first-layer resist 101 is formed on a desired substrate 103, for example, a defect having a concave portion (a so-called white defect) 102
May be formed. In the present invention,
A second resist film 104 is formed. by this,
The defect 102 is filled, and a film with few defects is formed.

The defects in the resist film depend on the thickness of the resist, the method of forming the film, and the material of the resist. Defects in the film include, as shown in the figure, defects such as pinholes and voids in the resist.
There are various things.

For use in photolithography with a light source wavelength of 200 nm or less, the resist film thickness is 0.3 μm or less in order to prevent pattern collapse of the formed resist, improve resolution, and improve process latitude. It is desirable.
Light absorption in the resist film tends to increase as the wavelength becomes shorter. If the light absorption is too large, the exposure light will not reach the bottom of the resist, resulting in poor pattern resolution. Therefore, when the wavelength is shorter than 170 nm, it is essential to reduce the resist film thickness to 0.3 μm or less.

The relationship between the thickness of the resist and the number of defects can be measured by the following method. First, a resist is applied to Si with a desired film thickness. Thereafter, the wafer is observed with a defect inspection device. After plating the resist,
Since the defective portion of the resist film is plated on the resist film, the defective portion can be more easily detected. In this case, the plating conditions are one of the factors that determine the detection sensitivity.

When a resist film is formed in a plurality of steps according to the present invention, it is difficult to form a defect at the same position of the lower layer and the upper layer, so that the defect density of the formed film can be remarkably reduced. Further, as the number of times of forming the resist film increases, the defect density in the resist film decreases. Therefore, it is possible to select the number of times of forming the resist film according to the desired defect density.

The causes of defects during spin coating are as follows.
A problem caused by surface tension such as generation of microbubbles due to entrainment of air when the resist is dropped may be considered. Also,
The causes of defects during the formation of the CVD film include a black defect formed by dust and the like falling into the film and a white defect formed at a low density portion. The method of the present invention is particularly effective for the above white defects.

When the present invention is carried out by a plurality of spin coating methods, it is desirable that the step of the underlying substrate be previously reduced as much as possible by using CMP or the like.

When wet development is performed, the shape of the resist pattern to be formed can be improved by changing the dissolution rate of the resist film formed on the upper layer and the resist film formed on the lower layer in a developing solution. For example, in the case of a positive resist, the resist shape is improved by increasing the dissolution rate of the exposed portion of the resist film formed below. Also, the light absorption coefficient at the exposure wavelength is
Similar effects can be obtained by optimizing each resist film.

The resist film is formed by spin coating, CV
A method such as Method D can be used. It is also possible to form a resist film by combining different film forming methods. By optimizing the material composition of each film, the resolution and shape of the resist pattern to be formed can be improved. In addition, it is desirable to introduce a step such as a surface treatment between the film formation and the film formation as required, for example, to enhance adhesion.

The method of the present invention is effective not only in the case where the constituent material of the resist film is an organic substance but also in a two-layer resist process method using a Si-containing resist.
During dry development in the two-layer resist process, if there is a white defect in the upper resist pattern, it is transferred to the lower layer. Therefore, the reduction of defects by the present method is effective for improving the yield even in the two-layer resist process.

The second object is attained by manufacturing a semiconductor device by using the pattern forming method for reducing the number of defects in the resist film. If there is a defect in the resist film, if the defect is relatively large with respect to a desired dimension, disconnection or the like is caused, leading to a decrease in yield. On the other hand, if the defect is relatively small with respect to the desired dimension, the dimension of the resist pattern changes. Since the above dimensional change can be avoided by reducing the defects in the resist film, by applying the present method, it is possible not only to improve the yield but also to manufacture a semiconductor device having more uniform dimensions, The performance can be improved.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Example 1) A PVP (polyvinyl phenol) resist having a thickness of 50 nm was formed on a Si substrate by spin coating, and the number of defects was measured by a defect inspection apparatus. FIG. 2 shows the result of the defect measurement. Fifteen defects were found on 25 8-inch wafers. Next, a 50 nm-thick PVP-based resist film serving as a second layer was applied to the wafer, and the number of defects was measured again using a defect inspection apparatus. As a result, only one defect was measured for 25 8-inch wafers. Did not. Further, when a PVP-based resist serving as a third layer was applied to the wafer with a thickness of 50 nm and a defect inspection measurement was performed, no defect in the resist film was measured. As described above, the effect of reducing defects in the resist film by the present method was confirmed.

When the resist has a thickness of 30 nm or more, a film having a uniform thickness can be formed by spin coating. Therefore,
In the case of forming a 180 nm film, it was possible to form a film by recoating up to six times. When a film is formed a plurality of times by the spin coating method, it is necessary to set processes such as the viscosity of the resist and the heat treatment while paying attention to uniformity of the film thickness, selection of a solvent, and the like. Further, in order to enhance the adhesion between the resist film and the resist film and the surface, it is preferable to perform a surface treatment or add a material before forming the film.

(Example 2) An organic film having a thickness of 200 nm was deposited on a Si substrate by a CVD method. Next, a photosensitive polysilane film was formed with a thickness of 30 nm. At this time, when the number of defects was measured by a defect inspection apparatus, a total of 128 defects were detected on the polysilane film for 25 8-inch wafers. Next, a photosensitive polysilane film is formed again in the same manner as above.
The film was formed with a thickness of 5 nm, and the defect was measured by a defect inspection apparatus. As a result, the number of defects was 2 on 25 8-inch wafers. As a result, the effect of reducing defects in the resist film by the present method was confirmed.

Next, pattern transfer was performed with an F ₂ exposure apparatus having a lens numerical aperture NA = 0.6 and illumination coherency σ = 0.6 to cause a photo-oxidation reaction on the exposed portion of the photosensitive polysilane film. . After performing dry development with chlorine gas to remove the unoxidized portion of the polysilane film, the pattern was transferred to a lower organic film by exposing the film to oxygen plasma. When the formed pattern was observed by a cross-sectional SEM, formation of a 0.1 μm L / S gate pattern was confirmed. As described above, a fine gate pattern could be formed without defects using the present method.

Example 3 After forming a polysilane-based resist with a thickness of 50 nm on a Si substrate by a CVD method,
As a result of measurement using a defect inspection apparatus, a total of 57 defects were detected on 25 8-inch wafers. Next, a cycloolefin-based resist was formed on the wafer with a thickness of 50 nm, and measured again with a defect inspection apparatus. As a result, two defects were measured on 25 8-inch wafers. As described above, the effect of reducing defects in the resist film by the present method was confirmed.

The white defect portion in the lower resist film formed by the CVD method was measured by AFM (atomic force microscope).
No change in the film thickness of the defective portion was observed. Also,
When a black defect (projection-like defect) was similarly measured by AFM, it was found that the degree of projection on the surface was improved.

Incidentally, in order to enhance the adhesion between the CVD resist film and the resist film formed by the spin coating, etc.,
It is preferable to perform a surface treatment before forming the upper layer film or to add a low molecular weight component to the coating type resist.

(Embodiment 4) Next, an example in which the present invention is applied to a gate processing step of a MOS integrated circuit will be described with reference to FIG. First, as shown in FIG. 3A, after forming an element isolation layer 302 on a Si substrate 301, a thermal oxide film 303 was formed. Next, a 200 nm-thick poly-Si layer 304 / WS
An i-layer 305 was formed by a CVD method, and a SiON inorganic antireflection film 306 was further formed on the film by a CVD method. The antireflection film pattern also serves as a hard mask, and enables pattern transfer to the underlying poly-Si film with little dimensional change.

Next, the SiON inorganic antireflection film 306 is used.
On top, acrylate-based resist 307 by spin coating,
Next, a polynorbornene-based resist 308 was formed to a thickness of 50 nm, respectively, and a resist film having a thickness of 100 nm was formed.

An ArF excimer laser exposure apparatus (NA = 0.60) was applied to the above substrate to reduce the size from 0.10 μm to 1 μm.
After exposing various patterns of μm, the pattern exposed portions were removed by predetermined heat treatment and wet development to form a pattern 309 (FIG. 3B).

As a result of observing the above pattern with a scanning electron microscope, it was confirmed that a resist pattern having a minimum dimension of 0.13 μm was formed for a laser irradiation amount of 21 mJ / cm ² . Further, when the Levenson-type phase shift mask was used, a pattern having a period of 200 nm and a size of 70 nm could be formed.

Next, the resist 30 is subjected to dry etching using an etching gas of C ₂ F ₆ + O ₂ + He.
The pattern of No. 9 was transferred to the SiON inorganic antireflection film 306. Further, using the above pattern as a mask, SF ₆ + C
A pattern 310 was formed by sequentially dry-etching the underlying WSi film 305 with an etching gas of l _{2 and} the dry etching of the poly-Si film 304 with an HBr + Cl ₂ + O ₂ etching gas. Here, when the resist remains on the SiON, it is preferable to perform an ashing step as needed. Thereafter, ion implantation and annealing were performed to form a source portion 311 and a drain portion 312 of the transistor (FIG. 3C).

According to the present embodiment, a fine gate pattern could be formed using a two-coat ArF exposure resist. The resist film had very few defects, so that a pattern could be formed with good yield.

In this embodiment, the resist for ArF exposure is used. However, the present invention is not limited to this embodiment as long as a photosensitive material capable of forming a thin film and having the same effect can be obtained. In the above description, the case of forming a film by the spin coating method has been described, but any method of forming a film may be used without departing from the spirit of the present invention. Needless to say, different film forming methods may be combined without departing from the spirit of the present invention.

Although chlorine gas was used as an etching gas, any gas used as an etching gas for polysilicon can be used without being restricted to this embodiment. For example, a fluorine-based gas may be used. Further, in the same manner as in the present embodiment, it is possible to process a polymetal silicon gate, a metal gate, or a Si oxide film, a Si nitride film, or the like which serves as a cap material for these gates.

The method of the present invention can be applied not only to the gate material but also to W (tungsten), various silicon oxide films, Cu
It can be applied to processing of (copper) and the like.

(Embodiment 5) An embodiment of a two-layer resist process with few defects in a resist film will be described with reference to FIG.

As shown in FIG. 4A, a coating film 40 made of a PVP-based material having a thickness of 400 nm is formed on a substrate to be processed on which a SiO ₂ processing film 402 having a thickness of 1 μm is formed on a wafer 401.
3 was formed by spin coating, and subjected to a thermal process at 200 ° C./120 seconds. Next, as shown in FIG. 4B, a positive chemically amplified Si-containing resist film 404 having a thickness of 50 nm was formed by spin coating.

When the defects of the film 404 were measured by a defect inspection apparatus, a total of 2 defects were measured for 25 8-inch wafers.
One defect was detected. Further, as shown in FIG. 4 (c), a Si-containing resist 405 is
Only nm was applied. When this was measured again by the defect inspection apparatus, no defect was found on 25 8-inch wafers.

As shown in FIG. 4D, the film was irradiated with F ₂ excimer laser light 406 to perform pattern exposure.
Here, the numerical aperture NA of the F ₂ excimer exposure apparatus is 0.6,
Although the coherency σ is set to 0.7, it is desirable to optimize both NA and σ according to the desired process latitude and resolution.

Next, as shown in FIG. 4 (e), the exposed portion was treated with a 2.38% aqueous solution of tetrahydromethylammonium for 6 hours.
After developing for 0 second, a pattern 407 was formed. After washing with water for 10 seconds, post-baking heat treatment was performed at 100 ° C. for 60 seconds.

Next, as shown in FIG.
The i-containing resist pattern 404 is formed by adding oxygen + SO ₂ + He
Dry development was performed using an etching gas, and the lower organic layer 403 was further etched to obtain a pattern 408. As a result, a two-layer resist pattern with extremely few defects could be obtained.

The pattern was transferred to the underlying SiO ₂ film 402 by dry etching using the pattern 408 to obtain a pattern 409 (FIG. 4G). Finally, as shown in FIG. 4H, the resist films 403, 404, 4
05 was peeled off by dry ashing and washed to obtain a desired pattern 410.

Here, when forming the resist pattern, an antireflection film may be formed on the lower layer or the upper layer. In the case of forming the pattern, it is desirable to use a resist whose adhesion, resolution, process latitude, and the like are optimized for the pattern to be formed.

(Embodiment 6) A method of manufacturing a MOS semiconductor device using the present invention will be described with reference to FIG. In addition,
The following description is to show the relation between the main steps of the MOS semiconductor device manufacturing process and the present invention, and does not describe all the manufacturing steps.

(1) Element Isolation Formation First, after forming a silicon oxide film 502 and a silicon nitride film 503 on a silicon substrate 504, an active layer of a MOS integrated circuit to be manufactured is manufactured by using a method substantially similar to that of the first embodiment. A resist pattern 501 was formed on the portion (FIG. 5A). Next, using this as a mask, the silicon nitride film 503, the Si oxide film 502, and the silicon substrate 504 are etched,
Silicon oxide 505 was embedded in the formed groove.
Next, a silicon nitride film is formed in a wide area portion of the above-mentioned groove portion by a usual method. Thereafter, the surface of the substrate is flattened by a CMP method, and the silicon nitride film is removed to form a so-called shallow groove isolation (SGI). A device isolation 505 was formed (FIG. 5b).

(2) Formation of Gate Next, after forming a predetermined well, forming a gate insulating film, forming a channel, etc., a gate multilayer of a polysilicon film 507, a TiN film 508, and a W film 509 is formed on the gate insulating film 506. A film was formed, and a silicon nitride film 510 and a silicon oxide film 511 were further laminated. A resist pattern 51 is formed on this laminated film by using a method substantially similar to that shown in the second embodiment.
2 was formed (FIG. 5C), the silicon nitride film and the silicon oxide film were etched using this as a mask, and the underlying gate film was further etched to form a gate pattern 513 (FIG. 5D).

(3) Formation of Contact Holes Next, after predetermined ion implantation regions 516, formation of LDD sidewalls 514, formation of salicide of source and drain portions, formation of an interlayer insulating film 520 of silicon oxide, flattening of the insulating film surface, A resist pattern 515 having openings in the contact hole portions was formed by using a method substantially similar to that shown in Example 1 (FIG. 5E), and the interlayer insulating film 520 was etched using this as a mask. After removing the resist pattern, a W plug 517 was buried and the surface was flattened to form a desired contact hole (FIG. 5).
f).

A MOS integrated circuit was manufactured using the above steps, and its operation was confirmed. MO manufactured according to this embodiment
The S integrated circuit has excellent uniformity in circuit dimensions and therefore has better performance than in the past, and the number of manufacturing steps is reduced as compared with the conventional manufacturing method, so that the manufacturing cost was also reduced.

Although not shown here, the pattern forming method according to the present invention uses other components of the MOS semiconductor device,
For example, it can be used for processing capacitors in DRAMs and ferroelectric memories.

Although the example in which the present invention is applied to the basic pattern of the MOS LSI has been described above, the present invention is not limited to this embodiment, and other processes of the LSI, and semiconductor devices of other types and materials, for example, bipolar LSIs and gallium arsenide The present invention can also be applied to an optoelectronic device such as a system semiconductor and a semiconductor laser. In that case, the material to be processed, the type of photosensitive material, the exposure method, the development method, the etching method, the gas, etc. are changed. It is desirable to optimize as long as the purpose is not deviated.

[0050]

As described above, according to the present invention, in a method for forming a fine pattern, a resist film having a thickness of 0.2 μm or less is formed on a substrate to be processed by performing film formation twice or more. Thus, a pattern forming method with a reduced defect density is provided. The defect density in the film can be reduced and excellent dimensional control can be performed, so that the performance of the LSI can be improved, the manufacturing yield can be improved, and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a process of the present invention.

FIG. 2 is a graph showing the operation and effect of the present invention.

FIG. 3 is a sectional view showing an embodiment in which the present invention is applied to gate processing.

FIG. 4 is a sectional view showing an embodiment in which the present invention is applied to a two-layer resist process.

FIG. 5 is a sectional view showing an embodiment in which the present invention is applied to the manufacture of a MOS type semiconductor device.

[Explanation of symbols]

101: resist film, 102: concave defect, 103: substrate,
104: second resist film, 301: Si substrate, 302
.., A gate insulating film, 304, a polysilicon layer, 305, a WSi layer, 306, a SiON antireflection film, 307, an acrylate resist, 308, a polynorbornene resist, 309, a resist pattern,
310: Work pattern, 311: MOS transistor source, 312: MOS transistor drain, 4
01 ... Si substrate, 402 ... SiO2 processed layer, 403 ...
PVP-based material, 404 ... Si-containing resist, 405 ... S
i-containing resist, 406 ... F2 excimer laser beam, 40
7: Si-containing resist pattern, 408: pattern after dry development, 409: processed part of SiO2, 410: desired SiO2 pattern, 501: resist pattern, 502
.., SiO2 layer, 503, silicon nitride film, 504, silicon substrate, 505, shallow trench isolation, 506, gate insulating film, 507, polysilicon film, 508, TiN film, 50
9 W film, 510 silicon oxide film, 511 silicon nitride film, 512 resist pattern, 513 gate pattern, 514 LDD sidewall, 515 resist pattern, 516 source and drain part, 517
W plug, 520: interlayer insulating film.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H096 AA25 BA01 BA09 CA14 CA17 EA05 EA23 2H097 AA03 BB10 CA13 FA10 LA10 5F046 CA03 CA04 JA04 JA20 NA01 NA06 NA09 NA19

Claims (8)

[Claims] 1. A step of forming a resist film having a total thickness of 0.3 μm or less on a substrate to be processed by two or more film formations, a step of selectively irradiating the film with energy rays, and a step of selectively irradiating the film with energy rays. A pattern forming method, comprising a step of removing the exposed portion or the unexposed portion. 2. The pattern forming method according to claim 1, wherein said resist film forming method is a spin coating or a chemical vapor deposition method. 3. The pattern forming method according to claim 1, wherein the resist films to be formed are made of different materials. 4. The pattern forming method according to claim 1, wherein said film forming method is different depending on the film. 5. The pattern forming method according to claim 1, wherein a wavelength of said energy ray is 200 nm or less. 6. The pattern forming method according to claim 1, wherein a wavelength of said energy ray is 173 nm or less. 7. A semiconductor manufacturing method using the pattern forming method according to any one of claims 1 to 6. 8. A semiconductor device manufactured by using the pattern forming method according to any one of claims 1 to 6.