TWI515589B - Semiconductor structure and method for fabricating semiconductor layout - Google Patents

Description

Semiconductor structure and method of fabricating semiconductor layout

The present invention relates to a semiconductor structure and a method of fabricating a semiconductor layout, and more particularly to a method and semiconductor structure for fabricating a semiconductor layout using a double patterning technique (DPT).

An integrated circuit (IC) is constructed by a device device and an interconnect structure formed by patterned features formed on a substrate or different film layers. In the production process of IC, photolithography process is an indispensable technology, which mainly forms the designed pattern, such as the layout pattern or circuit layout pattern, in one or more masks. The pattern on the reticle is then transferred to the photoresist layer on a film layer by an exposure and development step to accurately transfer the complex layout pattern onto the semiconductor wafer. Complicated IC structures can be completed with subsequent semiconductor fabrication processes such as ion implantation processes, etching processes, and deposition processes.

With the miniaturization of the semiconductor industry and the advancement of semiconductor fabrication technology, the exposure technology that is widely used as a technology has gradually approached its limits. Therefore, the double patterning technique (DPT), which can increase the minimum pattern distance (up to double) on the existing infrastructure, has almost become the most likely solution in the 32 nanometer (nm) and 22 nm linewidth technologies. method. Please refer to FIG. 1 , which is a schematic diagram of a decomposition method of a conventional double patterning technique. As shown in FIG. 1 , the double patterning technique mainly decomposes an original layout pattern 100 on two different masks, wherein one mask includes a layout pattern 102 and another mask includes a layout pattern. 104, and the layout pattern 102 and the layout pattern 104 are combined into the original layout pattern 100. In addition, when a complete and continuous original layout pattern is divided into the layout pattern 102 and the layout pattern 104 (as highlighted by the circle A in FIG. 1) due to the consideration of the minimum pattern distance, the continuous layout pattern is referred to as to be cut. To-be-split pattern.

Please refer to FIG. 2, which is a semiconductor layout structure fabricated by double patterning technology. It is worth noting that since double patterning technology must undergo multiple exposure steps, overlay control and alignment have always been the concerns of double patterning techniques, and the problem of overlap control and alignment It is further highlighted when the pattern to be cut is broken down into two split patterns. When the double patterning technique has an overlay error or an inaccurate alignment, it is possible that the cut patterns that should be connected are not connected after the double patterning technique. In addition, the line-end shortening phenomenon that often occurs in the lithography process may also result in a broken line as shown by the circle B in Fig. 2, and the cut pattern is not connected. Open circuit problem.

Therefore, the industry still needs a method and a semiconductor layout structure for fabricating a semiconductor layout pattern that can overcome the above problems.

Accordingly, the present invention provides a semiconductor structure and a method of fabricating a semiconductor layout for solving problems such as disconnection occurring in a double patterning technique.

According to the scope of the invention provided by the present invention, there is provided a semiconductor structure including a wiring pattern including at least a first line segment and a second line segment, and at least a portion of the first line segment and A portion of the second line segment is spliced to each other within a splicing region. The semiconductor structure further includes a connection pattern disposed in the splicing region and electrically connecting the first line segment and the second line segment.

According to the patent application scope provided by the present invention, there is further provided a method for fabricating a semiconductor layout, the method first providing a first layout and a second layout, the first layout comprising a plurality of wiring patterns, and the second layout comprising There are a plurality of connection patterns. Next, at least one first pattern to be cut is defined in the wiring patterns of the first layout, and the first patterns to be cut overlap with the connection patterns, respectively. After the first pattern to be cut is defined, the first pattern to be cut is sliced at an overlap of the first pattern to be cut and one of the connection patterns to decompose the first layer to form a third layout. And a fourth layout, and outputting the third layout and the fourth layout to a first photomask and a second photomask, respectively.

According to the patent application scope provided by the present invention, there is further provided a method for fabricating a semiconductor layout, the method first providing a first layout, the first layout comprising a plurality of wiring patterns, and then defining a plurality of wiring patterns in the wiring patterns The pattern to be cut. Next, a second layout is provided, the second layout includes a plurality of first connection patterns, and then a plurality of second connection patterns are added to the second layout, and the second connection patterns are respectively associated with the waiting cutting pattern Overlap, finally outputting the second layout to a first mask.

According to the patent application scope provided by the present invention, there is further provided a method for fabricating a semiconductor structure, the method first providing a first original layout and a second original layout, the first original layout comprising a plurality of wiring patterns, the second The original layout contains a number of connection patterns. Next, a plurality of patterns to be cut are defined in the first original layout, and the waiting cutting patterns respectively overlap the connected patterns. After the waiting for the cutting pattern is defined, the first original layout is decomposed, and the wiring pattern and the waiting cutting pattern are respectively formed in a first decomposition layout and a second decomposition layout, and then the first decomposition layout is And the second decomposition layout is formed on a first photomask and a second photomask, respectively. After the first reticle and the second reticle are to be formed, a double patterning technique is performed to sequentially transfer the first decomposition layout and the second decomposition layout to a film layer, and the film layer includes the film layer The wiring pattern and the waiting cutting pattern.

According to the method of fabricating a semiconductor layout provided by the present invention, the first original layout including the wiring patterns and the second original layout including the connection patterns are respectively provided. Next, a wiring pattern overlapping the the connection patterns in the first original layout is defined as the waiting cutting pattern. Alternatively, in the second original layout, a connection pattern is provided relative to the waiting cutting pattern. It can be seen that in the first original layout, all the patterns to be cut correspond to a connection pattern. Therefore, when the first original layout is decomposed into the first decomposition layout and the second decomposition layout, and respectively transferred to a certain film layer by double patterning technology, the pattern to be cut, especially the pattern to be cut At the same time, a subsequent pattern will be formed. Therefore, even if the pattern to be cut which is decomposed in the double patterning technique has defects such as disconnection due to an incorrect alignment problem or a problem of end-of-line shrinkage, the defect can be removed by the formation of the connection pattern to ensure subsequent formation. The reliability of the semiconductor structure. Briefly stated, the present invention provides a method of designing and fabricating a semiconductor layout, which can effectively solve the problem of disconnection inherent in the double patterning technique without increasing the complexity of the process.

Please refer to FIG. 3 to FIG. 11 . FIG. 3 to FIG. 11 are schematic diagrams showing a first preferred embodiment of the method for fabricating a semiconductor layout provided by the present invention. As shown in FIG. 3, a first original layout 200 is provided. In the preferred embodiment, the first original layout 200 is a trench layout of a metal interconnect, and includes a plurality of wiring patterns 202 such as a trench pattern. But it is not limited to this. The wiring pattern 202 of the preferred embodiment may also be a polysilicon line.

It should be noted that when any of the wiring patterns 202 in the first original layout 200 and the adjacent at least two wiring patterns 202 violate a predetermined rule, for example, less than a minimum design rule (minimum design rule) In this case, it is conceivable to decompose the wiring patterns 202 by a double patterning technique. However, when the at least three wiring patterns 202 are respectively defined into two different decomposition masks by using a double patterning technique, and the problem of violating predetermined rules is still not solved, the preferred embodiment will One is defined as a pattern to be cut 204a. In other words, at least one pattern to be cut 204a is defined in the wiring pattern 202 of the first original layout 200, and the distance between the pattern 204a to be cut and the other wiring patterns 202 is in violation of the predetermined rule described above.

Please refer to Figure 4. Next, a second original layout 210 is provided, the second original layout 210 comprising a plurality of connection patterns 212a. In the preferred embodiment, the second original layout 210 may be a metal interconnect layer layout, a dummy via layout or a contact layout, but is not limited thereto. And the target film layer to be formed by the second original layout 210 and the target film layer to be formed by the first original layout 200 are layers stacked on top of each other. It should be noted that, in order to show the relative relationship between the second original layout 210 and the first original layout 200, in the fourth figure, the first original layout 200 is indicated by a dotted line, but those skilled in the art should know that The two original layouts 210 only include the connection patterns 212a shown by the solid lines.

Please refer to Figure 5. Next, the first original layout 200 and the second original layout 210 are compared, and the first original layout 200 is started to be decomposed at the same time. In detail, the adjacent two wiring patterns 202 in the first original layout 200 that violate the rule are first divided into a plurality of first wiring patterns 202a and a plurality of second wiring patterns 202b such that the first wiring patterns 202a are between each other. The distance is in accordance with the predetermined rule described above, and the same reason is that the distance between the second wiring patterns 202b is in accordance with the predetermined rule described above. Since the preferred embodiment is used for the double patterning technique, the first wiring pattern 202a and the second wiring pattern 202b are decomposed and subsequently formed on different reticle, wherein the reticle includes the first wiring pattern. 202a, another photomask includes a second wiring pattern 202b. Further, the pattern to be cut 204a is divided into a cut portion 206a and a counter portion cut portion 206b. The cutting portion 206a may be formed on the same mask as the first wiring pattern 202a; and the corresponding cutting portion 206b may be formed on the other mask simultaneously with the second wiring pattern 202b.

It should be noted that the preferred embodiment compares the first original layout 200 with the second original layout 210, when the wiring pattern 202 in the first original layout 200 overlaps with the connection pattern 212a in the second original layout 210. That is, the wiring pattern is further defined as a pattern to be cut 204b. In other words, the preferred embodiment defines at least one pattern to be cut 204b in the wiring pattern 202 in the first original layout 200, and the pattern to be cut 204b overlaps the connection pattern 212a. In addition, the preferred embodiment further divides the pattern to be cut 204b while cutting the pattern 204a to be cut, and divides the pattern to be cut 204b at the overlap of the pattern 204b to be cut and the connection pattern 212a, and is to be cut. The pattern 204b is diced to form a cut portion 206a and a corresponding cut portion 206b.

Please also refer to Figures 6 and 7. Next, the first original layout 200 is decomposed, and the pattern to be cut 204a and the pattern to be cut 204b are cut. The first wiring pattern 202a, the cut portion 206a of the pattern to be cut 204a, and the cut portion 206a of the pattern 204b to be cut are defined as a first exploded layout 220. At the same time, the second wiring pattern 202b, the corresponding cutting portion 206b of the pattern to be cut 204a, and the corresponding cutting portion 206b of the pattern 204b to be cut are defined as a second decomposition layout 230. It is to be noted that, in the first decomposition layout 220, the first wiring pattern 202a, the cutting portion 206a of the pattern to be cut 204a, and the cutting portion 206a of the pattern 204b to be cut are spaced apart from each other, and all conform to the aforementioned predetermined rule. Similarly, in the second decomposition layout 230, the second wiring pattern 202b, the corresponding cutting portion 206b of the pattern to be cut 204a, and the corresponding cutting portion 206b of the pattern 204b to be cut are spaced apart from each other, and all conform to the aforementioned predetermined rules. In addition, after forming the first decomposition layout 220 and the second decomposition layout 230, an optical proximity correction (OPC) method may be performed on the first decomposition layout 220 and the second decomposition layout 230, respectively.

It should be noted that the preferred embodiment further provides a correction step after forming the first decomposition layout 220 and the second decomposition layout 230. This correction step is specifically made for each of the first and second decomposed layouts 220, 230 and 230, and each of the corresponding cut portions 206b. In detail, the correcting step extends or enlarges each of the cutting portions 206a in the first disassembling layout 220 in a direction directed to the corresponding cutting portion 206b; meanwhile, the correcting step is also extended or added in a direction directed to the cutting portion 206a. Each of the corresponding cut portions 206b in the second second decomposition layout 230 forms a stitch pattern. By this modification step, the overlapping range of the cutting portion 206a and the corresponding cutting portion 206b can be increased, thereby reducing the cutting portion 206a and the corresponding cutting portion 206b due to inaccurate alignment or end-of-line shortening in the subsequent double patterning technique. There is no chance of being connected.

Please refer to Figure 8 and Figure 9. After the above steps are completed, the first decomposition layout 220 is formed on a first mask 222 (shown in FIG. 8), and the second decomposition layout 230 is output on a second mask 232 (shown in Figure 9). Next, using the first mask 222 and the second mask 232, a double patterning technique can be performed on a predetermined film layer. In detail, the preferred embodiment provides a substrate 300. The substrate 300 includes a conductive layer 302, and the conductive layer 302 and the substrate 300 form a bottom layer 304. In the preferred embodiment, the bottom layer 304 may include silicon carbon nitride (SiCN), but is not limited thereto. A dielectric layer 306 is formed on the bottom layer 304. In the preferred embodiment, the dielectric layer 306 may comprise an ultra low-k (ULK) material, but is not limited thereto. A cover layer 308, a composite metal hard mask 310, a bottom anti-reflective coating (hereinafter referred to as BARC) 312, and a photoresist layer 314 are sequentially formed on the dielectric layer 306.

Please continue to see Figure 8. Next, the first mask 222 and the second mask 232 are used to perform a double patterning technique: first, the first decomposition layout 220 on the first mask 222 is transferred into the photoresist layer 314 to form at least one An opening 316a. First of all, since the double patterning technique is performed by the double exposure primary development (2P1D) method in the preferred embodiment, when the first decomposition layout 220 is transferred to the photoresist layer 314, it is formed as the eighth. As shown, the first opening 316a is shown in dashed lines. Please refer to Figure 9. Next, the second decomposition layout 230 on the second mask 232 is transferred into the photoresist layer 314 to form at least one second opening 316b. It should be noted that in the double patterning technique, the first opening 316a and the second opening 316b formed by the cutting portion 206a of the pattern to be cut 204a/204b and the corresponding cutting portion 206b after the transfer pattern are often inaccurate due to the alignment. If the problem is not connected, as shown in FIG. 9, a residue 318 including the photoresist layer 314, the BARC 312, the metal hard mask 310, and the cover layer 308 is formed in the first opening 316a and the second opening 316b. In addition, those skilled in the art should be aware that the preferred embodiment can also use the second exposure secondary development (2P2D) method to include the first decomposition layout 220 and the second mask 232 included in the first mask 222. The included second decomposition layout 230 is transferred into the photoresist layer 314.

Please refer to Figure 10. Subsequently, an etching process of the double patterning technique is performed to transfer the opening 316a and the opening 316b included in the photoresist 314, that is, the first decomposition layout 220 and the second decomposition layout 230 to the composite metal hard mask 310 and the cover layer. In 308, a trench opening 320a is formed, and then the photoresist layer 314 and the BARC 312 are removed. It will be appreciated by those skilled in the art that after the double patterning technique is completed, each of the wiring patterns 202 and the patterns to be cut 204a/204b of the first original layout 200 are formed in the composite metal hard mask 310 and the cover layer 308. It should be noted that since the opening 316a and the opening 316b have a residue 318, the residue 320b is also formed in the trench opening 320a formed in the composite metal hard mask 310 and the cover layer 308. It is also worth noting that in the preferred embodiment, the double patterning technique is a 2P1E mode of a single photoresist layer or a double photoresist layer of a litho-litho-etch, but is not limited thereto. A 2P2E mode using a dual photoresist layer of a litho-etch-litho-etch. When the double patterning technique adopts the 2P2E mode, in addition to the alignment problem, it is more likely that the defect of the residue 320b is more serious due to the end-of-line shrinkage problem occurring in the two etching steps.

Please continue to see Figure 10. Next, a BARC 322 and a photoresist layer 324 are formed on the metal hard mask 310 and the opening 320a and the residue 320b. And performing a development process of a patterning process again by using a third mask 330 including the second original layout 210, and transferring the connection pattern 212a of the second original layout 210 into the photoresist layer 324 to form a third opening. 332. The third opening 332 can be a contact hole opening or a via opening. Additionally, the step of transferring the second original layout 210 can be performed before or after the double patterning technique described above.

Please refer to Figure 11. Next, an etching process of a patterning process is performed to etch the BARC 322, the metal hard mask 310, the capping layer 308, and the dielectric layer 306 from the third opening 332 in the photoresist layer 324 until the bottom layer 304 is exposed. Thereafter, the photoresist layer 324 and the BARC 322 are removed. In other words, the second original layout 210 is transferred into the dielectric layer 306. Additionally, in a variation of the preferred embodiment, the transfer of the second original layout 210 can also be performed by a dual patterning technique.

It is to be noted that, since the first decomposition layout 220 and the second decomposition layout 230 are defined, the wiring pattern at which the connection pattern 212a overlaps is defined as the pattern to be cut 204b, and the first decomposition layout 220 and the second decomposition are decomposed. In the layout 230, the cutting portion 206a and the corresponding cutting portion 206b are formed by dividing the pattern to be cut 204b by the connection pattern 212a and the pattern 204b to be cut. Therefore, when the cutting portion 206a and the corresponding cutting portion 206b are transferred to the metal hard mask 310 and the cover layer 308, such as inaccurate alignment and end-of-line shortening, the residue 320b is formed on the cutting portion 206a as described above. The cutting portion 206b is bordered. More importantly, since the cut portion 206a corresponds to the corresponding cut portion 206b and overlaps the connection pattern 212a, the residue 320b can be completely removed when the connection pattern 212a is transferred to the dielectric layer 306. In other words, the cut portion 206a and the corresponding cut portion 206b can be completely connected after the connection pattern 212a is formed, so that the etching incomplete due to the residue 320b and the problem of disconnection can be completely eliminated.

According to the method of fabricating the semiconductor layout provided by the first preferred embodiment, the wiring pattern 202 in the first original layout 200 overlapping the connection pattern 212a in the second original layout 210 is defined as the pattern to be cut 204b. In other words, in the first original layout 200, all of the patterns to be cut 204b correspond to a connection pattern 212a. Therefore, when the first original layout 200 is decomposed into the first decomposition layout 220 and the second decomposition layout 230, and respectively transferred to the target film layer by the double patterning technique, where the pattern to be cut 204b is to be cut, especially to be cut The division of the pattern 204b (where the cutting portion 206a borders the corresponding cutting portion 206b) will subsequently form a connection pattern 212a. Therefore, even in the double patterning technique, the defect of the cut portion 206a and the corresponding cut portion 206b due to an incorrect alignment problem or a problem of line end shrinkage can be removed by the formation of the connection pattern 212a.

Next, please refer to FIG. 3 and FIG. 6 to FIG. 12 . FIG. 3 and FIG. 6 to FIG. 12 are schematic diagrams showing a second preferred embodiment of the method for fabricating a semiconductor layout provided by the present invention. It should be noted that in the second preferred embodiment, the same components as those in the first preferred embodiment are denoted by the same reference numerals, and the related descriptions may be referred to the disclosure of the first preferred embodiment. Therefore, this is not repeated here.

As shown in FIG. 3, the preferred embodiment first provides a first original layout 200. In the preferred embodiment, the first original layout 200 is also a metal interconnect trench layout, which includes a plurality of trench layouts. The wiring pattern 202 is not limited thereto. The first original layout included in the preferred embodiment may also be a polysilicon line. As described above, when any of the wiring patterns 202 in the first original layout 200 and the adjacent at least two wiring patterns violate a predetermined rule, for example, less than a minimum design rule, it is considered to utilize the double patterning technique. The wiring patterns 202 are resolved. However, when the at least three wiring patterns 202 are respectively defined into two different decomposition masks by using a double patterning technique, and the problem of violating predetermined rules is still not solved, the preferred embodiment will One is defined as a pattern to be cut 204a. In other words, at least one pattern to be cut 204a is defined in the wiring pattern 202 of the first original layout 200, and the distance between the pattern 204a to be cut and the other wiring patterns 202 is in violation of the predetermined rule described above.

Please refer to Figure 12. Next, a second original layout 210 is provided, the second original layout 210 comprising a plurality of connection patterns 212a. In the preferred embodiment, the second original layout 210 may be a metal interconnect layer layout, a dummy via layout or a contact layout, but is not limited thereto. And the target film layer to be formed by the second original layout 210 and the target film layer to be formed by the first original layout 200 are layers stacked on top of each other. It should be noted that, in order to show the relative relationship between the second original layout 210 and the first original layout 200, in the 12th figure, the first original layout 200 is also indicated by a dotted line, but those skilled in the art should know the second The original layout 210 includes only the connection pattern 212a shown by the solid line.

Please refer to Figure 5 and Figure 12. Next, the first original layout 200 and the second original layout 210 are compared, and the first original layout 200 is started to be decomposed at the same time. In detail, the adjacent two wiring patterns 202 in the first original layout 200 that violate the rule are first divided into a plurality of first wiring patterns 202a and a plurality of second wiring patterns 202b such that the first wiring patterns 202a are between each other. The distance is in accordance with the predetermined rule described above, and the same reason is that the distance between the second wiring patterns 202b is in accordance with the predetermined rule described above. Since the preferred embodiment is used for the double patterning technique, the first wiring pattern 202a and the second wiring pattern 202b can be formed on two different masks, wherein the mask includes the first wiring pattern 202a. The other photomask includes the second wiring pattern 202b. Further, the pattern to be cut 204a is divided into a cut portion 206a and a corresponding cut portion 206b. The cutting portion 206a may be formed on the same mask as the first wiring pattern 202a; and the corresponding cutting portion 206b may be formed on the other mask simultaneously with the second wiring pattern 202b.

It is to be noted that, when the cut portion 206a of the pattern to be cut 204a and the corresponding cut portion 206b are defined, the preferred embodiment further provides a connection pattern 212b, and the connection pattern 212b is tied to the pattern 204a to be cut, especially The cut portion 206a of the cut pattern 204a overlaps with the corresponding cut portion 206b. In the preferred embodiment, the connection pattern 212b is inserted into the second original layout 210, but the preferred embodiment is not limited to providing another third original layout (not shown), and the third original layout That is, the connection pattern 212b is included. In addition, in the preferred embodiment, as described in the first preferred embodiment, when the first original layout 200 and the second original layout 210 are aligned, when the wiring pattern 202 in the first original layout 200 is When the connection patterns 212a in the second original layout 210 are overlapped, the wiring pattern is otherwise defined as a pattern to be cut 204b.

Please refer back to Figures 6 and 7 at the same time. Next, the first original layout 200 is decomposed, and the pattern to be cut 204a and the pattern to be cut 204b are cut. The first wiring pattern 202a, the cut portion 206a of the pattern to be cut 204a, and the cut portion 206a of the pattern 204b to be cut are defined as a first exploded layout 220. At the same time, the second wiring pattern 202b, the corresponding cutting portion 206b of the pattern to be cut 204a, and the corresponding cutting portion 206b of the pattern 204b to be cut are defined as a second decomposition layout 230. It is to be noted that, in the first decomposition layout 220, the first wiring pattern 202a, the cutting portion 206a of the pattern to be cut 204a, and the cutting portion 206a of the pattern 204b to be cut are spaced apart from each other, and all conform to the aforementioned predetermined rule. Similarly, in the second decomposition layout 230, the second wiring pattern 202b, the corresponding cutting portion 206b of the pattern to be cut 204a, and the corresponding cutting portion 206b of the pattern 204b to be cut are spaced apart from each other, and all conform to the aforementioned predetermined rules. In addition, after forming the first decomposition layout 220 and the second decomposition layout 230, an optical proximity correction method may be performed on the first decomposition layout 220 and the second decomposition layout 230, respectively.

In addition, the preferred embodiment also provides a correction step after forming the first decomposition layout 220 and the second decomposition layout 230. This correction step is specifically made for each of the first and second decomposed layouts 220, 230 and 230, and each of the corresponding cut portions 206b. In detail, the correcting step extends or enlarges each of the cutting portions 206a in the first disassembling layout 220 in a direction directed to the corresponding cutting portion 206b; meanwhile, the correcting step is also extended or added in a direction directed to the cutting portion 206a. The respective second cutting portions 206b of the second decomposition layout 230 form a stitching pattern. By this modification step, the overlapping range of the cutting portion 206a and the corresponding cutting portion 206b can be increased, thereby reducing the cutting portion 206a and the corresponding cutting portion 206b due to inaccurate alignment or end-of-line shortening in the subsequent double patterning technique. There is no chance of being connected.

Please refer back to Figures 8 to 10. After the above steps are completed, the preferred embodiment can form the output of the first decomposition layout 220 on a first mask 222 (shown in FIG. 8), and output the second decomposition layout 230 in a second. Photomask 232 (shown on Figure 9). Next, using the first mask 222 and the second mask 232, a double patterning technique can be performed on a predetermined film layer. For example, as shown in FIG. 8 and FIG. 9, the first decomposition layout 220 on the first mask 222 and the second decomposition layout 230 on the second mask 232 can be transferred to the photoresist layer 314, respectively. A first opening 316a and a second opening 316b are formed. As described above, in the double patterning technique, the cut portion 206a of the pattern to be cut 204a/204b and the first opening 316a and the second opening 316b formed by the corresponding cut portion 206b after the transfer pattern are often likely to be aligned. Residues 318 are formed by inaccuracies and the like. The residue 318 is transferred into the composite metal hard mask 310 and the cover layer 308 after the etching process of the double patterning technique to form the residue 320b as shown in FIG.

Please refer to Figure 10 and Figure 11. Next, a BARC 322 and a photoresist layer 324 are formed on the metal hard mask 310 and the trench opening 320a and the residue 320b. And performing a development process of a patterning process again by using the third mask 330 including the second original layout 210, and transferring the connection pattern 212a and the connection pattern 212b of the second original layout 210 into the photoresist layer 324 to form At least one third opening 332. Next, an etching process of a patterning process is performed to transfer the second original layout 210 into the dielectric layer 306 to form a third opening 332.

It is to be noted that, since the second original layout 210 is formed, the pattern to be cut 204a corresponding to the first original layout 200 is provided, especially the portion of the cutting portion 206a overlapping the pattern to be cut 204a and the corresponding cutting portion 206b. The pattern 212b is connected. Therefore, when the cutting portion 206a and the corresponding cutting portion 206b are transferred to the metal hard mask 310 and the cover layer 3208, alignment inaccuracy and end line shortening occur, resulting in the residue 320b being formed on the cutting portion 206a and the corresponding cutting portion as described above. When the 206b is bordered, the residue 320b can be completely removed by the transfer pattern 212b corresponding to and overlapping with the cut portion 206a and the corresponding cut portion 206b. In other words, the cut portion 206a and the corresponding cut portion 206b can be completely connected after the formation of the connection pattern 212b, and the subsequent etching due to the residue 320b is incomplete and the problem of disconnection can be completely eliminated.

According to the method for fabricating a semiconductor layout provided by the second preferred embodiment, the pattern to be cut 204a corresponding to the first original layout 200, especially the portion of the cutting portion 206a overlapping the pattern to be cut 204a and the corresponding cutting portion 206b A connection pattern 212b is provided, and the connection pattern 212b can be inserted in the second original layout 210 or formed in a third original layout. Therefore, in the first original layout 200, all of the patterns to be cut 204a correspond to a connection pattern 212b. Therefore, when the first original layout 200 is decomposed into the first decomposition layout 220 and the second decomposition layout 230, and respectively transferred to a certain film layer by the double patterning technique, at the pattern to be cut 204a, especially The division of the cutting pattern 204a (where the cutting portion 206a is bordered by the corresponding cutting portion 206b) will subsequently form a line pattern 212b. Therefore, even in the double patterning technique, the defect of the cut portion 206a and the corresponding cut portion 206b due to the problem of misalignment or the problem of the end of the line is broken, the defect can be removed by the formation of the connection pattern 212b.

Finally, please refer to FIG. 13 and FIG. 14 . FIG. 13 and FIG. 14 are diagrams showing a method for fabricating a semiconductor layout according to a first preferred embodiment or/and a second preferred embodiment provided by the present invention. A schematic of a semiconductor structure formed. As shown in FIG. 13, a semiconductor structure 400 formed by the first preferred embodiment or/and the second preferred embodiment of the present invention is formed on the substrate 300, and the semiconductor structure 400 is formed. The wiring pattern 402 includes a plurality of wiring patterns 402 formed by forming a first decomposition layout 220 and a second decomposition layout 230 on the substrate 300 by a double patterning technique, so that the wiring pattern 402 is first The original layout 200 provides the same wiring pattern 202, which may include a metal interconnect trench pattern, but is not limited thereto. It should be noted that the wiring pattern 402 may be a complete pattern or may be composed of different patterns. Therefore, in the semiconductor structure 400 provided by the present invention, a portion of the wiring pattern 402 includes at least a first line segment 402a and a second line segment 402b, and the first line segment 402a and the second line segment 402b are equal to the first original layout. The cut portion 206a of the pattern to be cut 204a/204b in 200 and the corresponding cut portion 206b. The first line segment 402a and the second line segment 402b are connected to each other in a splicing area 404 (indicated by circle 404). Further, as described above, since the wiring pattern 402 formed by the first line segment 402a and the second line segment 402b is transferred from the first original layout 200, the first line segment 402a and the second line segment 402b are coplanar.

In addition, the first line segment 402a and the second line segment 402b may be arranged in an aligned manner as shown in FIG. 13, and as shown in FIG. 13, the first line segment 402a and the second line segment 402b form a one-line shape. Or a T-shaped shape. In addition, the first line segment 402a and the second line segment 402 may also be arranged in a non-aligned manner as shown in FIG. 14, and may further form an L-shaped shape.

Please continue to see Figure 13. The semiconductor structure 400 formed by the first preferred embodiment of the present invention or the method provided by the second preferred embodiment further includes a connection pattern 406 disposed in the splicing region 404 and electrically The first line segment 402a and the second line segment 402b are connected. It should be noted that the connection pattern 406 is disposed on the first line segment 402a and the second line segment 402b, and above or below the other wiring patterns 402, that is, the connection pattern 406 and the first line segment 402a and the second line segment 402b. The wiring patterns 402 are not coplanar. As described above, the connection pattern 406 is formed by forming a second original layout 210 on the substrate 300 by a patterning process, so that the connection pattern 406 is connected to the wiring pattern 212a provided by the second original layout 210. Similarly to 212b, it may include a via pattern of a metal interconnect of a metal interconnect, a dummy via pattern or a contact hole pattern, but is not limited thereto.

The semiconductor structure 400 formed by the first preferred embodiment or/the second preferred embodiment provided by the present invention has a wiring pattern 402 composed of a first line segment 402a and a second line segment 402b. A connection pattern for electrically connecting the first line segment 402a and the second line segment 402b must be formed above or below it. Therefore, even when the first line segment 402a and the second line segment 402b are formed, that is, when the double patterning technique is performed, the first line segment 402a and the second line segment 402b are broken due to the problem of incorrect alignment or end-of-line shrinkage. The defects can still be removed by the formation of the connection pattern 406, so that the semiconductor structure 400 provided by the present invention is more reliable.

In summary, the method for fabricating a semiconductor layout according to the present invention provides the first original layout including the wiring patterns and the second original layout including the connection patterns, respectively. Next, a wiring pattern overlapping the the connection patterns in the first original layout is defined as the waiting cutting pattern. Alternatively, a connection pattern may be provided relative to the waiting cutting pattern in the second original layout or even another layout. It can be seen that in the first original layout, all the patterns to be cut correspond to a connection pattern. Therefore, when the first original layout is decomposed into the first decomposition layout and the second decomposition layout, and respectively transferred to a certain film layer by double patterning technology, the pattern to be cut, especially the pattern to be cut At the same time, a subsequent pattern will be formed. Therefore, even in the double patterning technique, if the pattern to be cut is defective due to an incorrect alignment problem or a problem of wire breakage, the defect can be removed by the formation of the connection pattern to ensure the subsequently formed semiconductor structure. Reliability. Briefly stated, the present invention provides a method of designing and fabricating a semiconductor layout, which can effectively solve the problem of disconnection inherent in the double patterning technique without increasing the complexity of the process.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100. . . Original layout pattern

102. . . Layout pattern

104. . . Layout pattern

200. . . First original layout

202. . . Wiring pattern

202a. . . First wiring pattern

202b. . . Second wiring pattern

204a. . . Pattern to be cut

204b. . . Pattern to be cut

206a. . . Cutting part

206b. . . Corresponding cutting part

210. . . Second original layout

212a. . . Connection pattern

212b. . . Connection pattern

220. . . First decomposition layout

230. . . Second decomposition layout

222. . . First mask

232. . . Second mask

300. . . Base

302‧‧‧ Conductive layer

304‧‧‧ bottom layer

306‧‧‧Dielectric layer

308‧‧‧ Coverage

310‧‧‧Composite metal hard mask

312‧‧‧Anti-reflective bottom layer

314‧‧‧ photoresist layer

316a‧‧‧first opening

316b‧‧‧ second opening

318‧‧‧Residues

320a‧‧‧ Ditch opening

320b‧‧‧Residues

322‧‧‧Anti-reflective bottom layer

324‧‧‧ photoresist layer

330‧‧‧ third mask

332‧‧‧ third opening

400‧‧‧Semiconductor structure

402‧‧‧Wiring pattern

402a‧‧‧First line

402b‧‧‧second line

404‧‧‧Connected area

406‧‧‧Connection pattern

A, B‧‧ Circle

Figure 1 is a schematic diagram of a decomposition method of a conventional double patterning technique.

Figure 2 is a semiconductor layout structure fabricated using a double patterning technique.

Please refer to FIG. 3 to FIG. 11 . FIG. 3 to FIG. 11 are schematic diagrams showing a first preferred embodiment of the method for fabricating a semiconductor layout provided by the present invention.

3 and 6 to 12 are schematic views of a second preferred embodiment of the method of fabricating a semiconductor layout provided by the present invention.

Figures 13 and 14 are semiconductor structures formed in accordance with a first preferred embodiment of the present invention or/and a second preferred embodiment of the method of fabricating a semiconductor layout.

200. . . First original layout

202a. . . First wiring pattern

202b. . . Second wiring pattern

204a. . . Pattern to be cut

204b. . . Pattern to be cut

206a. . . Cutting part

206b. . . Corresponding cutting part

Claims (38)

A semiconductor structure includes: a wiring pattern including at least a first line segment and a second line segment, the first line segment and the second line segment being parallel to each other, and at least a portion of the first line segment and a portion of the second line segment is connected to each other in a splicing region, the first line segment includes a first line width, and the second line segment includes a second line width; and a connection pattern is disposed on the splicing And electrically connecting the first line segment and the second line segment, wherein the first line segment and the second line segment adjacent to each other comprise a third line width, and the third line width is greater than the first line width and The second line is wide. The semiconductor structure of claim 1, wherein the first line segment and the second line segment are arranged in an aligned or non-aligned manner. The semiconductor structure of claim 1, wherein the first line segment and the second line segment form an in-line shape, a T-shape, or an L-shape. The semiconductor structure of claim 1, wherein the first line segment and the second line segment are coplanar. The semiconductor structure of claim 1, wherein the connection The pattern is disposed above or below the first line segment and the second line segment. The semiconductor structure of claim 1, wherein the wiring pattern comprises a trench pattern of metal interconnects. The semiconductor structure of claim 1, wherein the connection pattern comprises a via of a metal interconnect, a dummy via pattern or a contact hole pattern. A method for fabricating a semiconductor layout, comprising: providing a first layout, the first layout comprising a plurality of wiring patterns; providing a second layout, the second layout comprising a plurality of connection patterns; At least one first to-be-split pattern is defined in the wiring patterns, and the first to-be-cut patterns are respectively overlapped with the connection patterns; and the first to-be-cut pattern and one of the connection patterns are Splitting the first to-be-cut pattern to form a third layout and a fourth layout; and outputting the third layout and the fourth layout to a first mask and a first On the two masks. The method of claim 8, further comprising defining at least one second pattern to be cut in the wiring patterns of the first layout, and the The distance between the second pattern to be cut and the wiring patterns violates a predetermined rule. The method of claim 9, further comprising dividing the second pattern to be cut while cutting the first pattern to be cut, to decompose the first layout to form the third layout and the first Four layouts. The method of claim 10, wherein the third layout and the fourth layout respectively comprise a portion of the wiring pattern and a portion of the second pattern to be cut, and the wiring patterns and the second to be cut The spacing between the patterns conforms to the predetermined rule. The method of claim 8, wherein the first patterns to be cut are respectively divided into a cutting portion and a counterpart portion, the third layout including the cutting portions, and the cutting portion The fourth layout includes the corresponding cut portions. The method of claim 12, further comprising performing a modification step on the third layout and the fourth layout after forming the third layout and the fourth layout to point to one of the corresponding cutting portions The direction extends the cut portions of the third layout and extends the corresponding cut portions of the fourth layout in a direction directed to one of the cut portions. The method of claim 8, further comprising performing an optical proximity correction method on the third layout and the fourth layout after forming the third layout and the fourth layout. The method of claim 8, wherein the first layout comprises a trench layout of metal interconnects. The method of claim 8, wherein the second layout comprises a via layout of a metal interconnect, a dummy via layout, or a contact layout. A method for fabricating a semiconductor layout, comprising: providing a first layout, the first layout comprising a plurality of wiring patterns; defining a plurality of patterns to be cut in the wiring patterns; providing a second layout, the second The layout includes a plurality of first connection patterns; a plurality of second connection patterns are added to the second layout, and the second connection patterns are respectively overlapped with the cutting patterns; and the second layout is outputted to a first On the mask. The method of claim 17, wherein the waiting for the cutting pattern and the wiring pattern are in violation of a predetermined rule. The method of claim 18, further comprising the step of performing the waiting for the cutting pattern to divide the waiting cutting pattern to form a third layout and a fourth layout. The method of claim 19, wherein the third layout and the fourth layout respectively comprise a portion of the wiring patterns, and the distance between the wiring patterns conforms to the predetermined rule. The method of claim 19, wherein the waiting cutting patterns are respectively divided into a cutting portion and a corresponding cutting portion, the third layout including the cutting portions, and the fourth layout includes the cutting portions Corresponding to the cutting part. The method of claim 21, further comprising performing a correcting step on the third layout and the fourth layout after forming the third layout and the fourth layout to point to one of the corresponding cutting portions The direction extends the cut portions of the third layout and extends the corresponding cut portions of the fourth layout in a direction directed to one of the cut portions. The method of claim 22, wherein the modifying method is performed after forming the third layout and the fourth layout or after forming the second connection patterns. The method of claim 19, further comprising performing an optical proximity correction method on the third layout and the fourth layout, respectively. The method of claim 24, wherein the optical proximity correction method is performed after forming the third layout and the fourth layout or after forming the second connection patterns. The method of claim 17, wherein the wiring patterns of the first layout comprise trench patterns of metal interconnects. The method of claim 17, wherein the first connection patterns of the second layout comprise via holes or contact hole patterns of metal interconnects. The method of claim 17, wherein the second connection patterns comprise a via pattern of a metal interconnect, a contact hole pattern, or a dummy via pattern. A method of fabricating a semiconductor structure, comprising: providing a first original layout and a second original layout, the first original layout comprising a plurality of wiring patterns, the second original layout comprising a plurality of connection patterns; a plurality of patterns to be cut are defined in an original layout, and the waiting The cutting patterns are respectively overlapped with the connecting patterns; the first original layout is decomposed, and the wiring patterns and the waiting cutting patterns are respectively formed in a first decomposition layout and a second decomposition layout; The second decomposition layout is respectively formed on a first mask and a second mask; and performing a double patterning technique, sequentially transferring the first decomposition layout and the second decomposition layout to a film layer, and The film layer includes the wiring patterns and the waiting cutting pattern. The method of claim 29, further comprising transferring the connection patterns of the second original layout onto the film layer. The method of claim 30, wherein the step of transferring the second original layout is performed before or after the double patterning technique. The method of claim 29, wherein the waiting for the cutting pattern and the wiring pattern in the first original layout violates a predetermined rule. The method of claim 32, wherein the distance between the wiring patterns of the first decomposition layout and a portion of the waiting cutting pattern conforms to the predetermined rule, and the wiring patterns and portions of the second decomposition layout The distance between the waiting cutting patterns conforms to the predetermined rule. The method of claim 29, wherein the waiting cutting patterns are respectively divided into a cutting portion and a corresponding cutting portion, the first decomposition layout including the cutting portions, and the second decomposition layout comprises These correspond to the cutting portion. The method of claim 34, wherein the overlap of the waiting cutting pattern and the connecting pattern is divided to form the cutting portion and the corresponding cutting portion. The method of claim 34, further comprising performing a correcting step after forming the first decomposition layout and the second decomposition layout, and extending the first decomposition layout in a direction pointing to one of the corresponding cutting portions. The cutting portions extend the corresponding cutting portions of the second exploded layout in a direction toward one of the cutting portions. The method of claim 29, wherein the wiring patterns of the first original layout comprise trench patterns of metal interconnects. The method of claim 37, wherein the connection patterns of the second original layout comprise a via pattern of a metal interconnect, a dummy via pattern or a contact hole pattern.