TWI518446B - Method for correcting layout pattern and method for manufacturing photomask - Google Patents

Description

Method for correcting layout pattern and method for making photomask

The present invention relates to a method of modifying a layout pattern and a method of fabricating a reticle, and more particularly to a method of correcting a layout pattern for correcting a contact hole pattern overlapping a wire pattern and a method of fabricating the reticle.

In the process of manufacturing a semiconductor device, in order to smoothly transfer the pattern of integrated circuits to the semiconductor wafer, the circuit pattern in a database must be designed into a layout pattern by using a computer, and then the layout pattern is used. A reticle and the pattern on the reticle is transferred to the semiconductor wafer in a certain proportion, also known as the lithography process. The transfer of the layout pattern described above needs to be extremely accurate so as to correspond to the patterns of other processes before and after, thereby producing a precise integrated circuit.

In the lithography process, when the standard pattern on the reticle is transferred to the surface of the wafer, the pattern transferred to the surface of the wafer is deviated due to the influence of the alignment accuracy of the lithography machine, thereby affecting the semiconductor device. Performance. Especially for a stacked structure such as a multiple metal interconnect, when the contact hole pattern designed to overlap the upper and lower conductor patterns is affected by the alignment condition, the effective contact hole area is reduced. Affects the condition of electrical connections.

In the conventional method for correcting the layout pattern, in order to compensate for the influence of the alignment error generated by the lithography machine, the wire pattern is generally corrected, and in particular, the wire pattern of the position of the contact hole pattern is locally enlarged and corrected. So that even if a registration error occurs, the effective contact area between the contact hole pattern and the wire pattern is not affected.

Furthermore, as the integrated level of the semiconductor circuit rapidly increases, the line width required for the lithography process becomes smaller and smaller, and the distance between the semiconductor elements is also increasingly shortened. Due to the physical limitations of the exposure wavelengths used in current lithography processes, many too small and too small distances cannot be achieved by a single exposure alone. Therefore, a double exposure technique has been developed to decompose the target pattern and perform it through two exposure processes. However, when the double exposure technique is used, since the spacing between the conductor patterns is very close to the critical space, and there is also a consideration of the alignment error between the two exposures, the conventional method of correcting the layout pattern is generated. There are many limitations that do not achieve the desired corrections. In addition, when the double exposure technique is generally used to define the contact hole pattern, the contact hole etching is often performed in a self-aligned manner, so that the size of the contact hole is not easily adjusted by the etching process, so how to It is especially important to adjust the design of the contact hole pattern.

One of the objects of the present invention is to provide a method of correcting a layout pattern and a method of fabricating a reticle, which corrects the contact hole pattern to compensate for the influence of the exposure alignment error.

A preferred embodiment of the present invention provides a method of modifying a layout pattern comprising the following steps. First, a first layout pattern, a second layout pattern, and a pair of mis-alignment values are provided. The first layout pattern includes a first wire pattern, the second layout pattern includes at least one contact hole pattern, and the contact hole pattern at least partially overlaps the first wire pattern. Next, a computer system detects whether the distance between the contact hole pattern and the first wire pattern is less than a registration error value. Then, the contact hole pattern is enlarged from the side of the contact hole pattern and the first wire pattern by a distance smaller than the alignment error value to obtain a first corrected contact hole pattern.

A preferred embodiment of the present invention provides a method of making a reticle comprising the following steps. First, a first layout pattern, a second layout pattern, and a pair of bit error values are provided. The first layout pattern includes a first wire pattern, the second layout pattern includes at least one contact hole pattern, and the contact hole pattern at least partially overlaps the first wire pattern. Next, a computer system detects whether the distance between the contact hole pattern and the first wire pattern is less than a registration error value. Then, the contact hole pattern is enlarged from the side of the contact hole pattern and the first wire pattern by a distance smaller than the alignment error value to obtain a first corrected contact hole pattern. Thereafter, the second layout pattern is output to at least one reticle.

A preferred embodiment of the present invention provides a method of making a reticle comprising the following steps. First, a first layout pattern, a second layout pattern, a third layout pattern, a pair of bit error values, and a critical space are provided. The first layout pattern includes a first wire pattern, the second layout pattern includes at least one contact hole pattern, and the third layout pattern includes a second wire pattern and a third wire pattern. The contact hole pattern at least partially overlaps the first wire pattern, and the contact hole pattern at least partially overlaps the second wire pattern. Next, a computer system detects whether the distance between the contact hole pattern and the first wire pattern is less than a registration error value. Then, the contact hole pattern is enlarged from the side of the contact hole pattern and the first wire pattern by a distance smaller than the alignment error value to obtain a first corrected contact hole pattern. Then, it is detected by the computer system whether the distance between the first modified contact hole pattern and the third wire pattern is less than a critical interval. Then, the first modified contact hole pattern is reduced from the first modified contact hole pattern and the third conductive pattern at a distance less than one of the critical pitch to obtain a second corrected contact hole pattern. The distance between the second modified contact hole pattern and the third wire pattern is greater than or equal to the critical pitch. Thereafter, the second layout pattern is output to at least one reticle.

The invention can be applied to various top and bottom stacked structures, such as contact plugs and doped regions, multiple metal interconnect plugs and wires, and dual damascene layers. In the structure of a via hole and a trench, that is, the present invention can effectively solve the problem that the layout pattern in which the upper and lower layers overlap each other is affected by the alignment condition, and the double exposure technique can be improved. Or multiple exposure techniques to define contact hole patterns and self-aligned methods for process hole etching, which improves semiconductor process yield and component reliability (reliability) ).

Please refer to Figures 1 to 4. 1 to 3 are schematic views showing a method of modifying a layout pattern according to a first preferred embodiment of the present invention. FIG. 4 is a flow chart showing a method for modifying a layout pattern according to a first preferred embodiment of the present invention. As shown in FIGS. 1 to 4, a first preferred embodiment of the present invention provides a method of correcting a layout pattern, comprising the following steps. First, in step S10, a first layout pattern 210, a second layout pattern 220, and a pair of bit error values are provided by a database. The second layout pattern 220 includes a plurality of contact hole patterns, and the first layout pattern 210 includes a plurality of first wire patterns. In the embodiment, the second layout pattern 220 may include a plurality of contact hole patterns 221, and the first layout pattern 210 may include a first conductive line pattern 211, and the contact hole pattern 221 is overlapped with the first conductive line pattern 211. Further, the contact hole pattern 221 is overlapped with the corresponding position of the first wire pattern 211 in the subsequent semiconductor process. In order to more clearly describe the various conditions of the method for modifying the layout pattern of the embodiment, the second layout pattern 220 of the embodiment may further include a plurality of contact hole patterns 222, a plurality of contact hole patterns 223, and a plurality of contact hole patterns 224. The first layout pattern 210 may further include a first conductive line pattern 212, a first conductive line pattern 213, and a first conductive line pattern 214. However, the present invention is not limited thereto, and the second layout pattern 220 may be included only. At least one contact hole pattern, and the first layout pattern includes only one first wire pattern. Each of the contact hole patterns 222 overlaps with the first conductive line pattern 212 , and each contact hole pattern 223 overlaps with the first conductive line pattern 213 , and each contact hole pattern 224 overlaps with the first conductive line pattern 214 .

Next, in step S11, a computer system is used to detect whether the distance between each contact hole pattern and the corresponding first wire pattern is less than the alignment error value. The value of the alignment error is generally less than 10 nm, but it is not limited thereto to determine the magnitude of the alignment error value depending on the performance of the exposure machine used. For example, the method for modifying the layout pattern of the embodiment may be between a distance DL1 and a distance DR1 between each contact hole pattern 221 and the first conductive line pattern 211, and between each contact hole pattern 222 and the first conductive line pattern 212. a distance DL2 and a distance DR2, a distance DL3 and a distance DR3 between each contact hole pattern 223 and the first wire pattern 213, and a distance DL4 and a distance between each contact hole pattern 224 and the first wire pattern 214 The DR 4 performs detection, respectively, and compares the distance DL1, the distance DR1, the distance DL2, the distance DR2, the distance DL3, the distance DR3, the distance DL4, and the distance DR4 by less than the registration error value.

Then, if the distance between each contact hole pattern and the corresponding first wire pattern is not less than the alignment error value, step S14 is performed, that is, the contact hole pattern is not modified. In contrast, if the distance between each contact hole pattern and the corresponding first wire pattern is less than the alignment error value, step S12 is performed, that is, the distance between the contact hole pattern and the corresponding first wire pattern is less than the alignment error value. One of the opposite sides enlarges the contact hole pattern to obtain a first corrected contact hole pattern.

For example, since the distance DL1 and the distance DR1 are smaller than the alignment error value, the distance between the contact hole pattern 221 and the first wire pattern 211 is less than the opposite side of the alignment error value (also can be said to be respectively in FIG. 2) The direction X2 and the direction X1) enlarge the contact hole pattern 221 to obtain a first corrected contact hole pattern 221R1 (indicated by a broken line). According to the same rule, since the distance DL2 and the distance DR2 are smaller than the alignment error value, the distance between the contact hole pattern 222 and the first wire pattern 212 is less than the opposite side of the alignment error value (also can be said to be respectively toward the second figure). The middle direction X2 and the direction X1) enlarge the contact hole pattern 222 to obtain a first corrected contact hole pattern 222R1 (indicated by a broken line). In addition, since the distance DL3 is smaller than the alignment error value and the distance DR3 is not less than the alignment error value, only the distance between the contact hole pattern 223 and the first wire pattern 213 may be less than one of the alignment error values (it may also be said The contact hole pattern 223 is enlarged in the direction X2) in FIG. 2 to obtain a first corrected contact hole pattern 223R1 (indicated by a broken line). Please also note that since the distance DL4 and the distance DR4 are not less than the registration error value, the contact pattern 224 may not be modified. According to the method for correcting the layout pattern of the embodiment, the influence of the exposure alignment error can be compensated for.

In the present embodiment, the method of enlarging the contact hole pattern may include increasing the contact hole pattern by a correction length in one direction. For example, as shown in FIG. 2, the method of expanding the contact hole pattern 221 to obtain the first modified contact hole pattern 221R1 may include adding a correction length LL1 toward the direction X1 and adding a correction length LR1 toward the direction X2 to expand the contact. The method for obtaining the first modified contact hole pattern 222R1 by the hole pattern 222 may include adding a correction length LL2 toward the direction X1 and adding a correction length LR2 toward the direction X2, and expanding the contact hole pattern 223 to obtain the first corrected contact hole pattern. The method of 223R1 can include adding a correction length LR3 toward the direction X2. It should be noted that the correction length LL1, the correction length LR1, the correction length LL2, the correction length LR2, and the correction length LR3 are preferably greater than or equal to the alignment error value. It is further explained that the difference between the alignment error value and the distance between the contact hole pattern and the corresponding first conductor pattern is preferably less than or equal to the corresponding correction length. That is to say, the difference between the alignment error value and the distance DL1 is preferably less than or equal to the correction length LR1, and the difference between the alignment error value and the distance DR1 is preferably less than or equal to the correction length LL1, the alignment error value. Preferably, the difference from the distance DL2 is less than or equal to the correction length LR2, and the difference between the alignment error value and the distance DR2 is preferably less than or equal to the correction length LL2, and the difference between the alignment error value and the distance DL3 It is less than or equal to the correction length LR3, but not limited to this.

With the above method of correcting the layout pattern of the present embodiment, it is possible to compensate for the influence of the overlap region between the first layout pattern 210 and the second layout pattern 220 when a problem occurs in alignment. For example, as shown in FIG. 3, when the first layout pattern 210 is offset due to the alignment condition, the first modified contact hole is obtained since the contact hole pattern to be corrected is adjusted. The pattern 221R1, the first corrected contact hole pattern 222R1, and the first corrected contact hole pattern 223R1, so that the first corrected contact hole pattern 221R1, the first corrected contact hole pattern 222R1, and the first corrected contact hole pattern 223R1 correspond thereto The overlapping area between the first wire pattern 211, the first wire pattern 212, and the first wire pattern 213 can still maintain a certain size.

In order to further explain the semiconductor element fabricated by the method of modifying the layout pattern of the present embodiment, please refer to FIG. 5, and please refer to FIG. 1 together. FIG. 5 is a schematic view showing a semiconductor element corresponding to the method for modifying a layout pattern according to the first preferred embodiment of the present invention. As shown in FIG. 5, the semiconductor device 250 corresponding to the method for modifying the layout pattern of the present embodiment may include a semiconductor substrate 251, a dielectric layer 252, and a metal wire 254. The dielectric layer 252 has a contact hole 252V, and the metal wire 254 can be electrically connected to the semiconductor substrate 251 by the contact plug 253 formed in the contact hole 252V. As shown in FIG. 5 and FIG. 1 , in the method for modifying the layout pattern of the embodiment, the photomask fabricated by using the first layout pattern 210 including the first wiring pattern can be used to define the metal wire 254, and the The reticle formed by the second layout pattern 220 of the contact hole pattern can be used to define the contact hole 252V. Therefore, if the contact hole 252V is defined by the first modified contact hole pattern obtained by the method for modifying the layout pattern of the embodiment, the effective area of the metal wire 254 contacting the contact plug 253 due to the exposure alignment error can be prevented from being too small. The electrical performance of the semiconductor component 250 is affected, that is, the relatively widened modified contact hole pattern can still have an effective contact area with the phase-shifted original conductor pattern. Please note that, as described above, the method of modifying the layout pattern of the present embodiment is not limited to the formation of the semiconductor element 250, but is applicable to forming other semiconductor elements having overlapping designs of doped regions, contact holes and wires.

Please refer to Figure 4 and Figure 2 again. As shown in FIG. 4 and FIG. 2, the first preferred embodiment of the present invention provides a method for fabricating a reticle. The method for fabricating the reticle includes the method for modifying the layout pattern, and is further included in step S12. Then, a step S13 is performed to output the second layout pattern 220 including the first corrected contact hole pattern, for example, the first corrected contact hole pattern 221R1, the first corrected contact hole pattern 222R1, and the first modified contact hole pattern 223R1 to At least one reticle. In other words, the first modified contact hole pattern 221R1, the first modified contact hole pattern 222R1, and the first modified contact hole pattern 223R1 can also be output to different masks as needed to perform single or multiple exposure processes to form each Contact hole. The first layout pattern 210 including the first wire pattern can be output to the at least one reticle without correction. Please also note that the second layout pattern 220 may include, in addition to the first modified contact hole pattern, a contact hole pattern that is determined to be uncorrected after being detected, but is not limited thereto.

It should be noted that the present invention directly corrects the contact hole pattern without adjusting the wire pattern when solving the problem that the layout pattern in which the upper and lower layers are aligned with each other is affected by the alignment condition. Therefore, in the method of fabricating the reticle of the embodiment, in addition to outputting the first modified contact hole pattern to at least one reticle, the remaining wire patterns are not adjusted for the alignment of the upper and lower layers. However, the first layout pattern 210 and the second layout pattern 220 can be further modified. For example, the second layout pattern 220 can be subjected to optical proximity correction (OPC), for example, before the step S13. After the process rule check (PRC) or the lithography rule check (LRC) process, the mask is output, but it is not limited thereto.

Please refer to Figures 6 to 9. 6 to 8 are schematic views showing a method of modifying a layout pattern according to a second preferred embodiment of the present invention. FIG. 9 is a flow chart showing a method for modifying a layout pattern according to a second preferred embodiment of the present invention. As shown in FIGS. 6 to 9, a second preferred embodiment of the present invention provides a method of correcting a layout pattern, comprising the following steps. First, in step S20, a first layout pattern 310, a second layout pattern 320, a third layout pattern 330, a pair of bit error values, and a critical space are provided by a database. The second layout pattern 320 may include a plurality of contact hole patterns 321 , and the first layout pattern 310 may include a first wire pattern 311 , and the third layout pattern 330 may include a second wire pattern 331 and a third wire pattern 341 . The contact hole pattern 321 is overlapped with the first wire pattern 311, and the contact hole pattern 321 is overlapped with the second wire pattern 331. Further, the contact hole pattern 321 is overlapped with the corresponding positions of the first wire pattern 311 and the second wire pattern 331 in subsequent semiconductor processes, respectively. In other words, the upper and lower wiring patterns are connected by the contact hole pattern 321. In order to more clearly describe various conditions of the method for modifying the layout pattern of the embodiment, the second layout pattern 320 of the embodiment may further include a plurality of contact hole patterns 322, and the first layout pattern 310 may further include a first wire pattern 312. The third layout pattern 330 may further include a second wire pattern 332 and a third wire pattern 342. However, the present invention is not limited thereto, and the second layout pattern 320 may include only at least one contact hole pattern. A layout pattern 310 includes only a first wire pattern such that the third layout pattern 330 includes only a second wire pattern and a third wire pattern. The contact hole pattern 322 is overlapped with the first wire pattern 312, and the contact hole pattern 322 is overlapped with the second wire pattern 332.

Next, in step S21, a computer system is used to detect whether the distance between each contact hole pattern and the corresponding first wire pattern is less than the alignment error value. For example, the method for modifying the layout pattern of the embodiment may be between a distance DL5 and a distance DR5 between each contact hole pattern 321 and the first conductive line pattern 311, and between each contact hole pattern 322 and the first conductive line pattern 312. One of the distances DL6 and one distance DR6 is detected separately, and the comparison distance DL5, the distance DR5, the distance DL6, and the distance DR6 are smaller than the registration error value. Then, if the distance between each contact hole pattern and the corresponding first wire pattern is not less than the alignment error value, step S26 is performed, that is, the contact hole pattern is not modified. In contrast, if the distance between each contact hole pattern and the corresponding first wire pattern is less than the alignment error value, step S22 is performed, that is, the distance between the contact hole pattern and the corresponding first wire pattern is less than the alignment error value. One of the opposite sides, the contact hole pattern is enlarged to obtain a first corrected contact hole pattern. For example, since the distance DL5 is smaller than the alignment error value and the distance DR5 is not less than the alignment error value, only the distance between the contact hole pattern 321 and the first wire pattern 311 may be less than one of the alignment error values (also It can be said that the contact hole pattern 321 is enlarged in the direction X2) in FIG. 7 to obtain a first corrected contact hole pattern 321R1 (indicated by a thin broken line). Similarly, since the distance DL6 is smaller than the alignment error value and the distance DR6 is not less than the alignment error value, only the distance between the contact hole pattern 322 and the first wire pattern 312 may be less than one of the alignment error values (also It is said that the direction X2 in Fig. 7) enlarges the contact hole pattern 322 to obtain a first corrected contact hole pattern 322R1 (indicated by a thin broken line).

In the present embodiment, the method of enlarging the contact hole pattern may include increasing the contact hole pattern by a correction length in one direction. For example, as shown in FIG. 7, the method of expanding the contact hole pattern 321 to obtain the first modified contact hole pattern 321R1 may include adding a correction length LR5 toward the direction X2, and expanding the contact hole pattern 322 to obtain the first correction. The method of rear contact hole pattern 322R1 may include adding a correction length LR6 toward direction X2. It should be noted that the correction length LR5 and the correction length LR6 are preferably greater than or equal to the alignment error value. It is further explained that the difference between the alignment error value and the distance between the contact hole pattern and the corresponding first conductor pattern is preferably less than or equal to the corresponding correction length. That is, the difference between the alignment error value and the distance DL5 is preferably less than or equal to the correction length LR5, and the difference between the alignment error value and the distance DL6 is less than or equal to the correction length LR6, but not Limited.

After the step of adjusting the contact hole pattern and the upper layer conductor pattern, the step S23 is continued, and the corresponding position of the contact hole pattern and the underlying conductor pattern is detected by the computer system, that is, the first modified contact hole pattern and the third conductor are detected. Whether one of the distances between the patterns is less than the critical spacing. For example, the method for modifying the layout pattern of the embodiment may be a distance RD1 between the first modified contact hole pattern 321R1 and the third wire pattern 341, and the first modified contact hole pattern 322R1 and the third conductive pattern. One of the 342 distances is detected by the distance RD2, and whether the distance RD1 and the distance RD2 are smaller than the critical distance. Then, if the distance between each of the first modified contact hole patterns and the corresponding third wire pattern is not less than the critical pitch, step S27 is performed, that is, the first modified contact hole pattern is not modified. In contrast, if the distance between each of the first modified contact hole patterns and the corresponding third wire pattern is less than the critical pitch, step S24 is performed, that is, the distance between the contact hole pattern and the third wire pattern after the first correction is less than One of the critical pitches is reduced by the first modified contact hole pattern to obtain a second modified contact hole pattern. For example, since the distance RD1 is smaller than the critical pitch, the distance between the first modified contact hole pattern 321R1 and the third wire pattern 341 may be less than one of the alignment error values (also referred to as the direction in FIG. 8). X1) The first corrected contact hole pattern 321R1 is reduced to obtain a second corrected contact hole pattern 321R2 (indicated by a dotted dotted line). In contrast, since the distance RD2 is not smaller than the critical pitch, the first modified contact hole pattern 322R1 may not need to be modified. It should be noted that the distance RD3 between the second modified contact hole pattern 321R2 and the third wire pattern 341 is preferably greater than or equal to the critical pitch to prevent the second modified contact hole pattern 321R2 from being too close to the third wire pattern 341. . Please note that the registration error value of this embodiment is substantially less than 10 nm, but the limitation of the alignment error value may be determined by the performance of the exposure machine used. In addition, the critical spacing of the present embodiment is substantially less than 10 nanometers, but is not limited thereto and can be adjusted by visual process and design rules.

In order to further explain the semiconductor element fabricated by the method of modifying the layout pattern of the present embodiment, please refer to FIG. 10, and please refer to FIG. 6 together. FIG. 10 is a schematic view showing a semiconductor element corresponding to the method for modifying a layout pattern according to a second preferred embodiment of the present invention. As shown in FIG. 10, the semiconductor device 350 corresponding to the method for modifying the layout pattern of the embodiment may include a semiconductor substrate 351, a dielectric layer 352, an upper metal wire 354, a lower metal wire 355, and a lower metal wire 356. . The upper metal wire 354 may be referred to as a second metal (metal 2), and the lower metal wire 355 and the lower metal wire 356 may be referred to as a first metal (metal 1), but is not limited thereto. The dielectric layer 352 has a contact hole 352V, and the upper metal wire 354 can be electrically connected to the lower metal wire 355 by the contact plug 353 formed in the contact hole 352V. As shown in FIG. 10 and FIG. 6, in the method for modifying the layout pattern of the embodiment, the reticle formed by using the first layout pattern 310 including the first wire pattern can be used to define the upper metal wire 354, and the The reticle formed by the second layout pattern of the second wire pattern and the third wire pattern can be used to define the lower metal wire 355 and the lower metal wire 356, and the reticle made by using the second layout pattern 320 including the contact hole pattern can be used. To define the contact hole 352V. Therefore, if the contact hole 352V is defined by the first modified contact hole pattern obtained by the method of modifying the layout pattern of the embodiment, the effective area of the upper metal wire 354 contacting the contact plug 353 due to the exposure alignment error can be avoided. Too small to affect the electrical connection with the lower metal wire 355, that is, the relatively widened modified contact hole pattern can still have an effective contact area with the phase-shifted original wire pattern. In addition, if the contact hole 352V is defined by the second modified contact hole pattern obtained by the method for modifying the layout pattern of the embodiment, the contact insertion of the original design by the correction of the contact hole pattern can be further avoided. The plug 353 forms an electrical connection with the lower metal wire 356. Please also note that the method of modifying the layout pattern of the present embodiment is not limited to the formation of the semiconductor element 350, but is applicable to forming other semiconductor elements having doped regions, contact holes and wire overlap designs.

Please refer to Figure 9 and Figure 8 again. As shown in FIG. 9 and FIG. 8, a second preferred embodiment of the present invention provides a method of fabricating a reticle, the method of fabricating the reticle comprising the method of modifying the layout pattern of the second preferred embodiment described above. In addition, a step S25 is further performed after the step S24, and the second layout pattern 320 including the second modified contact hole pattern, for example, the second modified contact hole pattern 321R2, is output to the at least one photomask. Please also note that the second layout pattern 320 may include a first modified contact hole pattern, such as the first modified contact hole pattern 322R1, or may be determined to be uncorrected after being detected, in addition to the second modified contact hole pattern. Contact hole pattern, but not limited to this. In other words, the second modified contact hole pattern 321R2 and the first modified contact hole pattern 322R1 can also be output to different masks as needed to perform a multiple exposure process to form the contact holes. The first layout pattern 310 including the first wire pattern and the third layout pattern 330 including the second wire pattern and the third wire pattern may be respectively output to at least one reticle without correction.

It should be noted that the present invention directly corrects the contact hole pattern without adjusting the wire pattern when solving the problem that the layout pattern in which the upper and lower layers are aligned with each other is affected by the alignment condition. Therefore, in the method for fabricating the reticle of the embodiment, in addition to outputting the second modified contact hole pattern or/and the first modified contact hole pattern to at least one reticle, the remaining wire patterns are not aligned with the upper and lower layers. And make adjustments. However, the first layout pattern 310, the second layout pattern 320, and the third layout pattern 330 may be further modified. For example, the second layout pattern 320 may be subjected to optical proximity correction and process rules before step S25. After the inspection or optical rule inspection, etc., the mask is output, but it is not limited thereto.

In summary, the method for modifying the layout pattern and the method for fabricating the reticle provided by the present invention compensate for the influence of the alignment error during the subsequent exposure process by correcting the contact hole pattern. In addition, the distance between the conductor patterns corresponding to the contact hole pattern is also included in the correction contact hole pattern, so that the contact hole pattern can be most suitably corrected within the allowable range, thereby improving the use of double exposure technology or multiple exposures. The technique is to define the contact hole pattern and the self-alignment method to perform process tolerance during contact hole etching and to improve the reliability of the semiconductor device used for the fabrication.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

210. . . First layout pattern

220. . . Second layout pattern

211-214. . . First wire pattern

221-224. . . Contact hole pattern

221R1. . . First modified contact hole pattern

222R1. . . First modified contact hole pattern

223R1. . . First modified contact hole pattern

250. . . Semiconductor component

251. . . Semiconductor substrate

252. . . Dielectric layer

252V. . . Contact hole

253. . . Contact plug

254. . . Metal wire

310. . . First layout pattern

320. . . Second layout pattern

330. . . Third layout pattern

311-312. . . First wire pattern

321-322. . . Contact hole pattern

321R1. . . First modified contact hole pattern

321R2. . . Second corrected contact hole pattern

322R1. . . First modified contact hole pattern

331-332. . . Second wire pattern

341-342. . . Third wire pattern

350. . . Semiconductor component

351. . . Semiconductor substrate

352. . . Dielectric layer

352V. . . Contact hole

353. . . Contact plug

354. . . Upper metal wire

355. . . Lower metal wire

356. . . Lower metal wire

DL1-DL6. . . distance

DR1-DR6. . . distance

LL1-LL3. . . Corrected length

LR1. . . Corrected length

LR2. . . Corrected length

LR5. . . Corrected length

LR6. . . Corrected length

RD1-RD3. . . distance

S10-S14. . . step

S20-S27. . . step

X1. . . direction

X2. . . direction

1 to 3 are schematic views showing a method of modifying a layout pattern according to a first preferred embodiment of the present invention.

FIG. 4 is a flow chart showing a method for modifying a layout pattern according to a first preferred embodiment of the present invention.

FIG. 5 is a schematic view showing a semiconductor element corresponding to the method for modifying a layout pattern according to the first preferred embodiment of the present invention.

6 to 8 are schematic views showing a method of modifying a layout pattern according to a second preferred embodiment of the present invention.

FIG. 9 is a flow chart showing a method for modifying a layout pattern according to a second preferred embodiment of the present invention.

FIG. 10 is a schematic view showing a semiconductor element corresponding to the method for modifying a layout pattern according to a second preferred embodiment of the present invention.

210. . . First layout pattern

220. . . Second layout pattern

211-214. . . First wire pattern

221-224. . . Contact hole pattern

221R1. . . First modified contact hole pattern

222R1. . . First modified contact hole pattern

223R1. . . First modified contact hole pattern

LL1. . . Corrected length

LR1. . . Corrected length

LL2. . . Corrected length

LR2. . . Corrected length

LR3. . . Corrected length

X1. . . direction

X2. . . direction

Claims (19)

A method for modifying a layout pattern, comprising: providing a first layout pattern and a second layout pattern, wherein the first layout pattern includes a first conductive pattern, the second layout pattern includes at least one contact hole pattern, and the contact The hole pattern at least partially overlaps with the first wire pattern; providing a pair of mis-alignment values; detecting, by a computer system, whether the distance between the contact hole pattern and the first wire pattern is less than the alignment error And expanding the contact hole pattern to obtain a first corrected contact hole pattern from a distance between the contact hole pattern and the first conductive pattern that is less than one of the alignment error values. The method of modifying a layout pattern according to claim 1, wherein the method of enlarging the contact hole pattern comprises adding the contact hole pattern to a modified length. The method of modifying a layout pattern according to claim 2, wherein the correction length is greater than or equal to the alignment error value. The method of modifying a layout pattern according to claim 2, wherein a difference between the alignment error value and a distance between the contact hole pattern and the first wire pattern is less than or equal to the correction length. The method of modifying a layout pattern according to claim 1, wherein the alignment error value is substantially less than 10 nm. The method for modifying a layout pattern according to claim 1, further comprising providing a third layout pattern, wherein the third layout pattern comprises a second wire pattern and a third wire pattern, and the contact hole pattern is The second wire patterns at least partially overlap. The method for modifying a layout pattern according to claim 6 further includes: providing a critical spacing; and detecting, by the computer system, whether a distance between the first modified contact hole pattern and the third conductive pattern is less than And the second modified contact hole pattern is obtained by reducing the distance between the first modified contact hole pattern and the third conductive pattern by less than one of the critical spacings to obtain a second modified contact hole pattern, wherein the The distance between the second modified contact hole pattern and the third wire pattern is greater than or equal to the critical pitch. A method of modifying a layout pattern as described in claim 7 wherein the critical spacing is substantially less than 10 nanometers. A method of fabricating a reticle includes: providing a first layout pattern and a second layout pattern, wherein the first layout pattern includes a first conductive pattern, the second layout pattern includes at least one contact hole pattern, and the contact The hole pattern at least partially overlaps with the first wire pattern; providing a pair of bit error values; detecting, by a computer system, whether the distance between the contact hole pattern and the first wire pattern is less than the alignment error value; And the distance between the pattern and the first conductive pattern is less than one of the alignment error values, the contact hole pattern is enlarged to obtain a first modified contact hole pattern; and the second layout pattern is output to the at least one photomask. The method of producing a reticle according to claim 9, wherein the alignment error value is substantially less than 10 nm. The method of fabricating a reticle of claim 9, wherein the method of expanding the contact hole pattern comprises adding the contact hole pattern to a modified length. The method of fabricating a reticle according to claim 11, wherein the correction length is greater than or equal to the alignment error value. The method of fabricating a reticle according to claim 11, wherein a difference between the alignment error value and a distance between the contact hole pattern and the first wire pattern is less than or equal to the correction length. A method of fabricating a reticle includes: providing a first layout pattern, a second layout pattern, and a third layout pattern, wherein the first layout pattern includes a first conductive pattern, the second layout pattern including at least one contact a hole pattern, the third layout pattern includes a second wire pattern and a third wire pattern, the contact hole pattern at least partially overlapping the first wire pattern, and the contact hole pattern at least partially overlapping the second wire pattern; Providing a pair of bit error values and a critical interval; detecting, by a computer system, whether the distance between the contact hole pattern and the first wire pattern is less than the alignment error value; from the contact hole pattern and the first wire pattern Expanding the contact hole pattern by a distance less than one of the alignment error values to obtain a first corrected contact hole pattern; and detecting, by the computer system, one of the first modified contact hole pattern and the third conductive pattern Whether the distance is less than the critical spacing; the distance between the first modified contact hole pattern and the third conductive pattern is smaller than the critical spacing Correcting the contact hole pattern to obtain a second modified contact hole pattern, wherein a distance between the second modified contact hole pattern and the third wire pattern is greater than or equal to the critical pitch; and outputting the second layout pattern To at least one reticle. A method of fabricating a reticle as described in claim 14, wherein the alignment error value is substantially less than 10 nanometers. A method of making a reticle as described in claim 14, wherein the critical spacing is substantially less than 10 nanometers. The method of fabricating a reticle of claim 14, wherein the method of expanding the contact hole pattern comprises adding the contact hole pattern to a modified length. The method of fabricating a reticle according to claim 17, wherein the corrected length is greater than or equal to the alignment error value. The method of fabricating a reticle according to claim 17, wherein a difference between the alignment error value and a distance between the contact hole pattern and the first wire pattern is less than or equal to the correction length.