JP2007103723A - Semiconductor device, and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which is a large device and its circuits are easily integrated with each other, and to provide a method of manufacturing the same. <P>SOLUTION: The manufacturing method is the one of a semiconductor device wherein circuit patterns are formed on a substrate 100. The processes for forming the circuit patterns include a step of forming a first pattern 11 by the exposure performed in a first region 101 of the substrate 100 via a first mask 10, a step of forming a second pattern 21 by the exposure performed in a second region 102 adjacent to the first region via a second mask 20, and a step of so forming a third pattern 31 by the exposure performed in a boundary region 112 between the first and second regions via a third mask 30 as to connect with each other the first and second patterns 11, 21. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a large-sized semiconductor device such as a photographing element of a digital camera and a manufacturing method thereof.

  In order to improve the characteristics of a semiconductor device such as a photographing element of a high-end digital camera, development of a semiconductor device having a larger size and higher circuit integration is required. When manufacturing a large-sized semiconductor device having an area larger than the exposure area of the exposure apparatus for forming the circuit pattern of the semiconductor device, the circuit pattern formed in one exposure area and the exposure area adjacent thereto It is necessary to connect the circuit pattern formed in the above.

  Conventionally, in the exposure for forming a circuit pattern, a mask or reticle is aligned in a boundary area between a single exposure area and an exposure area adjacent to the exposure area (referred to as a boundary line and its adjacent area, hereinafter the same). An allowance is provided for connecting circuit patterns, such as by providing an overlap in the circuit pattern or by setting the end of the circuit pattern to be large (see, for example, Patent Documents 1 to 4).

However, when an overlap is provided in the direction in which the mask or reticle is arranged, if the position of the mask or reticle is shifted in the direction perpendicular to the direction in which the mask or reticle is arranged, the width of the circuit pattern in the boundary region becomes small and the circuit breaks. There are problems such as. Further, when the end of the circuit pattern is designed to be large in order to prevent disconnection or the like, it becomes difficult to form a fine pattern and it is difficult to integrate the circuit.
US Pat. No. 6,225,013 US Pat. No. 6,194,105 Japanese Patent Laid-Open No. 9-251954 JP 2004-226898 A

  The present invention provides a semiconductor device that is a large-scale semiconductor device including a plurality of regions that are divided and exposed, and that can be easily integrated by forming a fine circuit pattern, and a method for manufacturing the same. Objective.

  The present invention relates to a method of manufacturing a semiconductor device in which a circuit pattern is formed on a substrate, and the step of forming the circuit pattern is performed by exposing the first region on the substrate through a first mask. Forming a first pattern; forming a second pattern in a second region adjacent to the first region by exposure through a second mask; and the first region and the second region Forming a third pattern so as to connect the first pattern and the second pattern by exposure through a third mask in a boundary region with the region.

  The present invention also relates to a method of manufacturing a semiconductor device in which a circuit pattern is formed on a substrate, and the step of forming the circuit pattern includes a step of forming a resist film on the substrate and a step of forming a resist film A step of forming a latent image of a first pattern by exposure through a first mask in one region and a second region adjacent to the first region of the resist film by exposure through a second mask. Forming a latent image of the second pattern, and exposing the third pattern latent image to the first pattern and the first pattern by exposure through a third mask in a boundary region between the first region and the second region; A method of manufacturing a semiconductor device, comprising: a step of forming the two patterns so as to be joined together; and a step of developing the resist film to form a resist pattern including the first pattern, the second pattern, and the third pattern. It is.

  Further, the present invention is a method for manufacturing a semiconductor device in which a circuit pattern is formed on a substrate, and the step of forming the circuit pattern includes a step of forming a conductive film on the substrate, and a step of forming the conductive pattern on the conductive film. Forming a resist film; forming a first pattern latent image on the first region of the resist film by exposure through a first mask; and a second adjacent to the first region of the resist film. Forming a latent image of the second pattern by exposure through the second mask in the region, and third through exposure through the third mask at the boundary region between the first region and the second region. Forming a latent image of the pattern so as to connect the first pattern and the second pattern, and developing a resist film to form a resist pattern including the first pattern, the second pattern, and the third pattern And a resist pattern The chromatography down a manufacturing method of a semiconductor device and forming a wiring pattern and the conductive film is etched as an etching mask.

  The third mask used in the step of forming the third pattern in the semiconductor device manufacturing method according to the present invention is characterized in that the opening width at the end of the opening is smaller than the opening width at the center of the opening. can do.

  In the step of forming the third pattern of the manufacturing method of the semiconductor device according to the present invention, the third mask is formed so that the deviation between the position of the third mask and the positions of the first mask and the second mask is minimized. A pattern can be formed.

  In the method for manufacturing a semiconductor device according to the present invention, the first mask has a first overlay mark, the second mask has a second overlay mark, and the third mask has a first overlay mark. In the step of forming the first pattern having a third overlay mark corresponding to the second overlay mark and a fourth overlay mark corresponding to the second overlay mark, In the step of forming a first overlay mark pattern together with the first pattern in the first region using the first mask and forming the second pattern, the second region is formed using the second mask. In the step of forming the second overlay mark pattern together with the second pattern and forming the third pattern, the third pattern is formed in the boundary region using the third mask, and the first overlay is formed. Together Forming a third overlay mark pattern so as to overlap the mark pattern and a fourth overlay mark pattern so as to overlap the second overlay mark pattern; The position of the third mask is minimized so as to minimize the positional deviation from the third overlay mark pattern and the positional deviation between the second overlay mark pattern and the fourth overlay mark pattern. It can be characterized in that a deviation from the positions of the first mask and the second mask is minimized.

  In addition, the present invention is a semiconductor device including a plurality of regions that are divided and exposed, wherein a circuit pattern in at least one boundary region in the region is formed by the above manufacturing method.

  According to the present invention, by forming a fine circuit pattern, it is possible to provide a large-sized semiconductor device that includes a plurality of regions that are divided and exposed and that can be easily integrated, and a method for manufacturing the same.

(Embodiment 1)
An embodiment of a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device in which a circuit pattern is formed on a substrate 100 with reference to FIG. Includes a step of forming the first pattern 11 in the first region 101 on the substrate 100 by exposure through the first mask 10 (FIG. 1A), and a second adjacent to the first region 101. A step of forming the second pattern 21 by exposure through the second mask 20 in the region 102 (FIG. 1B) and a boundary region 112 between the first region 101 and the second region 102. A step (FIGS. 1D and 1E) of forming the third pattern 31 so as to connect the first pattern 11 and the second pattern 21 by exposure through the third mask 30.

  According to the method for manufacturing a semiconductor device according to the present embodiment, a large overlay margin of the mask is not required, and the first pattern 11 and the second pattern that form the circuit pattern without increasing the end of the circuit pattern. Fine patterns can be formed without narrowing the pattern widths of the pattern 21 and the third pattern 31, and a large-sized semiconductor device with easy circuit integration can be easily manufactured. Note that the mask used in the present embodiment refers to a mask in a broad sense that includes a reticle that is placed on a substrate apart from the substrate, in addition to a mask in a narrow sense placed on the substrate. The effects of the present invention will be described in detail below in comparison with the prior art.

  In a semiconductor device including a plurality of regions exposed in a divided manner, when connecting a circuit pattern in the first region and a circuit pattern in the second region, conventionally, as shown in FIG. An overlap was provided in the direction in which the reticles were lined up. That is, first, as shown in FIG. 11A, the first mask 10 is arranged such that the pattern forming portion 10b is positioned in the second region 102 slightly beyond the boundary line L from the first region 101. After the arrangement, the first region 101 is exposed to form a first pattern 11 as shown in FIG. Next, as shown in FIG. 11B, the second mask 20 is arranged so that the pattern forming portion 20 b is positioned in the first region 101 slightly beyond the boundary line L from the second region 102. After that, the second region 102 is exposed to form a second pattern 21 as shown in FIG.

  In the conventional method for connecting the first pattern and the second pattern as described above, the position of the second mask 20 is perpendicular to the mask alignment direction with respect to the position of the first mask 10. When shifted by D3 (FIG. 11B), the position of the second pattern 21 is shifted from the position of the first pattern 11 by D3. For this reason, the width of the pattern to be formed is narrower by D3 in the boundary region 112 between the first region 101 and the second region 102 than in the other regions. Therefore, when D3 increases, the pattern breaks. In order to prevent this, if the width D1 at the end of the pattern is designed large, it becomes difficult to form a fine pattern. The opening width of the pattern opening 10a of the first mask 10 and the opening width of the pattern opening 20a of the second mask 20 are both set to D1. In the discussion of the positional deviation of the mask, the positional deviation criterion is not the boundary line of the pattern forming portion in the mask and / or pattern but the center line. Specifically, in FIG. 11, D3 denotes the center line of the first pattern pattern forming portion (that is, the pattern forming portion 10b of the first mask 10) and the second pattern pattern forming portion (that is, the second mask). It means the distance from the center line of the 20 pattern forming portions 20b). Hereinafter, when discussing misalignment of the mask and / or pattern, the misalignment reference is the center line of the pattern forming portion in the mask and / or pattern.

  On the other hand, the semiconductor device manufacturing method according to the present invention is characterized in that the first pattern 11 and the second pattern 21 are connected by the third pattern 31 as shown in FIG. That is, first, as shown in FIG. 2A, the first mask 10 is arranged so that the pattern forming portion 10b is positioned in the first region 101, and then the first region 101 is exposed. A first pattern 11 as shown in FIG. 2B is formed. Next, as shown in FIG. 2B, after the second mask 20 is arranged so that the pattern forming portion 20b is located in the second region 102, the second region 102 is exposed, A second pattern 11 as shown in FIG. 2C is formed. The width of the opening 10a of the first mask 10 and the width of the opening 20a of the second mask 20 are both D1.

  Here, when the position of the second mask 20 is shifted by D3 with respect to the position of the first mask 10 in the direction perpendicular to the direction in which the masks are arranged (FIG. 2B), FIG. As shown, the position of the second pattern 21 is deviated from the position of the first pattern 11 by D3.

  Next, as shown in FIG. 2D, the pattern forming portion 30 b of the third mask 30 having the opening 30 a is positioned in the boundary region 112 between the first region 101 and the second region 102. Thus, the boundary region 112 is exposed to form a third pattern 31 that joins the first pattern 11 and the second pattern 21 as shown in FIG. Note that the width of the opening 30a of the third mask 30 is D2.

  Here, as shown in FIG. 2E, the positional deviation between the first pattern 11 and the third pattern 31 is D4, and the positional deviation between the second pattern 21 and the third pattern 31 is D5. Then, the positional deviation D3 between the first pattern 11 and the second pattern 21 is D3 = D4 + D5. That is, according to the manufacturing method of the semiconductor device according to the present embodiment, the first pattern 11 and the second pattern 21 are connected by connecting the first pattern 11 and the second pattern 21 with the third pattern 31. 21 is divided into a positional deviation D4 between the first pattern 11 and the third pattern 31 and a positional deviation D5 between the second pattern 21 and the third pattern 31 and The misalignment can be reduced. Thereby, the disconnection of the pattern can be prevented without designing the width of the end portion of the pattern to be large, and a large semiconductor device having a fine pattern can be manufactured.

  More specifically, the manufacturing method of the semiconductor device according to the present embodiment is a manufacturing method of a semiconductor device in which a circuit pattern is formed on a substrate 100 with reference to FIG. The forming step includes a step of forming a resist film on the substrate 100 and a step of forming a latent image of the first pattern 11 in the first region 101 of the resist film by exposure through the first mask 10 (FIG. 2 (a) and (b)) and a step of forming a latent image of the second pattern 21 in the second region 102 adjacent to the first region of the resist film by exposure through the second mask 20 ( 2 (b) and (c)), the latent image of the third pattern 31 is first exposed to the boundary region 112 between the first region 101 and the second region 102 through the third mask 30. The pattern 11 and the second pattern 21 together Forming the resist film (FIGS. 2D and 2E), developing the resist film, and forming a resist pattern including the first pattern 11, the second pattern 21, and the third pattern 31; including.

  According to the above method for manufacturing a semiconductor device, the latent image of the first pattern 11 and the latent image of the second pattern 21 are joined together by the latent image of the third pattern 31. The positional deviation D3 between the latent image and the latent image of the second pattern 21 is the positional deviation D4 between the latent image of the first pattern 11 and the latent image of the third pattern 31 and the latent image of the second pattern 21. By dividing the third pattern 31 into the positional deviation D5 with respect to the latent image, the positional deviation at the time of joining can be reduced. Thereby, the disconnection of the pattern can be prevented without designing the width of the end portion of the pattern to be large, and a large semiconductor device having a fine resist pattern can be manufactured.

  More specifically, the manufacturing method of the semiconductor device according to the present embodiment is a manufacturing method of a semiconductor device in which a circuit pattern is formed on a substrate 100 with reference to FIG. The forming step includes a step of forming a conductive film on the substrate 100, a step of forming a resist film on the conductive film, and exposure to the first region 101 of the resist film through the first mask 10 by first exposure. The latent image of the pattern 11 is formed (FIGS. 2A and 2B), and the second region 102 adjacent to the first region of the resist film is exposed through the second mask 20 to the first region. A process of forming a latent image of the second pattern 21 (FIGS. 2B and 2C), and exposure through the third mask 30 to the boundary region 112 between the first region 101 and the second region 102 The latent image of the third pattern 31 is converted into the first pattern 11 by A step of forming the second pattern 21 so as to be joined (FIGS. 2D and 2E), and developing the resist film to form the first pattern 11, the second pattern 21, and the third pattern 31. And a step of forming a wiring pattern by etching the conductive film using the resist pattern as an etching mask. By including such a process, a large semiconductor device having a fine wiring pattern can be manufactured.

  According to the above method for manufacturing a semiconductor device, the latent image of the first pattern 11 and the latent image of the second pattern 21 are joined together by the latent image of the third pattern 31. The positional deviation D3 between the latent image and the latent image of the second pattern 21 is the positional deviation D4 between the latent image of the first pattern 11 and the latent image of the third pattern 31 and the latent image of the second pattern 21. By dividing the third pattern 31 into the positional deviation D5 with respect to the latent image, the positional deviation at the time of joining can be reduced. Thereby, the disconnection of the pattern can be prevented without designing the width of the end of the pattern to be large, and a large semiconductor device having a fine wiring pattern can be manufactured.

  Here, when a positive resist from which an exposed portion is removed by development is used as the resist for forming the resist film, the resist film exists on the first pattern 11, the second pattern 21, and the third pattern 31. A resist pattern is formed, and a wiring pattern in which a conductive film exists on the first pattern 11, the second pattern 21, and the third pattern 31 is formed. In such a case, from the viewpoint of preventing the disconnection of the wiring pattern by making the pattern width of the third pattern equal to or greater than the pattern width of the first pattern and the second pattern, the opening width of the opening 10a of the first mask 10 and It is preferable to use a mask in which the opening width D1 of the opening 20a of the second mask 20 and the opening width D2 of the opening 30a of the third mask 30 have a relationship of D1 ≧ D2.

  Further, when a negative resist from which a portion not exposed by development is removed is used as a resist for forming the resist film, openings are formed on the first pattern 11, the second pattern 21, and the third pattern 31. A resist pattern in which an opening exists is formed, and a wiring pattern in which an opening is present is formed on the first pattern 11, the second pattern 21, and the third pattern 31. In such a case, from the viewpoint of preventing the disconnection of the wiring pattern by making the pattern width of the third pattern equal to or greater than the pattern width of the first pattern and the second pattern, the opening width of the opening 10a of the first mask 10 and It is preferable to use a mask in which the opening width D1 of the opening 20a of the second mask 20 and the opening width D2 of the opening 30a of the third mask 30 have a relationship of D1 ≦ D2.

  Referring to FIG. 3A, the first mask 10 used to form the first pattern 11 includes an exposure target in addition to the opening 10a, the pattern forming portion 10b, and the mask band 10c. A masking blade 10d may be provided to prevent the exposure of the second region adjacent to the first region 101, which is the region. Similarly, referring to FIG. 3B, the second mask 20 used for forming the second pattern 21 is exposed in addition to the opening 20a, the pattern forming portion 20b, and the mask band 20c. A masking blade 20d may be provided to prevent the exposure of the second area adjacent to the second area 101, which is the target area.

  Referring to FIG. 4, the third mask 30 is preferably designed such that the opening width at the end of the opening 30a is smaller than the opening width D2 at the center of the opening. In the third mask, the width of the end of the opening may be continuously reduced (FIG. 4A), or the width of the end of the opening may be reduced stepwise (FIG. 4). (B)). By using the third mask 30, as shown in FIG. 4C, the rapid reduction of the pattern width caused by the positional deviation between the third pattern and the first pattern and the second pattern is alleviated. And a pattern with a smaller change in pattern width can be obtained. In the pattern generated by actual exposure, the change in the pattern width becomes smaller because the corner of the stepped portion becomes round.

(Embodiment 2)
In this embodiment, referring to FIGS. 2, 5, and 6, in the step of forming the third pattern 31 of the first embodiment, the position of the third mask 30, the first mask 10, and the second mask 31 are the same. The third pattern is formed so that the deviation from the position of the mask 20 is minimized.

  In the present embodiment, a mask as shown in FIG. 5 is used. That is, as shown in FIG. 5A, the first mask 10 has a first overlap indicating the position of the first mask 10 in addition to the opening 10a, the pattern forming portion 10b, and the mask band 10c. An alignment mark 10e is provided. In addition, as shown in FIG. 5B, the second mask 20 includes a second mask 20 that displays the position of the second mask 20 in addition to the opening 20a, the pattern forming portion 20b, and the mask band 20c. An overlay mark 20e is provided. Further, as shown in FIG. 5C, the third mask 30 displays a third mask 30 that displays the position of the third mask 30 as another opening in addition to the opening 30a and the pattern forming portion 30b. An overlay mark 30e and a fourth overlay mark 30f are provided. Here, the third overlay mark 30e corresponds to the first overlay mark 10e, and the fourth overlay mark 30f corresponds to the second overlay mark 20e. .

  In the present embodiment, using the mask with the overlay mark, the displacement between the position of the third mask 30 and the positions of the first mask 10 and the second mask 20 is as follows. The mask can be aligned so as to be minimized.

  Referring to FIG. 2, the first mask 10 having the first overlay mark 10e is used in the first pattern forming step shown in FIGS. A first overlay mark pattern (not shown) is formed in the region 101 together with the first pattern 11. Next, in the second pattern forming step shown in FIGS. 2B and 2C, the second mask 20 having the second overlay mark 20e is used, so that the second region 102 is formed. In addition to the second pattern 21, a second overlay mark pattern (not shown) is formed.

  Next, in the third pattern forming step shown in FIGS. 2D and 2E, a third overlay mark 30e corresponding to the first overlay mark 10e, and the second overlay mark 30e. By using the third mask 30 having the fourth overlay mark 30f corresponding to the overlay mark 20e, the third mask pattern 31 is formed in the boundary region 112, and as shown in FIG. A third overlay pattern 31e is formed so as to overlap the first overlay mark pattern 11e, and a third overlay mark pattern 31f is formed so as to overlap the second overlay pattern 21e. Is done.

  That is, referring to FIG. 6, the first overlay mark pattern 61 constituted by the first overlay mark pattern 11e and the third overlay mark pattern 31e as shown in FIG. A second overlay mark pattern 62 constituted by the second overlay mark pattern 21e and the fourth overlay mark pattern 31f as shown in FIG. 6B is obtained.

  Here, in the first overlay mark pattern 61, the left side, the right side, the upper side, and the lower side of the first overlay mark pattern 11e, and the corresponding left side, right side, and upper side of the third overlay mark pattern 31e. And the distance from the lower side are X11, X12, Y11 and Y12, respectively. At this time, the X component of the positional deviation of the third mask with respect to the first mask in the first overlay mark pattern 61 is evaluated as | X11−X12 | / 2, and the Y component is evaluated as | Y11−Y12 | / 2. be able to. Similarly, in the second overlay mark pattern 62, the left side, the right side, the upper side, and the lower side of the second overlay mark pattern 21e, and the corresponding left side, right side, and upper side of the fourth overlay mark pattern 31f, respectively. And the distance from the lower side are X21, X22, Y21 and Y22, respectively. At this time, the X component of the positional deviation of the third mask with respect to the second mask in the second overlay mark pattern 62 is evaluated as | X21−X22 | / 2, and the Y component is evaluated as | Y21−Y22 | / 2. be able to.

  Therefore, preliminary exposure is performed using a mask with overlay marks, and | X11-X12 | / 2 and | Y11-Y12 | / 2 of the first overlay mark pattern 61 and the second overlay mark. By adjusting the position of the third mask with respect to the positions of the first mask and the second mask so that | X21-X22 | / 2 and | Y21-Y22 | / 2 of the pattern 62 are minimized. The positional deviation of the third mask with respect to the first mask and the second mask can be minimized. By using the first mask, the second mask, and the third mask thus positioned, the first pattern, the second pattern, and the third pattern are formed, respectively, so that the change in the pattern width is minimized. Pattern can be formed. For example, according to the method for manufacturing a semiconductor device of the present embodiment, the change in the pattern width at the joining portion of the pattern having the pattern width of 400 nm can be made 40 nm or less. According to the conventional manufacturing method, a change in the pattern width of about 250 nm at the maximum has occurred in the joint portion of the pattern having a pattern width of 400 nm.

(Embodiment 3)
One embodiment of a semiconductor device according to the present invention is described with reference to FIG. 7 in which a plurality of regions to be divided and exposed (in FIG. 7, a first region 101, a second region 102, and a third region 103). , Fourth region 104,..., Kth region,..., Nth region), and the circuit pattern in at least one boundary region in these regions is the above-described first embodiment. Alternatively, the semiconductor device is formed by the manufacturing method of the second embodiment. As described above, by forming the circuit pattern in at least one boundary region by the manufacturing method of the first embodiment or the second embodiment, a large-sized semiconductor device with easy circuit integration can be obtained.

As a specific embodiment of the semiconductor device according to the present invention, a complementary metal-oxide semiconductor (CMOS) device will be described. A CMOS device, which is a semiconductor device of the present embodiment, is manufactured as follows with reference to FIGS.
First, impurity layers 702 and 703 are formed on the surface layer of the silicon substrate 700 and a photodiode 704 is formed on the surface layer of the impurity layer 702 on the silicon substrate 700 using conventional lithography, etching, and ion implantation techniques. . Subsequently, a silicon oxide film is deposited by a CVD (Chemical Vapor Deposition) method, an isolation region 705 is formed using lithography, etching, and oxidation techniques to form an S10 layer.

  Next, polysilicon is deposited on the S10 layer by CVD, silicon oxide is deposited by CVD, and a gate 711 is formed using lithography and etching techniques. Further, after depositing silicon oxide as the insulating layer 712 by a CVD method, a contact 713 and a gate 711 for conducting the impurity layer 703 and a first wiring 721 to be formed later and a first wiring 721 to be formed later are formed. A conductive contact 714 is formed, W (tungsten) is further deposited, W is buried in the contacts 713 and 714 by a CMP (Chemical Mechanical Polishing) method, and an S11 layer is formed.

  Next, Al is deposited on the S11 layer, and the first wiring 721 is formed using lithography and etching techniques. Subsequently, after depositing silicon oxide as the insulating layer 722 by a CVD method, a via 725 is formed to connect the first wiring 721 and a second wiring 731 to be formed later, W is deposited, and a CMP method is formed. Thus, W is buried in the via 725 to form the S12 layer.

  Next, Al is deposited on the S12 layer, and the second wiring 731 is formed using lithography and etching techniques. In the present embodiment, the second wiring 731 connects the wiring patterns (connecting portion 731B). That is, an Al film for forming the second wiring 731 is formed on the insulating layer 722 by a CVD method, a resist film is formed on the Al film, and a first mask is formed in the first region of the resist film. A latent image of the first pattern is formed by exposure via Subsequently, a latent image of a second pattern is formed in a second region adjacent to the first region of the resist film by exposure through a second mask. Subsequently, the latent image of the third pattern is connected to the first pattern and the second pattern by exposing the boundary area between the first area and the second area through the third mask. Form. Subsequently, the resist film is developed to form a resist pattern including the first pattern, the second pattern, and the third pattern. Next, using this resist pattern as an etching mask, the Al film is etched to form a wiring pattern of the second wiring. Next, after depositing silicon oxide as the insulating layer 732 by a CVD method, a via 735 is formed to connect the second wiring 731 and a third wiring 741 to be formed later, W is deposited, and CMP is performed. W is buried in the via 735 to form the S23 layer.

  Next, Al is deposited on the S23 layer, and a third wiring 741 is formed using lithography and etching techniques. Subsequently, silicon oxide is deposited as the insulating layer 742 by a CVD method to form an S30 layer.

Finally, a lens 751 is formed on the S30 layer to form a CMOS device.
By the above manufacturing method, a CMOS device which is a large semiconductor device in which fine circuit patterns are integrated can be obtained. In the present embodiment, the patterns are connected in the second wiring, but the patterns can be connected by the first wiring, the third wiring, or a combination thereof. From the viewpoint of suppressing an increase in the number of processes, it is preferable to combine patterns together into any one wiring.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a schematic diagram which shows the manufacturing method of the semiconductor device concerning this invention. (A) shows the formation process of the 1st pattern, (b) shows the formation process of the 2nd pattern, (c) shows the shape of the formed 1st pattern and the 2nd pattern, (d ) Shows a step of forming a third pattern, and (e) shows the formed first pattern, second pattern, and third pattern. It is a schematic diagram which shows the actual manufacturing method of the semiconductor device concerning this invention. (A) shows the formation process of the 1st pattern, (b) shows the formation process of the 2nd pattern, (c) shows the shape of the formed 1st pattern and the 2nd pattern, d) shows the formation process of a 3rd pattern, (e) shows the formed 1st pattern, 2nd pattern, and 3rd pattern. It is a schematic diagram explaining the structure of a mask. (A) shows the structure of the first mask, and (b) shows the structure of the second mask. It is a schematic diagram which shows the shape of the opening part of a 3rd mask. (A) shows a shape in which the width of the end of the opening is continuously reduced, (b) shows a shape in which the width of the end of the opening is gradually reduced, and (c) is a third mask. The pattern obtained when (a) or (b) is used is shown. It is a schematic diagram explaining the mask with a mark for superimposition. (A) shows a 1st mask, (b) shows a 2nd mask, (c) shows a 3rd mask. It is a schematic diagram which shows the overlay state of an overlay mark pattern. It is a schematic diagram which shows a semiconductor device provided with the several area | region exposed by dividing | segmenting. 1 is a schematic top view showing a specific embodiment of a semiconductor device according to the present invention. It is a cross-sectional schematic diagram of the IX-IX cross section in FIG. It is a cross-sectional schematic diagram of the XX cross section in FIG. It is a schematic diagram which shows the actual manufacturing method of the conventional semiconductor device. (A) shows the formation process of a 1st pattern, (b) shows the formation process of a 2nd pattern, (c) shows the shape of the formed 1st pattern and 2nd pattern.

Explanation of symbols

  10 first mask, 10a, 20a, 30a opening, 10b, 20b, 30b pattern forming part, 10c, 20c mask band, 10d, 20d masking blade, 10e first overlay mark, 11 first pattern, 11e First overlay mark pattern, 20 second mask, 20e second overlay mark, 21 second pattern, 21e second overlay mark pattern, 30 third mask, 30e third 30f 4th overlay mark, 31 3rd pattern, 31e 3rd overlay mark pattern, 31f 4th overlay mark pattern, 61 1st overlay mark pattern, 62 second overlay mark pattern, 100 substrate, 101 first region, 102 2nd region, 103 3rd region, 104 4th region, 112 boundary region, 700 silicon substrate, 702, 703 impurity region, 704 photodiode, 705 isolation region, 711 gate, 712, 722, 732, 742 insulation Layer, 713, 714 contact, 721 first wiring, 725, 735 via, 731 second wiring, 731B connecting portion, 741 third wiring, 756 lens.

Claims (7)

A method of manufacturing a semiconductor device in which a circuit pattern is formed on a substrate,
The step of forming the circuit pattern includes a step of forming a first pattern on the first region on the substrate by exposure through a first mask, and a second region adjacent to the first region. Forming a second pattern by exposure through a second mask, and forming a third pattern by exposure through a third mask at a boundary region between the first region and the second region. A method of manufacturing a semiconductor device, comprising: forming the first pattern and the second pattern so as to be joined together. A method of manufacturing a semiconductor device in which a circuit pattern is formed on a substrate,
The step of forming the circuit pattern includes forming a resist film on the substrate, and forming a latent image of the first pattern on the first region of the resist film by exposure through a first mask. A step of forming a latent image of a second pattern by exposure through a second mask in a second region adjacent to the first region of the resist film; the first region and the first region; Forming a latent image of a third pattern in a boundary region with the second region by exposure through a third mask so as to connect the first pattern and the second pattern, and the resist film And developing a resist pattern including the first pattern, the second pattern, and the third pattern by developing the semiconductor device. A method of manufacturing a semiconductor device in which a circuit pattern is formed on a substrate,
The step of forming the circuit pattern includes a step of forming a conductive film on the substrate, a step of forming a resist film on the conductive film, and a first mask in the first region of the resist film. Forming a latent image of the first pattern by performing the exposure, and forming a latent image of the second pattern by exposing through a second mask to the second region adjacent to the first region of the resist film. Forming a latent image of a third pattern in a boundary region between the first region and the second region by exposing through a third mask to the first pattern and the second pattern; Forming the resist pattern, developing the resist film to form a resist pattern including the first pattern, the second pattern, and the third pattern, and etching the resist pattern into an etching mask Method of manufacturing a semiconductor device and forming a wiring pattern by etching the conductive film is.   The said 3rd mask used in the process of forming a said 3rd pattern is characterized by the opening width in the edge part of an opening part being smaller than the opening width in the center part of the said opening part. 4. A method for manufacturing a semiconductor device according to any one of items 3 to 3.   Forming the third pattern so that a shift between the position of the third mask and the positions of the first mask and the second mask is minimized in the step of forming the third pattern; The method for manufacturing a semiconductor device according to claim 1, wherein: The first mask has a first overlay mark, the second mask has a second overlay mark, and the third mask corresponds to the first overlay mark. A third overlay mark, and a fourth overlay mark corresponding to the second overlay mark,
In the step of forming the first pattern, a first overlapping mark pattern is formed together with the first pattern in the first region using the first mask,
In the step of forming the second pattern, a second overlay mark pattern is formed in the second region together with the second pattern using the second mask,
In the step of forming the third pattern, the third pattern is formed in the boundary region using the third mask, and a third overlap is formed so as to overlap the first overlay mark pattern. Forming an alignment mark pattern and a fourth overlay mark pattern so as to overlap the second overlay mark pattern;
The positional deviation between the first overlay mark pattern and the third overlay mark pattern, and the positional deviation between the second overlay mark pattern and the fourth overlay mark pattern. 6. The shift between the position of the third mask and the positions of the first mask and the second mask is minimized so as to minimize the position. The manufacturing method of the semiconductor device of description. A semiconductor device including a plurality of regions to be divided and exposed,
The semiconductor device in which the circuit pattern in at least one boundary region in the region is formed by the manufacturing method according to claim 1.

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