JPS60140720A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent an electrode wiring from causing step coverage without high-temperature treatment, by providing an electrode window with stairs-like steps from the ends of the window along the longitudinal directions of the electrode wiring. CONSTITUTION:An Si substrate 1 is provided with an impurity region 2 which is covered with an SiO2 film 3, and resist is superposed thereon. A rectangular window 5 including the region 2 and extending from both sides of the region 2 along the longitudinal directions of wiring is provided, and a half of the thickness of the film 3 is etched away to form a rectangular groove 6. Subsequently, resist 7 is further superposed and a rectangular hole 8 is provided so as to intersect the hole 5 orthogonally. When the film 3 is etched away to expose the region 2 and the resists 4 and 7 are removed, an electrode window extending stepwise only in the longitudinal directions of the wiring is completed. A wiring 10 of a predetermined pattern is then applied thereto. In such a manner, no step coverage is caused at least in the longitudinal directions of the wiring, and the integration density is not decreased.

Description

Detailed Description of the Invention (7) Technical Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same. More specifically, the present invention relates to a semiconductor device in which electrode wiring of a semiconductor device makes a predetermined electrical connection. This invention relates to the formation of a blank electrode contact window.

(() Prior Art and Problems In a semiconductor device, wiring is formed to configure a predetermined circuit, and this wiring passes through an electrode contact window (contact hole) formed in an insulating film to an impurity-introduced region of a semiconductor substrate or a polygon. It is in contact with a silicon gate, etc.

In recent years, as semiconductor devices have become increasingly highly integrated, electrode contact windows have also become smaller. If this electrode contact window is small, or if there is a large step (difference between the exposed surface inside the window and the surface of the insulating film) at the electrode contact window due to unevenness of the insulating film, the wiring may break at the step or become thin. There is a problem in that poor step coverage occurs, such as an increase in resistance. In order to prevent this step force parage failure, the insulating film is made of phosphosilicate glass (P).
SG) and then heat it to high temperature (1000 to 1100℃).
℃) to fluidize (melt flow), thereby eliminating the corners of the steps and creating a rounded slope. However, when such high-temperature heating is performed, the impurity-introduced region of the semiconductor substrate expands due to thermal diffusion of the impurity, causing undesirable changes in device characteristics, and in the worst case, normal operation becomes impossible. Furthermore, warping of the wafer may have an unfavorable effect on the semiconductor device.

(1) Purpose of the Invention The purpose of the present invention is to prevent defective step coverage of electrode wiring without performing the above-mentioned high-temperature heat treatment.

Another object of the present invention is to form a wiring electrode contact window in an insulating film that can avoid step coverage defects.

B) Structure of the Invention The above-mentioned object is to extend an electrode wiring in contact with a contact region within the electrode contact window on an insulating film in which an electrode contact window is formed, and the insulating film extends from the edge of the electrode contact window to the electrode. This is achieved by a semiconductor device characterized by having step-like steps along the longitudinal direction of the wiring. In other words, the shape of this electrode contact window can be said to be a convex shape in which two rectangles are overlapped in cross section in the longitudinal direction of the electrode wiring.

The above method for manufacturing a semiconductor device having an electrode tent window includes selectively etching an insulating film to form a groove extending on both sides in the longitudinal direction of the electrode wiring including the base conductive portion to be exposed within the window; Next, the method of manufacturing a semiconductor device is characterized in that the insulating film on the underlying conductive portion to be exposed within the trench is selectively etched away to complete an electrode contact window.

(3) Examples of Embodiments of the Invention The present invention will be described in more detail below with reference to embodiments of Yumei Moto, with reference to the accompanying drawings.

Embodiment Example 1 First, a predetermined impurity introduction region 2 is formed in a semiconductor substrate 1 (FIG. 1B), and an insulating film 3 is formed on this semiconductor substrate. The insulating film 3 is formed of silicon dioxide (5io2) or phosphosilicate glass (PSG) by a conventional method (for example, chemical vapor deposition). In the case of a PSG film, a thin 5i02 film is formed between the film and the semiconductor substrate to prevent phosphorus in the PSG from diffusing into the substrate. 172nd
11 layers 4 (FIGS. 1A and 1B) are coated on the insulating film 3, exposed to four turns of a rectangular shape by a well-known method such as ultraviolet rays or an electron beam using a photomask, and developed.
A rectangular hole 5 is formed in the 17211th layer 4.

Using this 17211th layer 4 as a mask, the insulating film 3 is selectively etched until its film thickness is reduced to approximately half, thereby forming rectangular grooves 6.
(Fig. 1B) is formed. The etching method is preferably a conventional dry etching method, such as a reactive ion etching (RIE) method.

The groove 6 thus formed includes a region corresponding to the window exposing the impurity introduction region 2 and extends on both sides of the region in the longitudinal direction of the electrode wiring.

Next, without removing the 17211 layer 4, a second resist layer 7 (FIGS. 2A and 2B) is applied to the entire surface, exposed to light in a rectangular pattern, and acupuncture is performed.
A rectangular hole 8 is formed in.

This hole 8 intersects the previously formed hole 5 at almost a right angle, and this intersecting area corresponds to the exposure window to be formed. Note that, as shown in FIG. 2A, it is preferable that the holes 8 and 5 are perpendicular to each other, but they do not need to be perpendicular to each other, in which case the contact window becomes a parallelogram. When the holes 8 in the second resist layer 7 are formed in this manner, the portions of the insulating film 30 in the intersection areas are exposed, and the exposed insulating film portions are etched away by selective etching as described above to form the exposed windows 9, (Second
Figure B) is formed. A portion of the impurity-introduced region 2 of the semiconductor substrate 1 is exposed within this exposure window 9. Then, the first V cyst layer 4 and the second resist layer 7 are removed with a solvent or by ashing to complete an electrode contact window that extends stepwise only in the longitudinal direction of the electrode wiring, as shown in FIG. 2B. do.

Next, a conductive layer is formed on the entire surface by vapor deposition or sputtering of a conductive material such as aluminum, and a predetermined/4' turn wiring 10 (see FIG. , Figure 3B)
to form. In FIG. 3A, the portion of the wiring 10 corresponding to the contact window is made wider to allow for alignment with the electrode contact window. In the wiring 10 formed in this way, as shown in FIG. 3B, the side surface of the electrode contact window has a two-step difference, and the height of each step is low, so that there is no problem in step coverage. However, since the level difference between the semiconductor substrate 1 and the surface of the insulating film 3 on the side surface parallel to the longitudinal direction of the wiring 10 of the electrode contact window is the same as in the conventional case, there is a possibility that step coverage failure may occur in this part. . Even if a step coverage defect occurs here, there is no problem as a semiconductor device because electrical connection is established between the wiring 10 and the impurity doped region 2 in the longitudinal direction of the wiring. On the other hand, if the electrode windows are made to have a step-like shape even in a direction perpendicular to the longitudinal direction of the wiring, it is necessary to leave a sufficient distance between adjacent contact windows in the perpendicular direction, which reduces the integration density. In this point, in the longitudinal direction of the wiring, even if the contact window occupies a somewhat long area, it does not cause a reduction in the integration density because it is the area where the wiring originally extends.

Embodiment 2 After forming the grooves 6 as shown in FIGS. 1A and 1B in Embodiment 1, the second resist layer 4 is removed using a solvent or by ashing. Then, the second resist layer 7 is applied to the entire surface of the insulating film 3 with the grooves 6, exposed to light in a rectangular pattern, and developed to form the same rectangular holes 8 as in the embodiment example 1 in the second resist layer 7. (Fig. 4A, 4B)
Figure and Figure 4C). Using this second resist film 7 as a mask, the insulating film 3 is similarly etched away until the impurity introduced region 2 of the semiconductor substrate 1 is exposed, thereby forming a trench 11 similar to the trench 6 as shown in FIG. 4C. At the intersection of groove 6 and groove 11, an exposed window 9 is formed.
(FIGS. 4B and 4C) are formed.

Next, after removing the second resist layer 7, the wiring 10 is formed in the same manner as in Embodiment 1 (FIG. 5A).

Figure 5B). In this case, the cross section in the longitudinal direction of the wiring (arrow 11
1B-11 [B) is the same as FIG. 3B, and no defective step coverage occurs in the step at the electrode contact window in the wiring 10. The cross section in the direction perpendicular to the longitudinal direction of the wiring (arrow VB-VB) is as shown in Fig. 5B, and since the thickness of the insulating film 3 is almost half and the step difference is small, no defective step coverage occurs. .

ψ) Effects of the Invention In the semiconductor device according to the present invention, since the electrode contact window has two steps, each step can be made small and step coverage defects can be easily prevented. Although the above description concerns the connection between the wiring and the semiconductor substrate, the present invention can also be applied to the connection between the upper electrode and the lower electrode in a multilayer wiring structure.

[Brief explanation of the drawing]

FIG. 1A is a plan view of the semiconductor device when the insulating film is etched using the second resist layer as a mask), FIG. 1B is a cross-sectional view taken along line IB-IB in FIG. Figure 2A is a plan view of the semiconductor device when etching is performed using the second resist layer as a mask, and Figure 2B is a cross-sectional view taken along line nB-1[B in the second figure. 3A is a plan view of the semiconductor device when wiring is formed, FIG. 3B is a cross-sectional view taken along line IIB-11iB in FIG. 38, and FIG. 4A is a cross-sectional view of the semiconductor device in another embodiment. 2 is a plan view of the semiconductor device when etching is performed using the resist layer as a mask, and FIGS. 4B and 14C are along the line ■B-IVB in FIG. 48.
5A is a plan view of the semiconductor device when wiring is formed in another embodiment, and FIG. 5B is a sectional view taken along the line VB-
It is a sectional view at VB. l... Semiconductor substrate, 3... Insulating film, 4... Second resist layer, 6... Groove, 7... Second resist layer, 9...
...Exterior window, 10...Wiring. Patent applicant Fujitsu Ltd. Patent attorney Akira Aoki Patent attorney Kazuyuki Nishidate 1) Yukio Patent attorney Akira Yamaguchi No. 5A

Claims (1)

[Scope of Claims] 1. On an insulating film in which an electrode contact window is formed, an electrode wiring extending in contact with a contact area within the outer window of the electrode contact, and the insulating film is connected to the edge of the electrode contact window. A semiconductor device characterized in that the electrode wiring extends stepwise along the longitudinal direction of the electrode wiring. 2. In a method for manufacturing a semiconductor device including a step of forming an electrode contact window in an insulating film, selectively etching the insulating film to form a longitudinal electrode wiring including a region corresponding to a conductive portion to be exposed in the electrode contact window. forming a groove that widens on both sides in the direction, and then selectively etching away the insulating film on the underlying conductive portion to be exposed within the groove to complete the electrode contact window. A method for manufacturing a featured semiconductor device.