JPH0434955A - Integrated circuit device - Google Patents
Integrated circuit deviceInfo
- Publication number
- JPH0434955A JPH0434955A JP14083590A JP14083590A JPH0434955A JP H0434955 A JPH0434955 A JP H0434955A JP 14083590 A JP14083590 A JP 14083590A JP 14083590 A JP14083590 A JP 14083590A JP H0434955 A JPH0434955 A JP H0434955A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- interlayer insulating
- wiring
- opening part
- lower wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010410 layer Substances 0.000 claims abstract description 32
- 239000011229 interlayer Substances 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000004065 semiconductor Substances 0.000 claims abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052782 aluminium Inorganic materials 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 4
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、集積回路装置に間する。[Detailed description of the invention] [Industrial application field] The present invention relates to an integrated circuit device.
従来の集積回路装置は、第２図に示すように、シリコン
基板１の上に設けた酸化シリコン膜２の上に選択的に下
層配線３を設け、下層配線３を含む表面に層間絶縁膜４
を設ける。次に、下層配線３の上の層間絶縁膜４を選択
的にエツチングして開口部７を設け、開口部７の下層配
線３と接続する上層配線６を設ける。In the conventional integrated circuit device, as shown in FIG. 2, a lower layer wiring 3 is selectively provided on a silicon oxide film 2 provided on a silicon substrate 1, and an interlayer insulating film 4 is provided on the surface including the lower layer wiring 3.
will be established. Next, the interlayer insulating film 4 above the lower layer wiring 3 is selectively etched to form an opening 7, and an upper layer wiring 6 connected to the lower layer wiring 3 in the opening 7 is provided.
ここで、開口部７の上端部近傍の上層配線６の膜厚が薄
くなっている。Here, the film thickness of the upper layer wiring 6 near the upper end of the opening 7 is thinner.
上述した従来の集積回路装置は、開口部上端に接する上
層配線が薄くなっているため、薄い部分でエレクトロマ
イグレーションをひきおこし、集積回路の信頼性を低下
させるという問題点がある。The above-described conventional integrated circuit device has a problem in that since the upper layer wiring in contact with the upper end of the opening is thin, electromigration occurs in the thin portion, reducing the reliability of the integrated circuit.
本発明の集積回路装置は、半導体基板上に設けた絶縁膜
の上に形成した下層配線と、前記下層配線を含む表面に
設けた層間絶縁膜と、前記下層配線上の前記層間絶縁膜
に設けた環状の開口部と、前記開口部の前記下層配線に
接続して前記層間絶縁膜上に設けた上層配線とを有する
。The integrated circuit device of the present invention includes a lower layer wiring formed on an insulating film provided on a semiconductor substrate, an interlayer insulating film provided on a surface including the lower layer wiring, and a layer provided on the interlayer insulating film on the lower layer wiring. and an upper layer wiring connected to the lower layer wiring of the opening and provided on the interlayer insulating film.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の断面図である。FIG. 1 is a sectional view of one embodiment of the present invention.
第１図に示すように、シリコン基板１の上に設けた酸化
シリコン膜２の上に選択的にアルミニウム層からなる下
層配線３を設け、下層配線３を含む表面に層間絶縁膜４
を設ける。次に、下層配線３の上の層間絶縁膜４を選択
的にエツチングして中央に層間絶縁膜４の一部を残した
環状の開口部５を設ける。次に、開口部５を含む表面に
アルミニウム層を堆積して選択的にエツチングし、開口
部の下層配線３と電気的に接続する上層配線６を設ける
。As shown in FIG. 1, a lower layer wiring 3 made of an aluminum layer is selectively provided on a silicon oxide film 2 provided on a silicon substrate 1, and an interlayer insulating film 4 is formed on the surface including the lower layer wiring 3.
will be established. Next, the interlayer insulating film 4 on the lower wiring 3 is selectively etched to form an annular opening 5 in which a part of the interlayer insulating film 4 remains in the center. Next, an aluminum layer is deposited on the surface including the opening 5 and selectively etched to provide an upper layer wiring 6 electrically connected to the lower layer wiring 3 in the opening.
ここで、開孔部５の中央に層間絶縁膜４の一部が残され
ているため、上層配線６の上面に凹部が形成されず、従
って開口部５の上端で上層配線６が薄くなることを防止
できる。Here, since a part of the interlayer insulating film 4 remains in the center of the opening 5, no recess is formed on the upper surface of the upper layer wiring 6, and therefore the upper layer wiring 6 becomes thinner at the upper end of the opening 5. can be prevented.
以上説明したように本発明は、上層配線と下層配線が接
続する開口部の上端で厚さを厚く保つことができ、エレ
クトロマイグレーションを回避して、集積回路装置の信
頼性を向上させるという効果を有する。As explained above, the present invention can maintain a thick thickness at the upper end of the opening where the upper layer wiring and the lower layer wiring connect, thereby avoiding electromigration and improving the reliability of the integrated circuit device. have
第１図は本発明の一実施例の断面図、第２図は従来の集
積回路装置の断面図である。
１・・・シリコン基板、２・・・酸化シリコン膜、３・
・・下層配線、４・・・層間絶縁膜、５・・・開口部、
６・・・上層配線、７・・・開口部。FIG. 1 is a sectional view of an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional integrated circuit device. 1... Silicon substrate, 2... Silicon oxide film, 3.
... lower layer wiring, 4 ... interlayer insulating film, 5 ... opening,
6... Upper layer wiring, 7... Opening.
Claims (1)
と、前記下層配線を含む表面に設けた層間絶縁膜と、前
記下層配線上の前記層間絶縁膜に設けた環状の開口部と
、前記開口部の前記下層配線に接続して前記層間絶縁膜
上に設けた上層配線とを有することを特徴とする集積回
路装置。a lower layer wiring formed on an insulating film provided on a semiconductor substrate; an interlayer insulating film provided on a surface including the lower layer wiring; an annular opening provided in the interlayer insulating film on the lower layer wiring; An integrated circuit device comprising an upper layer wiring connected to the lower layer wiring in the opening and provided on the interlayer insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14083590A JPH0434955A (en) | 1990-05-30 | 1990-05-30 | Integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14083590A JPH0434955A (en) | 1990-05-30 | 1990-05-30 | Integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0434955A true JPH0434955A (en) | 1992-02-05 |
Family
ID=15277823
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14083590A Pending JPH0434955A (en) | 1990-05-30 | 1990-05-30 | Integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0434955A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10350137B4 (en) * | 2002-10-30 | 2017-02-09 | Denso Corporation | Semiconductor device |
-
1990
- 1990-05-30 JP JP14083590A patent/JPH0434955A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10350137B4 (en) * | 2002-10-30 | 2017-02-09 | Denso Corporation | Semiconductor device |
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