JPS6173350A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the flatness in an interlayer connection portion, by forming an uppermost conductive layer on a substrate into a protrudent shape, providing an interlayer insulation film around the conductive layer so as to burry the same and adhering a wiring layer thereon to effect the interlayer connection. CONSTITUTION:An SiO2 layer 4 is adhered on an Si substrate 1 provided with a base region 2 and an emitter region 3, and is provided with contact holes. A first conductive layer 5 as a first wiring layer, a heterogeneous conductive layer 8 having a smaller etching rate and a second conductive layer 9 are adhered successively in that order. The layers are then patterned and removed by etching except the layer 9 in the interlayer connection portion which is left as a protrusion. Electrodes 4E, 5B and 5C are formed by patterning. PSG6 is then adhered thereon as an interlayer insulation film while the top of the protrudent layer 9 is exposed. A second wiring layer 7 is adhered thereon to cover the exposed portion of the layer 9, and patterned into a wiring pattern. In this manner, the interlayer connection portion having a good flatness is obtained, and therefore a highly integrated and high density semiconductor device can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming multilayer wiring in a semiconductor manufacturing process.

In recent years, as large-scale integrated circuits (LSI) have become highly integrated, multilayer wiring has come into widespread use. In this case, there is a need for a manufacturing process that can easily and reliably connect the layers of multilayer wiring, and that can flatten the substrate.

[Conventional technology]

FIGS. 2(a) and 2(b) are cross-sectional views of a substrate showing interlayer connections according to a conventional example in the order of steps.

In FIG. 2 (al), p-type impurities are introduced into an n-type silicon (Si) substrate 1 to form a base region 2, and further n-type impurities are introduced to form an emitter region 3.

Next, a thermally oxidized silicon dioxide (SIO□) layer 4 is deposited, contact windows for the emitter, base, and collector are opened, and an aluminum (AI) layer 5 is deposited as a first wiring layer and buttered. Emitter electrode 5E, base electrode 5
B. Forming collector electrode 5C.

Next, a phosphosilicate glass (PSG) layer 6 is deposited as an insulating layer between the eyebrows and patterned to open an interlayer connection portion.

In FIG. 2(b), an AI layer 7 is deposited as a second wiring layer covering the opening and patterned into a wiring pattern.

[Problem that the invention seeks to solve]

In the conventional example, a connection hole (through hole) is opened in an interlayer insulating layer deposited on a first wiring layer to expose the first wiring layer, and a second wiring layer is deposited on top of the first wiring layer. Since interlayer connections are made, the opening area becomes large, and the flatness in this portion is poor, thus hindering high integration and high density of semiconductor devices.

[Means for solving problems]

The above problem can be solved by depositing a first wiring layer on the substrate, which has a different type of conductive layer interposed between the conductive layers and having a lower etching rate than these conductive layers, and After the conductive layer is removed leaving the interlayer connection, an interlayer insulating layer is deposited to expose the top of the remaining conductive layer, and a second layer is formed covering the top of the conductive layer and the interlayer insulating layer. This is achieved by the method of manufacturing a semiconductor device according to the invention, which deposits a wiring layer.

[Effect]

In the first wiring layer, the conductive layer of a different type with a low etching rate acts as a stopper when etching the conductive layer on the outermost surface, and by patterning the conductive layer on the outermost surface with a convex pattern using a normal glue-on-glue process. form into a shape.

The periphery of the convexly formed outermost conductive layer is filled with an interlayer insulating layer, and the second wiring layer is deposited thereon to perform the glabella connection, so that the substrate surface becomes extremely flat.

〔Example〕

FIGS. 1A and 1B are cross-sectional views of a substrate showing the interlayer connection according to the present invention in the order of steps.

In FIG. 1(a), p-type impurities are introduced into an n-type Si substrate 1 to form a base region 2, and further n-type impurities are introduced to form an emitter region 3.

Next, a 5102 layer 4 is deposited by thermal oxidation, and the emitter and
A1 layer 5 (first conductive layer) with a thickness of 6,000 people as the first wiring layer, with contact windows for the base and collector opened;
1500mm thick titanium tungsten (TiW) layer 8
(Different 4-conductor layer with small etching rate), thickness 6
41 layers 9 (second conductive layer) of 0.000 are deposited one after another.

Each layer of the first wiring layer was deposited using argon (Ar) gas at 2×10 Torr and a frequency of 13.56 MHz.
, by sputtering with a power of 300W.

Next, by patterning, the 41st layer 9 of the interlayer connection portion is left in a convex shape, and the other portions are removed by etching.

Next, patterning is performed to form an emitter electrode 5E, a base electrode 5B, and a collector electrode 5C.

In FIG. 1(b), a PSG layer 6 is deposited as an insulating layer between the eyebrows, and the top of the convex 41 layer 9 of the interlayer connection portion is exposed.

This method is carried out, for example, as follows. After depositing the PSG layer 6 on the entire surface of the substrate, a resist is applied thickly thereon so that the substrate surface is flat, and reactive ion etching ( By anisotropic etching using RIE method, etching is performed only in the direction perpendicular to the substrate until the top of the convex 41 layer 9 of the interlayer connection portion is exposed. By etching in this manner, the surface of the PSG layer 6 is planarized.

A second wiring layer 7° is deposited to cover the exposed portion of the A1 layer 9, and patterned into a wiring pattern.

For etching each layer of the first wiring layer, the etching gas for AI was boron trichloride (BCl2) and phosphorus trichloride (PC+3).
The processing was carried out using fluorine (F) as the Ti-etching gas and applying a power of 300 mm at a frequency of 13.56 MH2 at 0.15 Torr.

In the example, TiW was used as the dissimilar conductive layer with a small etching rate, but titanium nitride (TiW) was used instead.
Even if N), titanium (Ti), etc. are used, the gist of the invention does not change.

〔Effect of the invention〕

As explained in detail above, according to the present invention, since interlayer connections are made without forming through holes in the interlayer insulating layer deposited on the first wiring layer, the flatness of the interlayer connection portions is good, and therefore It becomes possible to increase the integration and density of semiconductor devices.

[Brief explanation of drawings]

FIGS. 1A and 1B are cross-sectional views of a substrate showing interlayer connections according to the present invention in order of process, and FIGS. 2A and 2B are cross-sectional views of a substrate showing interlayer connections according to a conventional example in order of processes. In, 1 is an n-type Si substrate, 2 is a base region 23 is an emitter region, 4 is a STO□ layer, 5 is an A1 layer, (5, 8,
9 is the first wiring layer) 8 is the TiW layer, 9 is the first layer, 5E is the emitter electrode, 5B is the base electrode, 5C is the collector electrode, and 7 is the A1 layer (second wiring layer).

Claims (1)

[Claims] A first wiring layer is formed by interposing a different type of conductive layer with a lower etching rate than these conductive layers between the conductive layers, and the uppermost conductive layer is connected to the interlayer connection portion. After removing the remaining conductive layer, depositing an interlayer insulating layer so as to expose the top of the remaining conductive layer, and depositing a second wiring layer covering the top of the conductive layer and the interlayer insulating layer. A method for manufacturing a semiconductor device, characterized by: