JPH0235731A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0235731A
JPH0235731A JP18604388A JP18604388A JPH0235731A JP H0235731 A JPH0235731 A JP H0235731A JP 18604388 A JP18604388 A JP 18604388A JP 18604388 A JP18604388 A JP 18604388A JP H0235731 A JPH0235731 A JP H0235731A
Authority
JP
Japan
Prior art keywords
wiring
film
titanium nitride
oxide film
cvd
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18604388A
Other languages
Japanese (ja)
Inventor
Yukio Morozumi
幸男 両角
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP18604388A priority Critical patent/JPH0235731A/en
Publication of JPH0235731A publication Critical patent/JPH0235731A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To completely prevent the generation of hillock, and improve productivity, utility and reliability by a method wherein, after a second conductor thin film of different kind and a CVD insulating film are stacked on a lamination film in which wiring is formed, these films are left as side walls on the wiring side surface by anisotropic etching. CONSTITUTION:In an oxide film 12 on a semiconductor substrate 11, a contact hole is formed, and aluminum silicon alloy 13 and titanium nitride 14 for wiring use are continuously sputtered; by using photoresist as a mask, this lamination film is subjected to dry etching of halogen system gas and to simultaneous patterning; after a second titanium nitride 15 is sputtered, a CVD oxide film 15 using SiH4 and O2 is stacked; the whole surface is anisotropically etched by dry etcher using CF4 or C2F6, and the titanium nitride 15 and the CVD oxide film 16 are left as side walls of the wiring patterned in the preceding process. In this case, although the the CVD oxide film 16 and the titanium nitride 15 are etched at the same time in the same chamber, the titanium oxide 15 on the side wall is covered with the side wall of the CVD oxide film 16, and surely left with excellent reproducibility.

Description

【発明の詳細な説明】 〔産業上の利用分野] 本発明は、半導体装置の特に配線の形成方法に関するも
のである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor device, particularly to a method for forming wiring.

[従来の技術] 従来微細化された半導体装置の配線方法は、第2図の如
く、例えば半導体素子がJヒ成された半導体基板21上
の酸化膜22にコンタクトホールが形成され、配線用の
アルミニウム合金23を0.5〜1.0μm、ヒロック
とハレーション防止の為に窒化チタン24をa、1μm
程度スパッタする(第2図(a))。次に7オトレジス
トをマスクにして、前記積層膜をドライエツチングしパ
ターニングした後、第2の窒化チタン25を0.1μm
程度スハッタする(第2図(h))。続いてay4ガス
を用いた異方性ドライエツチャーで全面エツチングし、
前工程でパターニングした配線に側壁として窒化チタン
25を残し、後工程の熱処理で発生する横方向ヒロック
が、配線リークや1絶縁膜のボイドの原因とならないよ
うにしでいる(第2図(C))。その後、層間膜あるい
はパシベーション膜としてOVD絶縁膜を成長させてい
る。
[Prior Art] Conventionally, as shown in FIG. 2, in a wiring method for a miniaturized semiconductor device, a contact hole is formed in an oxide film 22 on a semiconductor substrate 21 on which a semiconductor element is J-heated, and a contact hole is formed for wiring. Aluminum alloy 23 has a thickness of 0.5 to 1.0 μm, and titanium nitride 24 has a thickness of 1 μm to prevent hillocks and halation.
Sputtering occurs to some extent (FIG. 2(a)). Next, using the photoresist 7 as a mask, the laminated film is dry etched and patterned, and then a second titanium nitride 25 is deposited to a thickness of 0.1 μm.
(Fig. 2 (h)). Next, the entire surface was etched with an anisotropic dry etcher using ay4 gas,
Titanium nitride 25 is left as a sidewall on the wiring patterned in the previous process to prevent lateral hillocks generated during the heat treatment in the post process from causing wiring leakage or voids in the first insulating film (Figure 2 (C)). ). Thereafter, an OVD insulating film is grown as an interlayer film or passivation film.

[発明が解決しようとする課題] しかしながら従来技術では、アルミニウム合金の側面形
状が急峻であり、スパックしまた第2の窒化膜タン25
の付き回りが悪く、全面異方性エツチングの際に1.ヒ
ロックの抑制効果のある側壁として十分に残らず、その
生産制浦性、再現性も極めて悪く、実用化に供し難い上
、信頼性も問題となっている。
[Problems to be Solved by the Invention] However, in the prior art, the aluminum alloy has a steep side surface shape, which causes spatter and the second nitride film tongue 25.
The coverage is poor, and when performing anisotropic etching on the entire surface, 1. Not enough remains as a side wall that has the effect of suppressing hillocks, and its production control and reproducibility are extremely poor, making it difficult to put it into practical use and causing reliability problems.

しかるに本発明は、かかる課題を解決するものであり、
その目的とするところは、ヒロックを完全に防止l−1
生産性、実用性及び信頼性の高い微細配線を安定して供
給するものである。
However, the present invention solves these problems,
The purpose is to completely prevent hillocks l-1
It stably supplies fine wiring with high productivity, practicality, and reliability.

[課題を解決するための手段] 本発明の半導体装置の製造方法は、半導体素子が形成さ
れた半導体基板上に、絶縁膜を介してアルミニウムやそ
の合金の配線を設けてなる半導体装置に於いて、少なく
ともアルミニウムやその合金と異種導電材薄膜を連続し
て形成する工程、前記積層膜を同時にバターニングして
配線を形成する工程、第2の異種導電材N膜とOVD絶
縁膜を積層する工程、前記第2の導電材薄IIりとOV
D絶縁膜を異方性エツチングして配線側面に、前記第2
の導電膜とOV D絶縁膜を側壁とり、で残す工程を有
したことを特徴とする。
[Means for Solving the Problems] The method for manufacturing a semiconductor device of the present invention is a semiconductor device in which wiring made of aluminum or its alloy is provided on a semiconductor substrate on which a semiconductor element is formed, via an insulating film. , a step of successively forming at least aluminum or its alloy and a thin film of a different conductive material, a step of simultaneously patterning the laminated film to form wiring, and a step of laminating a second N film of a different conductive material and an OVD insulating film. , the second conductive material thin II and OV
The D insulating film is anisotropically etched to form the second layer on the side surface of the wiring.
The method is characterized in that it includes a step of removing the conductive film and the OVD insulating film from the sidewalls and leaving them on the sidewalls.

[実施例コ 以下本発明の実施の工程を、第2図−a%Cに基づいて
詳細に説明すイー。
[Example 2] Hereinafter, the steps for implementing the present invention will be explained in detail based on FIG. 2-a%C.

サフミクロンルールの集積回路製造に於いて、トランジ
スタや抵抗等の半導体素子が形成された半導体基板11
Fの酸化IFJI2にフンククトホールが開孔されてお
り、配線用のアルミ;・)ムーシリコン合金1ろを約1
.0μm1続いて窒化チタン14を約0.1μm連続ス
パッタする(第1図(a))。次にフォトレジス1−を
マスクにして、前記債層戻をC62やB Ot、の様な
ハロゲン系ガスでドライエツチャーして同時バターニン
グした後、第2の窒化チタン15を約0.1μmスパッ
タ後5LH4とO7を用いたOVD酸化膜18を約0、
6 μm 積層する(第2図(h))。続いてOF。
Semiconductor substrate 11 on which semiconductor elements such as transistors and resistors are formed in integrated circuit manufacturing according to the safmicron rule
A funkkut hole is opened in the oxidized IFJI2 of F, and aluminum for wiring;
.. Subsequently, titanium nitride 14 is continuously sputtered to a thickness of about 0.1 μm (FIG. 1(a)). Next, using the photoresist 1- as a mask, the bond layer was dry-etched and buttered with a halogen gas such as C62 or BOt, and then a second titanium nitride layer 15 was deposited to a thickness of about 0.1 μm. After sputtering, the OVD oxide film 18 using 5LH4 and O7 is
A layer of 6 μm is layered (Fig. 2 (h)). Followed by OF.

もしくは02F、を用いたドライエツチャーで全面異方
性エツチングし、前工程でバターニングした配線に側壁
として窒化チタン15とOvD酸化+i% 16を残す
(第6図(C))。この時側壁形成の工程は、OVD酸
化膵16と窒化チタン15を同一チャンバーで同時にエ
ツチングするが、側壁の窒化チタン15はCvD酸化@
16の側壁にカバーされ、再現性よく確実に残る。その
後パシベーション膜としてOVDにより、psa膜とプ
ラズマ窒化膜を成長させた。
Alternatively, the entire surface is anisotropically etched with a dry etcher using 02F, leaving titanium nitride 15 and OvD oxidation +i% 16 as side walls on the wiring patterned in the previous step (FIG. 6(C)). At this time, in the process of forming the side wall, the OVD oxidized pancreas 16 and the titanium nitride 15 are etched simultaneously in the same chamber, but the titanium nitride 15 on the side wall is etched by the CvD oxidized
16 side walls and remains reliably with good reproducibility. Thereafter, a PSA film and a plasma nitride film were grown as passivation films by OVD.

この他の実施例として、アルミニウム合金を用いた2層
配線構造の下層配線として本発明を適用したが、窒化チ
タンの[[I壁を再現性良く残すことが出来、耐ヒロッ
クやマイグレーション効果も向上し、更にOVD酸化膜
の側壁により、後工程で形成する層間膜や上層配線の平
担性を向上する効果もあった。
As another example, the present invention was applied to the lower layer wiring of a two-layer wiring structure using an aluminum alloy, but the [[I wall of titanium nitride can be left with good reproducibility, and the hillock resistance and migration effect are improved. Furthermore, the sidewalls of the OVD oxide film also had the effect of improving the flatness of interlayer films and upper layer interconnections formed in subsequent steps.

尚、ヒロック防止膜とl−で窒化チタンを用いたが、こ
れはフォトリソのハレーション防止も兼ねている為で有
り、これに限らずモリブデン、タングステン、チタンの
様な高融点金属やそのX71Jサイド等の導電材でも応
用できる。又アルミニウム合金配線としては、アルミニ
ウムーシリコンニ限らず銅、白金等やこれらの混合物の
合金でも良く、その形成方法は、加熱、無加熱あるいは
バイアスの有無に限定されない。更に配線の下に、バリ
ア金属を敷いた場合にも適用できる。
Titanium nitride was used for the hillock prevention film and l-, but this is also to prevent halation in photolithography, and is not limited to titanium nitride. It can also be applied to conductive materials. Further, the aluminum alloy wiring is not limited to aluminum-silicon, but may also be an alloy of copper, platinum, etc., or a mixture thereof, and the method of forming it is not limited to heating, non-heating, or with or without bias. Furthermore, it can also be applied when a barrier metal is placed under the wiring.

[発明の効果コ 以上の如く本発明によれば、アルミニウムやその合金配
線の少なくとも上面、(ll1面を確実に異種導電材薄
膜で被うことが可能となり、生産性、信頼性の高い微細
半導体装置の実用化と安定供給が可能となる。
[Effects of the Invention] As described above, according to the present invention, it is possible to reliably cover at least the upper surface (ll1 side) of aluminum or its alloy wiring with a thin film of a different type of conductive material, thereby producing a fine semiconductor with high productivity and reliability. This will enable practical use and stable supply of the device.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(α)〜CC)は、本発明の一実施例による配線
形成工程を示す概略断面図である。 第2図(α)〜(C)は、従来の配線形成工程を示す概
略断面図である。        °ゝ・11.21・
・・・・・半導体基板 12.22・・・・・・酸化膜 13.23・・・・・・アルミニウム合金膜14.24
・・・・・・窒化チタン 15.25・−・・−・第2の窒feチタン26   
・・・・・(コV D酸化膜以上
FIGS. 1(α) to CC) are schematic cross-sectional views showing a wiring forming process according to an embodiment of the present invention. FIGS. 2(α) to 2(C) are schematic cross-sectional views showing a conventional wiring forming process. °ゝ・11.21・
... Semiconductor substrate 12.22 ... Oxide film 13.23 ... Aluminum alloy film 14.24
...Titanium nitride 15.25 --- Second fe titanium nitride 26
・・・・・・(CoV D oxide film or more

Claims (1)

【特許請求の範囲】[Claims] 半導体素子が形成された半導体基板上に、絶縁膜を介し
てアルミニウムやその合金の配線を設けてなる半導体装
置に於いて、少なくともアルミニウムやその合金と異種
導電材薄膜を連続して形成する工程、前記積層膜を同時
にパターニングして配線を形成する工程、第2の異種導
電材薄膜とCVD絶縁膜を積層する工程、前記第2の導
電材薄膜とCVD絶縁膜を異方性エッチングして配線側
面に、前記第2の導電膜とCVD絶縁膜を側壁として残
す工程を有したことを特徴とする半導体装置の製造方法
In a semiconductor device in which wiring made of aluminum or its alloy is provided on a semiconductor substrate on which a semiconductor element is formed via an insulating film, a step of continuously forming at least aluminum or its alloy and a thin film of a different conductive material; A step of simultaneously patterning the laminated film to form a wiring, a step of laminating a second thin film of a different type of conductive material and a CVD insulating film, and anisotropic etching of the second thin film of a conductive material and a CVD insulating film to form a side surface of the wiring. A method of manufacturing a semiconductor device, comprising the step of leaving the second conductive film and the CVD insulating film as side walls.
JP18604388A 1988-07-26 1988-07-26 Manufacture of semiconductor device Pending JPH0235731A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18604388A JPH0235731A (en) 1988-07-26 1988-07-26 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18604388A JPH0235731A (en) 1988-07-26 1988-07-26 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0235731A true JPH0235731A (en) 1990-02-06

Family

ID=16181399

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18604388A Pending JPH0235731A (en) 1988-07-26 1988-07-26 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0235731A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0321026A (en) * 1989-06-19 1991-01-29 Fujitsu Ltd Semiconductor device low in parasitic capacitance in wiring and its manufacture
KR100268949B1 (en) * 1997-12-29 2000-10-16 김영환 Method for forming contact hole of semiconductor device
US6383942B1 (en) 1999-03-11 2002-05-07 Kabushiki Kaisha Toshiba Dry etching method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0321026A (en) * 1989-06-19 1991-01-29 Fujitsu Ltd Semiconductor device low in parasitic capacitance in wiring and its manufacture
KR100268949B1 (en) * 1997-12-29 2000-10-16 김영환 Method for forming contact hole of semiconductor device
US6383942B1 (en) 1999-03-11 2002-05-07 Kabushiki Kaisha Toshiba Dry etching method
KR100363591B1 (en) * 1999-03-11 2002-12-05 가부시끼가이샤 도시바 Method of dry etching

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