JPH0536842A - Multilayer interconnection formation method - Google Patents

Abstract

PURPOSE:To contrive a reduction in the resistance of an interlayer connection part in a multilayer wiring formation method comprising a method. wherein an interlayer insulating film is etched back to make the interlayer connection part expose. CONSTITUTION:A single-layer wiring material consisting of Al or an Al alloy or the like is applied on the surface of an insulating film 12 covering a substrate 10 to perform a patterning, whereby a first wiring layer 30 is formed, but the wiring material is etched, before or after this layer 30 is formed, to form an inter-layer connection part 30a of a form projecting from the layer 30. After an interlayer insulating film 36 is formed on the surface over the substrate, this film 36 is etched back to make the part 30a expose. After this, a second wiring layer 40 is formed on the surface over the substrate in such a way that it is connected with the part 30a. As one part of the first 30 is used as the part 30a, a reduction in the connection resistance becomes possible.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a multi-layered wiring used for manufacturing an LSI or the like. It is possible to reduce the connection resistance by using as an interlayer connecting portion.

[0002]

2. Description of the Related Art Conventionally, a method shown in FIGS. 9 to 11 is known as a highly integrated and highly reliable multilayer wiring forming method (see, for example, Japanese Patent Application Laid-Open No. 2-111052).

In the process of FIG. 9, a wiring material such as Al and a conductive material such as poly-Si are sequentially deposited on the insulating film 12 covering the semiconductor substrate 10, and then a desired wiring pattern is formed on the deposition layer. A resist layer 18 is formed. Then, the deposition layer is patterned by a selective etching process using the resist layer 18 as a mask to form the first wiring layer 14 and the conductive layer 16. After that, the resist layer 18 is removed.

Next, in the process of FIG. 10, a resist layer 20 is formed on the conductive layer 16 in accordance with a desired interlayer connection pattern. Then, the conductive layer 16 is patterned by a selective etching process using the resist layer 20 as a mask to form the interlayer connection portion 16A. After that, the resist layer 20 is removed.

Next, in the step shown in FIG.
Interlayer connection portion 16 using G (spin on glass) or the like
An interlayer insulating film 22 is formed in a substantially flat shape so as to cover A. Then, the interlayer insulating film 22 is etched back to expose the interlayer connecting portion 16A and leave a part of the interlayer insulating film 22 substantially flat. After that, the second wiring layer 24 is formed on the remaining portion of the interlayer insulating film 22 so as to be connected to the interlayer connecting portion 16A.

The selective etching process using the resist layer 20 as a mask may be performed before the selective etching process using the resist layer 18 as a mask, and even in this case, as shown in FIG. The wiring layer 14 having

[0007]

According to the above-mentioned conventional method, the interlayer connecting portion 16A is made of poly-S different from the wiring material such as Al.
Since it is formed of a conductive material such as i, the connection resistance is high.

An object of the present invention is to reduce the resistance of the interlayer connecting portion in the method for forming a multilayer wiring including the etching back of the interlayer insulating film to expose the interlayer connecting portion as described above.

[0009]

A method for forming a multilayer wiring according to the present invention comprises: (a) a step of forming a first wiring layer made of a single-layer wiring material on the surface of an insulating film covering a substrate; and (b) Forming an interlayer connection part protruding from a part of the first wiring layer by selectively etching the wiring material before or after forming the first wiring layer;
(C) a step of forming an interlayer insulating film on the insulating film so as to cover the first wiring layer and the interlayer connecting portion; and (d) etching back the interlayer insulating film to expose the interlayer connecting portion. And leaving a part of the interlayer insulating film around the interlayer connecting part, and (e) a second wiring layer so as to be connected to the interlayer connecting part on the remaining part of the interlayer insulating film. And a step of forming.

[0010]

According to the method of the present invention, a part of the first wiring layer made of a single-layer wiring material is processed into a convex shape by selective etching, and the part is used as an interlayer connecting portion. Therefore, the interlayer connection portion is formed of the wiring material having the same low resistivity as that of the first wiring layer, and the connection resistance can be reduced.

[0011]

1 to 5 show a multilayer wiring forming method according to an embodiment of the present invention, and steps (1) to (5) corresponding to the respective drawings will be sequentially described.

(1) Al is formed on the surface of the insulating film 12 such as silicon oxide covering the surface of the semiconductor substrate 10 such as silicon.
Alternatively, after a wiring material such as an Al alloy is deposited to form the wiring material layer 30A, a resist layer 3 corresponding to a desired wiring pattern is formed.
Wiring material layer 3 by selective etching treatment using 2 as a mask
0A is patterned to form the first wiring layer 30.

(2) Next, a resist layer 34 is formed on a part of the wiring layer 30 according to a desired interlayer connection pattern. An example of the plane pattern of the resist layer 34 at this time is shown in FIG.
Is shown in. After that, the wiring layer 30 is selectively etched halfway in the thickness direction using the resist layer 34 as a mask to form an interlayer connection portion 30a formed of a part of the wiring layer 30. Then, the resist layer 34 is removed.

(3) Next, a method of depositing and forming an insulating film of silicon oxide or the like by the CVD method or a method of depositing a thin insulating film and then rotating a fluid such as SOG (spin-on-glass) and polyimide. An interlayer insulating film 36 is formed in a substantially flat shape on the upper surface of the substrate so as to cover the interlayer connection portion 30a and the wiring layer 30 by a coating method or the like. The etching selection ratio with the film 36 is 1 on the interlayer insulating film 36.
A coating film 38 of photoresist or the like close to the above is formed to further flatten the upper surface of the substrate. The coating film 38 is provided in order to obtain good flatness in the later-described etch-back process and may be omitted, but if omitted, the flatness deteriorates.

(4) Next, the upper surface of the substrate is etched back from the side of the coating film 38 to expose the inter-layer connection portion 30a, and a part of the inter-layer insulation film 36 is left flat around it.

(5) Thereafter, a wiring material such as Al or Al alloy is deposited on the remaining portion of the interlayer insulating film 36 and patterned to form the second wiring so as to be connected to the interlayer connecting portion 30a. Form layer 40. As a result, the first and second wiring layers 30 and 40 are connected to each other via the low-resistance interlayer connecting portion 30a which is a part of the wiring layer 30. The wiring layer 40 may have a laminated structure of a refractory metal such as Ti or W and an Al alloy.

7 to 8 show a modification of the first layer patterning process. The same parts as those in FIGS. 1 and 2 are designated by the same reference numerals, and detailed description thereof will be omitted.

In the step of FIG. 7, the wiring material layer 30A on the insulating film 12 is selectively etched by using the resist layer 42 corresponding to a desired interlayer connection pattern as a mask to selectively form the interlayer connection portion 30.
a is formed. Then, the resist layer 42 is removed.

Next, in the process of FIG. 8, the wiring material layer 3 is formed using the resist layer 44 corresponding to the desired wiring pattern as a mask.
0A is patterned to form the first wiring layer 30.
Then, the resist layer 44 is removed.

The first wiring layer 30 having the interlayer connection portion 30a can be obtained also by the method shown in FIGS. After the step of FIG. 8, it is possible to move to the step of FIG.

[0021]

As described above, according to the present invention, the lower wiring layer of the upper and lower wiring layers is formed of a single-layer wiring material, and a part of the lower wiring layer is formed into a convex shape by selective etching. Since this is processed into a part and used as an interlayer connection part, the connection resistance can be reduced, and an effect that a low resistance multilayer wiring can be realized can be obtained. In addition, since the lower wiring layer is formed of a single wiring material, there is an advantage that the process is simplified.

[Brief description of drawings]

[Figure 1]

FIG. 5 is a substrate cross-sectional view showing a method for forming a multilayer wiring according to an embodiment of the present invention.

FIG. 6 is a top view of the substrate corresponding to FIG.

[Figure 7] ~

FIG. 8 is a substrate cross-sectional view showing a modified example of the first-layer patterning process.

[Fig. 9]

FIG. 11 is a cross-sectional view of a substrate showing a conventional multilayer wiring forming method.

[Explanation of symbols]

10: semiconductor substrate, 12, 36: insulating film, 30, 40:
Wiring layer, 30a: Interlayer connection portion.

Claims (1)

Claims: (a) a step of forming a first wiring layer made of a single-layer wiring material on the surface of an insulating film covering a substrate; and (b) forming the first wiring layer. By selectively etching the wiring material before or after formation, the first
A step of forming an interlayer connection part projecting from a part of the wiring layer, and (c) forming an interlayer insulation film on the insulating film so as to cover the first wiring layer and the interlayer connection part. (D) a step of etching back the interlayer insulating film to expose the interlayer connecting portion and leaving a part of the interlayer insulating film around the interlayer connecting portion, and (e) forming the interlayer insulating film. A step of forming a second wiring layer on the remaining portion so as to be connected to the interlayer connection portion.