JPS61199649A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61199649A JPS61199649A JP4050085A JP4050085A JPS61199649A JP S61199649 A JPS61199649 A JP S61199649A JP 4050085 A JP4050085 A JP 4050085A JP 4050085 A JP4050085 A JP 4050085A JP S61199649 A JPS61199649 A JP S61199649A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- interlayer insulating
- metal
- metal wiring
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体集積回路の多層配線の形成方法に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming multilayer wiring for semiconductor integrated circuits.
従来の半導体装置では、第２図−）および（ｂ）に示す
ように、拡散の施された半導体基体１表面の酸化膜３上
にＦ層配線２ｔ−形成後、その上に層間絶縁ｇ１を形成
し、この眉間絶縁膜ｌにスルーホールをあけ、１回の金
属蒸着でスルーホールを介して接続される上層配線６ｔ
一層間絶縁膜２上に形成していた。In the conventional semiconductor device, as shown in FIGS. 2-) and 2(b), after the F-layer wiring 2t- is formed on the oxide film 3 on the surface of the semiconductor substrate 1 which has been diffused, an interlayer insulation g1 is formed thereon. Upper layer wiring 6t is formed, a through hole is formed in this glabella insulating film l, and the upper layer wiring 6t is connected via the through hole in one metal vapor deposition.
It was formed on a single interlayer insulating film 2.
上述した従来の製法によって得られる構造では上層金属
配４６と下層金属配線２とつなぐため層間絶縁膜１に開
けたスルーホール開口部で上層金属配線６は陥没によ５
薄くなる。このため、この博くなフた部分で金属の電流
量が少なくなると言う欠点がある。In the structure obtained by the conventional manufacturing method described above, the upper layer metal interconnect 6 is depressed due to the through hole opening made in the interlayer insulating film 1 to connect the upper layer metal interconnect 46 and the lower layer metal interconnect 2.
Become thin. For this reason, there is a drawback that the amount of current flowing through the metal decreases at this wide lid portion.
本発明によれば、下層金属配線上に眉間絶縁膜を形成し
、この層間絶縁膜にスルーホール金形成し、その後第１
の金属蒸着によりスルーホール内に上層金属配線の金Ｓ
ｔ形成し、さらに第２の金属蒸着により上層金属配線を
形成する半導体装置の製造方法を得る０
〔実施例〕
次に本発明について図面を参照して説明する。According to the present invention, a glabellar insulating film is formed on the lower layer metal wiring, through-hole gold is formed in this interlayer insulating film, and then the first
The gold S of the upper layer metal wiring is placed inside the through hole by metal vapor deposition.
Example 1 Next, the present invention will be described with reference to the drawings.
第１図（ａ）〜（Ｃ）は、本発明の一実施例の製造工程
を示す縦断面図である。まず、第１図（ａ）のように不
純物拡散処理の施された半導体基体４表面の酸化膜３上
に形成した下層金属配線２の上に層間絶縁膜１ｔ−のせ
て、上層金属配線６と下層金属配線２とをつなぐため層
間絶縁膜１にスルーホールを開ける。次に、同図Φ）の
ように、層間絶縁膜ｌの上に１度目の金属蒸着を行ない
、上層金属配線６と下層金属配線２をつなぐため層間絶
縁膜ｌに開は九スルーホールの内部だけに金ｆｉ５ｔ−
形成し、他の金属はエツチングして取り除いてしまう。FIGS. 1(a) to 1(C) are longitudinal cross-sectional views showing the manufacturing process of an embodiment of the present invention. First, as shown in FIG. 1(a), an interlayer insulating film 1t- is placed on the lower metal wiring 2 formed on the oxide film 3 on the surface of the semiconductor substrate 4 which has been subjected to impurity diffusion treatment, and the upper metal wiring 6 and A through hole is made in the interlayer insulating film 1 to connect it to the lower metal wiring 2. Next, as shown in the figure Φ), a first metal vapor deposition is performed on the interlayer insulating film l, and nine through holes are opened in the interlayer insulating film l to connect the upper metal wiring 6 and the lower metal wiring 2. Only gold fi5t-
The other metals are etched away.
次に、同図（Ｃ）のように２度目の金属蒸着を行ない下
層金属配線６を形成する。Next, as shown in FIG. 2C, a second metal vapor deposition is performed to form the lower metal wiring 6.
以上説明したように本発明を実施することにより、従来
のように上層金属配線と下層金属配線金つなぐため層間
絶縁膜に開Ｖするホール開口部の金属が薄くならないの
で電流量が増大できる効果がある０
また本発明を大電流を流すＩＣに使用すれば、チッグサ
イズを縮少できる効果もある０As explained above, by implementing the present invention, the metal of the hole opening opened in the interlayer insulating film to connect the upper layer metal wiring and the lower layer metal wiring does not become thinner, unlike the conventional method, and the amount of current can be increased. 0 Also, if the present invention is used in an IC that flows a large current, it will also have the effect of reducing the chip size.
第１図（ａ）〜（Ｃ）は本発明の一実施例による製造工
程を示す断面図である０
第２図（ａ）＊ （ｂ）は従来の製造工程を示す断面図
である。
１・・・・・・層間絶縁膜
２・・・・・・下層金属配線
３・・・・・・酸化膜
４・・・・・・半導体基体
５・・・・・・ホール内部金属
６・・・・・・上層金属配線
（０Ｌ）
Ｃｂ＞
＄−７図
Ｃｂン
＄２ ］！ＩFIGS. 1(a) to (C) are cross-sectional views showing a manufacturing process according to an embodiment of the present invention. FIGS. 2(a)*(b) are cross-sectional views showing a conventional manufacturing process. 1...Interlayer insulating film 2...Lower metal wiring 3...Oxide film 4...Semiconductor base 5...Hole interior metal 6. ... Upper layer metal wiring (0L) Cb > $-7 Figure Cb - $2]! I
Claims (1)
金属配線上に層間絶縁膜を形成する工程と、該層間絶縁
膜にスルーホールを開ける工程と、前記スルーホール内
部に第１の金属蒸着で金属導体を形成する工程と、前記
層間絶縁膜上および前記金属導体上に第２の金属蒸着で
上層金属配線を形成する工程とを含むことを特徴とする
半導体装置の製造方法。forming a lower metal wiring on a semiconductor substrate; forming an interlayer insulating film on the lower metal wiring; opening a through hole in the interlayer insulating film; and depositing a first metal inside the through hole. 1. A method of manufacturing a semiconductor device, comprising: forming a metal conductor on the interlayer insulating film and on the metal conductor using a second metal vapor deposition process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4050085A JPS61199649A (en) | 1985-03-01 | 1985-03-01 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4050085A JPS61199649A (en) | 1985-03-01 | 1985-03-01 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61199649A true JPS61199649A (en) | 1986-09-04 |
Family
ID=12582280
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4050085A Pending JPS61199649A (en) | 1985-03-01 | 1985-03-01 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61199649A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USRE36663E (en) * | 1987-12-28 | 2000-04-18 | Texas Instruments Incorporated | Planarized selective tungsten metallization system |
-
1985
- 1985-03-01 JP JP4050085A patent/JPS61199649A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USRE36663E (en) * | 1987-12-28 | 2000-04-18 | Texas Instruments Incorporated | Planarized selective tungsten metallization system |
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