JPH0328058B2 - - Google Patents
Info
- Publication number
- JPH0328058B2 JPH0328058B2 JP61052619A JP5261986A JPH0328058B2 JP H0328058 B2 JPH0328058 B2 JP H0328058B2 JP 61052619 A JP61052619 A JP 61052619A JP 5261986 A JP5261986 A JP 5261986A JP H0328058 B2 JPH0328058 B2 JP H0328058B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- metal layer
- metal
- nickel
- heat treatment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 20
- 239000004065 semiconductor Substances 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 11
- 239000005300 metallic glass Substances 0.000 claims description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 30
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 20
- 229910052737 gold Inorganic materials 0.000 description 15
- 239000010931 gold Substances 0.000 description 15
- 229910052759 nickel Inorganic materials 0.000 description 15
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 13
- 238000010438 heat treatment Methods 0.000 description 12
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 11
- 229910052719 titanium Inorganic materials 0.000 description 11
- 239000010936 titanium Substances 0.000 description 11
- 229910052782 aluminium Inorganic materials 0.000 description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 10
- 229910052763 palladium Inorganic materials 0.000 description 10
- 238000000034 method Methods 0.000 description 8
- 229910000808 amorphous metal alloy Inorganic materials 0.000 description 7
- 239000010953 base metal Substances 0.000 description 7
- 230000007797 corrosion Effects 0.000 description 6
- 238000005260 corrosion Methods 0.000 description 6
- 238000002161 passivation Methods 0.000 description 6
- 150000002739 metals Chemical class 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 229910052735 hafnium Inorganic materials 0.000 description 4
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 238000003746 solid phase reaction Methods 0.000 description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 150000002343 gold Chemical class 0.000 description 2
- 150000002736 metal compounds Chemical class 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 239000010955 niobium Substances 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に係り、特に多層の金属か
らなる電極に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to an electrode made of multilayer metal.
近年、ICカードなどの機器に塔載する半導体
集積回路装置の薄型化が望まれている。従来、集
積回路装置の薄型化の一例として第2図に示す様
な電極の形成方法がある。
In recent years, it has been desired to make semiconductor integrated circuit devices mounted on devices such as IC cards thinner. Conventionally, there is a method of forming electrodes as shown in FIG. 2 as an example of reducing the thickness of an integrated circuit device.
第2図aに示す様に回路素子が形成された半導
体基板1上にアルミニウムの電極パツド2を設
け、パツシベーシヨン膜としてこのアルミニウム
電極パツド2周辺部及び半導体基板1表面を被膜
するシリコン窒化膜3を形成する。 As shown in FIG. 2a, an aluminum electrode pad 2 is provided on a semiconductor substrate 1 on which circuit elements are formed, and a silicon nitride film 3 is applied as a passivation film to cover the peripheral area of the aluminum electrode pad 2 and the surface of the semiconductor substrate 1. Form.
次にチタン、ニツケル、パラジウムを順次真空
蒸着して、チタン層4、ニツケル層5、パラジウ
ム層6を形成し、380℃でこれら下地金属4,5,
6の内部応力を低減するための熱処理を行なう。
これら下地金属4,5,6上にレジストを被覆し
ホトリソグラフイ工程をへて、アルミニウム電極
パツド2上に穴を形成する。(第2図b)つづい
て金を被覆しホトリソグラフイ工程を施してアル
ミニウム電極2上にチタン層4、ニツケル層5、
パラジウム層6を介した金バンプ8を形成する。
この金バンプ8は外部との接続のために使用さ
れ、この金バンプを介して直接ICカード等にマ
ウントされる。次にホトリソグラフイ工程で用い
たレジスト7を除去し、金バンプ8をマスクとし
て下地金属4,5,6であるチタン層4、ニツケ
ル層5、パラジウム層6をエツチング除去する。
これら工程をへて第2図Cに示すようなアルミニ
ウム電極パツド2上に、チタン4、ニツケル5、
パラジウム6からなる下地金属層、及び金バンプ
8を設けた構造の電極が形成されていた。 Next, titanium, nickel, and palladium are sequentially vacuum-deposited to form a titanium layer 4, a nickel layer 5, and a palladium layer 6.
6. Heat treatment is performed to reduce the internal stress.
Resist is coated on these base metals 4, 5, and 6, and a photolithography process is performed to form holes on the aluminum electrode pads 2. (Fig. 2b) Subsequently, gold is coated and a photolithography process is applied to form a titanium layer 4, a nickel layer 5, on the aluminum electrode 2.
Gold bumps 8 are formed through palladium layer 6.
This gold bump 8 is used for connection with the outside, and is directly mounted on an IC card or the like via this gold bump. Next, the resist 7 used in the photolithography process is removed, and the underlying metals 4, 5, 6, which are the titanium layer 4, the nickel layer 5, and the palladium layer 6, are etched away using the gold bumps 8 as a mask.
After these steps, titanium 4, nickel 5,
An electrode having a structure including a base metal layer made of palladium 6 and gold bumps 8 was formed.
従来の製造方法で製造された電極においては、
熱工程などでパラジウムのニツケル層への拡散が
起こり界面の制御が不安定になり、又熱工程にお
ける両金属間の拡散により生成される化合物は強
度が弱く、電気的特性も変化してしまうことから
半導体装置の破壊につながる。また、下地金属層
を形成した後に内部応力を低減するための熱処理
を施すが、この熱処理は金属間拡散を促進するこ
とから長時間行なえない。従つて、十分な内部応
力の緩和がなされない。
In electrodes manufactured using conventional manufacturing methods,
During the thermal process, palladium diffuses into the nickel layer, making control of the interface unstable, and the compounds generated by diffusion between the two metals during the thermal process have low strength and change electrical properties. This can lead to destruction of semiconductor devices. Further, after forming the base metal layer, heat treatment is performed to reduce internal stress, but this heat treatment cannot be carried out for a long time because it promotes intermetallic diffusion. Therefore, sufficient relaxation of internal stress is not achieved.
この内部応力による金属間の歪はパツシベーシ
ヨン膜に割れを生じさせる。またホトリソグラフ
イ工程における金属のエツチングにより電極パツ
ド周辺部上の段差部にピンホールが発生する。こ
れらの割れやピンホールを通してエツチング液な
どが侵入し、アルミニウム電極パツドや配線など
を腐食してしまう。 Distortion between metals due to this internal stress causes cracks in the passivation film. Furthermore, due to metal etching in the photolithography process, pinholes are generated at the stepped portions on the periphery of the electrode pads. Etching liquid and the like enter through these cracks and pinholes, corroding the aluminum electrode pads and wiring.
本発明の目的は、強度、耐食性に強い構造を持
つ電極を製造することにある。 An object of the present invention is to manufacture an electrode having a structure with high strength and corrosion resistance.
本発明においては、電極パツド上に、低温固相
反応により非晶質合金を形成する金属を含む多金
属層を形成し、これらの下地金属層上に選択的に
配線用金バンプを形成する。ここで低温熱処理を
施し、下地金属間の界面に非晶質合金を形成した
後、金バンプをマスクとして、下地金属を除去す
る。
In the present invention, a multimetal layer containing a metal that forms an amorphous alloy by low-temperature solid phase reaction is formed on the electrode pad, and gold bumps for wiring are selectively formed on these underlying metal layers. Here, low-temperature heat treatment is performed to form an amorphous alloy at the interface between the base metals, and then the base metals are removed using the gold bumps as a mask.
このように金バンプの下地となる多金属層に非
晶質層を含むことを特徴とする半導体装置の電極
を形成する。 In this way, an electrode of a semiconductor device is formed, which is characterized in that the polymetal layer underlying the gold bumps includes an amorphous layer.
本発明によれば電極パツド及び基板上に形成さ
れた絶縁膜上に非晶質合金を形成する金属を含む
複数の金属層を設ける。これらに基板内の回路素
子を破壊しない程度の低温の熱処理を施し金属層
間に低温固相反応を起こさせる。この低温固相反
応により非晶質合金層が形成される。
According to the present invention, a plurality of metal layers including a metal forming an amorphous alloy are provided on an electrode pad and an insulating film formed on a substrate. These are subjected to heat treatment at a low temperature that does not destroy the circuit elements within the substrate, causing a low-temperature solid phase reaction between the metal layers. This low-temperature solid phase reaction forms an amorphous alloy layer.
更にこの低温熱処理は金属層間の内部応力の緩
和を同時に行なうことができる。 Furthermore, this low-temperature heat treatment can simultaneously relieve internal stress between metal layers.
以下、本発明の実施例を第1図をもちいて説明
する。トランジスタ、ダイオード等の素子が形成
された半導体基板11上に選択的にアルミニウム
電極パツド12を形成する。このアルミニウム電
極パツド12上を含む半導体基板11全面に窒化
シリコンから成る絶縁膜13を被覆し、ホトリソ
グラフイ技術を用いてコンタクトホールを形成す
る。このシリコン窒化膜13は半導体基板11に
形成された回路素子のパツシベーシヨン膜として
作用する。なおこのパツシベーシヨン膜は窒化シ
リコンに限定されない。つづいて、コンタクトホ
ールを含む全面に順次、チタン、ニツケル、ハフ
ニウム、パラジウムを真空蒸着して2000Åのチタ
ン層14、5000Åのニツケル層15、3000Åのハ
フニウム層16、500Åのパラジウム層17を形
成する。
Embodiments of the present invention will be described below with reference to FIG. Aluminum electrode pads 12 are selectively formed on a semiconductor substrate 11 on which elements such as transistors and diodes are formed. The entire surface of the semiconductor substrate 11 including the aluminum electrode pad 12 is covered with an insulating film 13 made of silicon nitride, and contact holes are formed using photolithography. This silicon nitride film 13 acts as a passivation film for circuit elements formed on the semiconductor substrate 11. Note that this passivation film is not limited to silicon nitride. Subsequently, titanium, nickel, hafnium, and palladium are sequentially vacuum-deposited over the entire surface including the contact hole to form a titanium layer 14 of 2000 Å, a nickel layer 15 of 5000 Å, a hafnium layer 16 of 3000 Å, and a palladium layer 17 of 500 Å.
(第1図a)つづいてレジスト18を全面に被
覆し電極が形成される部分をエツチング除去す
る。この後、第1図bに示すような金バンプ19
をメツキにより形成する。次に、レジスト18を
除去し、380℃で熱処理を行なう。この低温熱処
理により、ニツケル層15とハフニウム層16と
の界面で低温固相反応が起こり、非晶質層20が
形成される。(第1図c)つづいて、硝酸、塩酸、
酢酸の混液で金バンプ19をマスクとして未反応
のハフニウム層16とパラジウム層17をエツチ
ング除去する。(第1図d)
つづいて、少なくともアルミニウム電極パツド
上に残る程度に非晶質金属層20及びニツケル層
15、チタン層14をエツチング除去し、電極が
形成される。(第1図e)
このように形成された電極は、低温熱処理によ
り非晶質層20を形成すると同時に金属間の内部
応力の緩和が行なわれる。形成された非晶質合金
20は、耐食性に優れており、又、ニツケル層1
5はチタン層14の酸化を防ぎ、チタン層14は
パツシベーシヨン膜13を保護する構成になつて
いることからアルミニウム電極12及び配線の腐
食を防止することができる。更に、このことから
アルミニウム電極パツド12と下地金属14,1
5,20,16,17との密着性が向上し、接触
抵抗のバラツキも抑えることができる。また、非
晶質合金20は引つ張り強度に優れている上、特
に内部応力を緩和するための熱処理が必要ないの
でパラジウムのチタン層14、ニツケル伺15へ
の拡散による金属化合物の生成を抑こることがで
きることから強度が向上する。 (FIG. 1a) Subsequently, the entire surface is covered with resist 18, and the portion where the electrode will be formed is removed by etching. After this, a gold bump 19 as shown in FIG.
is formed by plating. Next, the resist 18 is removed and heat treatment is performed at 380°C. By this low-temperature heat treatment, a low-temperature solid phase reaction occurs at the interface between the nickel layer 15 and the hafnium layer 16, and an amorphous layer 20 is formed. (Figure 1c) Next, nitric acid, hydrochloric acid,
The unreacted hafnium layer 16 and palladium layer 17 are etched away using a mixture of acetic acid and the gold bumps 19 as a mask. (FIG. 1d) Subsequently, the amorphous metal layer 20, the nickel layer 15, and the titanium layer 14 are etched away to the extent that they remain at least on the aluminum electrode pad, thereby forming an electrode. (FIG. 1e) In the electrode thus formed, the amorphous layer 20 is formed by low-temperature heat treatment, and at the same time, the internal stress between the metals is relaxed. The formed amorphous alloy 20 has excellent corrosion resistance, and the nickel layer 1
5 prevents oxidation of the titanium layer 14, and since the titanium layer 14 protects the passivation film 13, corrosion of the aluminum electrode 12 and wiring can be prevented. Furthermore, from this, the aluminum electrode pad 12 and the base metal 14,1
5, 20, 16, and 17 is improved, and variations in contact resistance can also be suppressed. In addition, the amorphous alloy 20 has excellent tensile strength and does not require heat treatment to relieve internal stress, so it suppresses the formation of metal compounds due to diffusion of palladium into the titanium layer 14 and the nickel layer 15. Strength is improved because it can be bent.
第1図の実施例では、非晶質合金を形成する金
属としてニツケルとハウニウムを用いたが金とラ
ンタン、イツトリウムと金、ニツケルとジルコニ
ウム、ニツケルとニオブなどを用いることができ
る。この場合100℃から400℃の範囲のそれぞれ適
した温度で熱処理を行なつて非晶質金金を形成す
る。この場合、熱処理の温度は、半導体基板に形
成される回路素子に影響を与えない温度であるこ
とが必要である。 In the embodiment shown in FIG. 1, nickel and haunium are used as the metals forming the amorphous alloy, but gold and lanthanum, yttrium and gold, nickel and zirconium, nickel and niobium, etc. can also be used. In this case, heat treatment is performed at a suitable temperature in the range of 100°C to 400°C to form amorphous gold. In this case, the temperature of the heat treatment needs to be a temperature that does not affect the circuit elements formed on the semiconductor substrate.
〔発明の効果〕
以上説明したように、半導体回路素子を破壊し
ない程度の低温の熱工程により、金属化合物の生
成が抑えられ、強度が向上し、また、内部応力の
緩和が十分行なわれ、これに伴なう電極パツドの
腐食を抑えることができる。このように強度、耐
食性に優れた電極を形成することができる。[Effects of the Invention] As explained above, the thermal process at a low temperature that does not destroy semiconductor circuit elements suppresses the formation of metal compounds, improves strength, and sufficiently relieves internal stress. Corrosion of the electrode pads caused by corrosion can be suppressed. In this way, an electrode with excellent strength and corrosion resistance can be formed.
第1図は、本発明の一実施例の製造方法、第2
図は従来例を示す。
11……半導体基板、12……電極パツド、1
3……パツシベーシヨン、14,15,16,1
7……下地金属層、19……金バンプ、20……
非晶質金属。
FIG. 1 shows a manufacturing method according to an embodiment of the present invention;
The figure shows a conventional example. 11... Semiconductor substrate, 12... Electrode pad, 1
3...passivation, 14, 15, 16, 1
7... Base metal layer, 19... Gold bump, 20...
Amorphous metal.
Claims (1)
導体基板上に選択的に設けられた電極パツドと、
この電極パツド上に設けられた第1金属層と、こ
の第1金属層上に設けられた非晶質金属層と、こ
の非晶質金属層上に設けられた第2金属層と、こ
の第2金属層上に設けられた金属バンプとからな
る半導体装置。1. A semiconductor substrate on which circuit elements are formed, electrode pads selectively provided on this semiconductor substrate,
A first metal layer provided on the electrode pad, an amorphous metal layer provided on the first metal layer, a second metal layer provided on the amorphous metal layer, and a second metal layer provided on the amorphous metal layer. A semiconductor device consisting of two metal layers and metal bumps provided on the metal layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61052619A JPS62210649A (en) | 1986-03-12 | 1986-03-12 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61052619A JPS62210649A (en) | 1986-03-12 | 1986-03-12 | Semiconductor device and manufacture thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS62210649A JPS62210649A (en) | 1987-09-16 |
JPH0328058B2 true JPH0328058B2 (en) | 1991-04-17 |
Family
ID=12919818
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61052619A Granted JPS62210649A (en) | 1986-03-12 | 1986-03-12 | Semiconductor device and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62210649A (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06103701B2 (en) * | 1988-03-11 | 1994-12-14 | 松下電器産業株式会社 | Semiconductor device mounting body |
JP2839513B2 (en) * | 1988-03-15 | 1998-12-16 | 株式会社東芝 | Method of forming bump |
JP2731040B2 (en) * | 1991-02-05 | 1998-03-25 | 三菱電機株式会社 | Method for manufacturing semiconductor device |
KR100319813B1 (en) * | 2000-01-03 | 2002-01-09 | 윤종용 | method of forming solder bumps with reduced UBM undercut |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57126132A (en) * | 1981-01-27 | 1982-08-05 | Citizen Watch Co Ltd | Manufacture of semiconductor device |
JPS57186344A (en) * | 1981-05-12 | 1982-11-16 | Fuji Electric Corp Res & Dev Ltd | Semiconductor device sealed in glass tube |
-
1986
- 1986-03-12 JP JP61052619A patent/JPS62210649A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57126132A (en) * | 1981-01-27 | 1982-08-05 | Citizen Watch Co Ltd | Manufacture of semiconductor device |
JPS57186344A (en) * | 1981-05-12 | 1982-11-16 | Fuji Electric Corp Res & Dev Ltd | Semiconductor device sealed in glass tube |
Also Published As
Publication number | Publication date |
---|---|
JPS62210649A (en) | 1987-09-16 |
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