JPS62210649A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS62210649A JPS62210649A JP61052619A JP5261986A JPS62210649A JP S62210649 A JPS62210649 A JP S62210649A JP 61052619 A JP61052619 A JP 61052619A JP 5261986 A JP5261986 A JP 5261986A JP S62210649 A JPS62210649 A JP S62210649A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- heat treatment
- nickel
- amorphous
- low
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title description 5
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000005300 metallic glass Substances 0.000 claims description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 abstract description 36
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 abstract description 22
- 229910052737 gold Inorganic materials 0.000 abstract description 19
- 239000010931 gold Substances 0.000 abstract description 19
- 229910052759 nickel Inorganic materials 0.000 abstract description 18
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 17
- 238000010438 heat treatment Methods 0.000 abstract description 14
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 abstract description 13
- 229910052719 titanium Inorganic materials 0.000 abstract description 13
- 239000010936 titanium Substances 0.000 abstract description 13
- 229910052782 aluminium Inorganic materials 0.000 abstract description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 11
- 229910052763 palladium Inorganic materials 0.000 abstract description 11
- 229910000808 amorphous metal alloy Inorganic materials 0.000 abstract description 8
- 229910052735 hafnium Inorganic materials 0.000 abstract description 7
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 abstract description 7
- 230000007797 corrosion Effects 0.000 abstract description 6
- 238000005260 corrosion Methods 0.000 abstract description 6
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 5
- 150000002739 metals Chemical class 0.000 abstract description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 5
- 238000003746 solid phase reaction Methods 0.000 abstract description 4
- 238000007747 plating Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 9
- 238000002161 passivation Methods 0.000 description 6
- 239000010953 base metal Substances 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- 150000002343 gold Chemical class 0.000 description 2
- 150000002736 metal compounds Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000013329 compounding Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 239000010955 niobium Substances 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
不兄明は半導体装置に係り、７待に多層の金属からなる
電極及びその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor devices, and more particularly to electrodes made of multilayer metal and methods for manufacturing the same.
近年、ＩＣカードなどの機器に塔載する半導体集積回路
装置の薄型化が望まれている。従来、集積回路装置の薄
型化の一例として第２図に示す様な電極の形成方法があ
る。In recent years, it has been desired to make semiconductor integrated circuit devices mounted on devices such as IC cards thinner. Conventionally, there is a method of forming electrodes as shown in FIG. 2 as an example of reducing the thickness of an integrated circuit device.
第２図ａに示す様に回路素子が形成された半導体基板１
上Ｖζアルミニウムの電極パッド２を設け、パッシベー
ション膜としてこのアルミニウム電極パッド２周辺部及
び半導体基板１表面を被膜するシリコン窒化膜３を形成
する。Semiconductor substrate 1 on which circuit elements are formed as shown in FIG. 2a
An upper Vζ aluminum electrode pad 2 is provided, and a silicon nitride film 3 is formed as a passivation film to cover the peripheral portion of the aluminum electrode pad 2 and the surface of the semiconductor substrate 1.
次にチタン、ニッケル、パラジウムを順次真空蒸着して
、チタン層４、ニッケル層５、パラジウム層６を彰成し
、３８０’Ｏでこれら下地金属４，５゜６の内部応力を
低減するための熱処理を行なう。Next, titanium, nickel, and palladium are sequentially vacuum-deposited to form a titanium layer 4, a nickel layer 5, and a palladium layer 6. Perform heat treatment.
これら下地金属４，５．６上にレジストを被覆しホトリ
ソグラフィ工程をへて、アルミニウム電極パッド２上に
穴を形成する。（第２図（ｂ））つづいて金を被覆しホ
トリソグラフィ工程を施してアルミニウム電極２上にチ
タン層４、ニッケル層５、パラジウム層６を介した金バ
ンプ８を形成する。この金バング８は外部との接続のた
めに使用され、この金バンプを介して直接ＩＣカード等
にマウントされる。次にホトリソグラフィ工程で用いた
レジスト７を除去し、金バンプ８をマスクとして下地金
属４，５．６であるチタン層４．ニッケル層５、パラジ
ウム層６をエツチング除去する。これら工程をへて第２
図Ｃｖこ示すようなアルミニウム電極パッド２上に、チ
タン４、ニッケル５、パラジウム６からなる下地金属層
、及び金バンプ８を設けた（４造の′シ他が形成されて
いた。Resist is coated on these base metals 4, 5, 6, and a photolithography process is performed to form holes on the aluminum electrode pads 2. (FIG. 2(b)) Subsequently, gold is coated and a photolithography process is performed to form gold bumps 8 on the aluminum electrode 2 via the titanium layer 4, the nickel layer 5, and the palladium layer 6. This gold bang 8 is used for connection with the outside, and is directly mounted on an IC card or the like via this gold bump. Next, the resist 7 used in the photolithography process is removed, and the titanium layer 4. The nickel layer 5 and palladium layer 6 are removed by etching. After passing through these steps, the second
A base metal layer consisting of titanium 4, nickel 5, and palladium 6 and gold bumps 8 were provided on the aluminum electrode pad 2 as shown in FIG.
従来の製造方法で製造された電極においては、熱工程な
どでパラジウムのニッケル層への拡散が起こり界面の制
御が不安定になり、又熱工程における両金属間の拡散に
より生成される化合・吻は強度が弱く、′五気的特性も
変化してしまうことから半導体装置の破壊につながる。In electrodes manufactured using conventional manufacturing methods, palladium diffuses into the nickel layer during the thermal process, making control of the interface unstable, and also due to the chemical compounding and oxidation produced by the diffusion between the two metals during the thermal process. is weak and its physical properties change, leading to the destruction of semiconductor devices.
また、下地金属層を形成した後に内部応力を低減するだ
めの熱処理を凧すが、この熱処理は金属間拡散を促進す
ることから長時間行なえない。従って、十分な内部応力
の緩和がなされない。Further, after forming the underlying metal layer, heat treatment is performed to reduce internal stress, but this heat treatment cannot be carried out for a long time because it promotes intermetallic diffusion. Therefore, sufficient relaxation of internal stress is not achieved.
この内部応力による金属間の歪はパッシベーション膜に
割れを生じさせる。またホトリソグラフィ工程における
金属のエツチングにより電極パッド周辺部上の段差部に
ピンホールが発生する。これらの割れやピンホールを通
して二ノチング液などが浸入し、アルミニウム電極パッ
ドや配線などを腐食してしまう。Strain between metals due to this internal stress causes cracks in the passivation film. Further, due to metal etching in the photolithography process, pinholes are generated in the stepped portions on the peripheral portions of the electrode pads. Ni-notching liquid and the like enter through these cracks and pinholes, corroding aluminum electrode pads and wiring.
本発明の目的は、強度、耐食性Ｖこ強い構造を持つ電極
を製造することにある。An object of the present invention is to produce an electrode having strength, corrosion resistance, and a strong structure.
本発明においては、′電極バッド上に、低温固相反応に
より非晶質合金を形成する金属を含む多金属層を形成し
、これらの下池金属層上ＶＣ選択的に配線用金バンプを
形成する。ここで低温熱処理を施し、下地金属間の界面
に非晶質合金を形成した後、金バンプをマスクとして、
下地金属を除去する。In the present invention, a polymetal layer containing a metal that forms an amorphous alloy by low-temperature solid-phase reaction is formed on the electrode pad, and gold bumps for wiring are selectively formed on the lower metal layer of the VC. . After performing low-temperature heat treatment to form an amorphous alloy at the interface between the base metals, using the gold bump as a mask,
Remove the underlying metal.
このように金バンブの下地となる多金（４層に非晶質層
を含むことを特徴とする半導体装置の電極を形成する。In this way, an electrode of a semiconductor device characterized by containing a multi-metal layer (four amorphous layers) serving as the base of the gold bump is formed.
本発明によれば電極パッド及び基板上に形成された絶縁
膜上に非晶質合金を形成する金属を含む複数の金属層を
設ける。これらに基板内の回路素子を破壊しない程度の
低温の熱処理を施し金属層間に低温固相反応を起こさせ
る。この低温同相反応により非晶質合金層が形成される
。According to the present invention, a plurality of metal layers containing a metal forming an amorphous alloy are provided on an electrode pad and an insulating film formed on a substrate. These are subjected to heat treatment at a low temperature that does not destroy the circuit elements within the substrate, causing a low-temperature solid phase reaction between the metal layers. This low-temperature in-phase reaction forms an amorphous alloy layer.
更にこの低温熱処理は金Ｆ１４層間の内部応力の緩和を
同時に行なうことができる。Furthermore, this low-temperature heat treatment can simultaneously relieve the internal stress between the gold F14 layers.
以下、本発明の実施例を第１図をもちいて説明する。ト
ランジスタ、ダイオード等の素子が形成された半導体基
板１１上に選択的にアルばニウム成極パッド１２を形成
する。このアルミニウム電極パッド１２上を含む半導体
基板１１全面に窒化シリコンから成る２他縁膜１３を被
覆し、ホトリングラフィ技術を用いてコンタクトホール
を形成する。このシリコン窒化膜１３は半導体基板１１
Ｖｃ形成された回路素子のパッシベーション膜として作
用する。なおこのパッシベーション膜は窒化シリコンに
限定されない。つづいて、コンタクトホールを含む全面
に順次、チタン、ニッケル、ノ・フニウム、パラジウム
を真空蒸着して２００ ＯＡのチタン層１４．５０００
Ａのニッケル層１５．３０００Ａのハフニウム層１６．
５００Ａのハフニウム層１７を形成する。Embodiments of the present invention will be described below with reference to FIG. Albanium polarization pads 12 are selectively formed on a semiconductor substrate 11 on which elements such as transistors and diodes are formed. The entire surface of the semiconductor substrate 11 including the aluminum electrode pad 12 is covered with a second edge film 13 made of silicon nitride, and contact holes are formed using photolithography. This silicon nitride film 13
It acts as a passivation film for circuit elements formed with Vc. Note that this passivation film is not limited to silicon nitride. Next, titanium, nickel, nitrogen, and palladium were sequentially vacuum-deposited on the entire surface including the contact hole to form a 200 OA titanium layer with a thickness of 14.5,000 mm.
A nickel layer 15. 3000A hafnium layer 16.
A hafnium layer 17 of 500A is formed.
（第１図ａ）つづいてレジスト１８を全面に被覆し電極
が形成される部分をエツチング１′余去する。(FIG. 1a) Subsequently, the entire surface is covered with a resist 18, and the portion where the electrode is to be formed is etched 1'.
この後、第１図すに示すような金バンプ１９ｔ−メッキ
により形成する。次に、レジスト１８を除去し、３８０
℃で熱処理を行なう。この低温熱処理により、ニッケル
層１５とハフニウム層１６との界面で低温固相反応が起
こり、非晶質層２０が形成される。（第１図Ｃ）つづい
て、硝酸、塩酸、酢酸の混液で金バンプ１９をマスクと
して未反応のハフニウム層１６とパラジウム層１７をエ
ツチング除去する。（第１図ｄ）
つづいて、少なくともアルミニウム゛砥極パッド上に残
る程度に非晶質金属層２０及びニッケル層１５． チタ
ン層１４をエツチング除去し、電極が形成される。（第
１図ｅ）
このように形成された電極は、低温熱処理により非晶質
層２０を形成すると同時に金＠間の内部応力の緩和が行
なわれる。形成された非晶質合金２０は、耐食性に針れ
ており、又、ニッケル層１５はチタン層１４の酸化を防
ぎ、チタン４１４はパッシベーション膜１３を保護する
構成になっていることからアルミニウム電極１２及び配
線の腐食を防止することができる。更に、このことから
アルミニウム電極パッド１２と下地金属１４．１５，２
０，１６．１７との密着性が向上し、接触抵抗のバラツ
キも抑えることができる。また。Thereafter, gold bumps 19t are formed by plating as shown in FIG. Next, the resist 18 is removed and 380
Heat treatment is carried out at ℃. This low-temperature heat treatment causes a low-temperature solid phase reaction to occur at the interface between the nickel layer 15 and the hafnium layer 16, and an amorphous layer 20 is formed. (FIG. 1C) Subsequently, the unreacted hafnium layer 16 and palladium layer 17 are removed by etching with a mixed solution of nitric acid, hydrochloric acid, and acetic acid using the gold bumps 19 as a mask. (FIG. 1d) Next, an amorphous metal layer 20 and a nickel layer 15 are formed to the extent that they remain at least on the aluminum abrasive pad. The titanium layer 14 is etched away to form an electrode. (FIG. 1e) In the electrode thus formed, the amorphous layer 20 is formed by low-temperature heat treatment, and at the same time, the internal stress between the gold layers is relaxed. The formed amorphous alloy 20 has excellent corrosion resistance, the nickel layer 15 prevents the oxidation of the titanium layer 14, and the titanium 414 protects the passivation film 13, so the aluminum electrode 12 And corrosion of wiring can be prevented. Furthermore, from this, the aluminum electrode pad 12 and the base metal 14, 15, 2
0, 16.17 is improved, and variations in contact resistance can also be suppressed. Also.
非晶質合金２０１’を強度に、浸れている上、特に内部
応力を緩和するための熱処理が必要ないのでパラジウム
のチタン層１４．ニッケル伺１５への拡散による金属化
合物の生成を抑こることができることから強度が向上す
る。The titanium layer 14. of palladium has a strong amorphous alloy 201' and does not require heat treatment to relieve internal stress. Since the formation of metal compounds due to diffusion into the nickel layer 15 can be suppressed, the strength is improved.
第１図の実施例では、非晶質合金を形成する金属として
ニッケルとハウニウムを用いたが金とランタン、イツト
リウムと金、ニッケルとジルコニウム、ニッケルとニオ
ブなどを用いることができる。この場合１００’ｏから
４００°Ｃの範囲のそれぞれ適した温度で熱処理を行な
って非晶Ｉ重合金を形成する。こＶ）場合、熱処理の＠
度は、半導体基板Ｖこ形成される回路素子に影響を与え
ない１温度であることが必要である。In the embodiment shown in FIG. 1, nickel and haunium are used as the metals forming the amorphous alloy, but gold and lanthanum, yttrium and gold, nickel and zirconium, nickel and niobium, etc. can also be used. In this case, the amorphous I heavy alloy is formed by heat treatment at a suitable temperature ranging from 100° to 400°C. V) In case of heat treatment @
The temperature needs to be a temperature that does not affect the circuit elements formed on the semiconductor substrate.
以上説明したように、半導体回路素子を破壊しない程度
の低温の熱工程により、金属化合物の生成が抑えられ、
強度が向上し、また、内部応力の緩和が十分性なわれ、
これに伴なう電極パッドの腐食を抑えることができる。As explained above, the generation of metal compounds is suppressed by a thermal process at a low temperature that does not destroy semiconductor circuit elements.
Strength is improved and internal stress is sufficiently relaxed.
Corrosion of the electrode pads accompanying this can be suppressed.
このように強度、耐食性に優れた電極を形成することが
できる。In this way, an electrode with excellent strength and corrosion resistance can be formed.
第１図は、本発明の一実施例の製造方法、第２図は従来
例を示す。
１１・・・半導体基板 １２・・・磁極パッド１３・
・・パッシベーション １４，１５，１６．１７・・・
下地金属層 １９・・金バンプ ２０・・・非晶質
金属（Ｃ）
第１図FIG. 1 shows a manufacturing method according to an embodiment of the present invention, and FIG. 2 shows a conventional example. 11... Semiconductor substrate 12... Magnetic pole pad 13.
...Passivation 14,15,16.17...
Base metal layer 19... Gold bump 20... Amorphous metal (C) Figure 1
Claims (2)
基板上に選択的に設けられた電極パッドと、この電極パ
ッド上に設けられた第１金属層と、この第１金属層上に
設けられた非晶質金属層と、この非晶質金属層上に設け
られた第２金属層と、この第２金属層上に設けられた金
属バンプとからなる半導体装置。(1) A semiconductor substrate on which a circuit element is formed, an electrode pad selectively provided on this semiconductor substrate, a first metal layer provided on this electrode pad, and a semiconductor substrate provided on this first metal layer. A semiconductor device comprising an amorphous metal layer, a second metal layer provided on the amorphous metal layer, and a metal bump provided on the second metal layer.
極パッドを形成する工程と、前記電極パッド上に複数の
金属層を形成する工程と、前記金属層上に金属バンプを
形成する工程と、前記複数の金属層間に非晶質金属層を
形成する工程とからなることを特徴とする半導体装置の
製造方法。(2) A step of selectively forming an electrode pad on a semiconductor substrate on which a circuit element is formed, a step of forming a plurality of metal layers on the electrode pad, and a step of forming a metal bump on the metal layer. and forming an amorphous metal layer between the plurality of metal layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61052619A JPS62210649A (en) | 1986-03-12 | 1986-03-12 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61052619A JPS62210649A (en) | 1986-03-12 | 1986-03-12 | Semiconductor device and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62210649A true JPS62210649A (en) | 1987-09-16 |
| JPH0328058B2 JPH0328058B2 (en) | 1991-04-17 |
Family
ID=12919818
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61052619A Granted JPS62210649A (en) | 1986-03-12 | 1986-03-12 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62210649A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01232735A (en) * | 1988-03-11 | 1989-09-18 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| JPH021127A (en) * | 1988-03-15 | 1990-01-05 | Toshiba Corp | Formation of bump |
| FR2672426A1 (en) * | 1991-02-05 | 1992-08-07 | Mitsubishi Electric Corp | Method of fabricating a semiconductor device comprising a metal deposition process |
| KR100319813B1 (en) * | 2000-01-03 | 2002-01-09 | 윤종용 | method of forming solder bumps with reduced UBM undercut |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57126132A (en) * | 1981-01-27 | 1982-08-05 | Citizen Watch Co Ltd | Manufacture of semiconductor device |
| JPS57186344A (en) * | 1981-05-12 | 1982-11-16 | Fuji Electric Corp Res & Dev Ltd | Semiconductor device sealed in glass tube |
-
1986
- 1986-03-12 JP JP61052619A patent/JPS62210649A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57126132A (en) * | 1981-01-27 | 1982-08-05 | Citizen Watch Co Ltd | Manufacture of semiconductor device |
| JPS57186344A (en) * | 1981-05-12 | 1982-11-16 | Fuji Electric Corp Res & Dev Ltd | Semiconductor device sealed in glass tube |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01232735A (en) * | 1988-03-11 | 1989-09-18 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| JPH021127A (en) * | 1988-03-15 | 1990-01-05 | Toshiba Corp | Formation of bump |
| FR2672426A1 (en) * | 1991-02-05 | 1992-08-07 | Mitsubishi Electric Corp | Method of fabricating a semiconductor device comprising a metal deposition process |
| US5272111A (en) * | 1991-02-05 | 1993-12-21 | Mitsubishi Denki Kabushiki Kaisha | Method for manufacturing semiconductor device contact |
| KR100319813B1 (en) * | 2000-01-03 | 2002-01-09 | 윤종용 | method of forming solder bumps with reduced UBM undercut |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0328058B2 (en) | 1991-04-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5492235A (en) | Process for single mask C4 solder bump fabrication | |
| US4440804A (en) | Lift-off process for fabricating self-aligned contacts | |
| JP3096061B2 (en) | Manufacturing method of microbump for flip chip mounting | |
| JPS5944830A (en) | Method of bonding, coupling and destroying lift-off region on semiconductor structure | |
| JP2002016096A (en) | Semiconductor device and its manufacturing method | |
| KR900001652B1 (en) | Semiconductor device and manufacturing method thereof | |
| JPS62210649A (en) | Semiconductor device and manufacture thereof | |
| JP3446021B2 (en) | Bump electrode structure of semiconductor device and method for forming the same | |
| JP2001007135A (en) | Manufacture of semiconductor device | |
| JPH0555228A (en) | Semiconductor device | |
| CN1103119C (en) | Process for single mask C4 solder bump fabrication | |
| JPS59205735A (en) | Manufacture of semiconductor device | |
| JP2644079B2 (en) | Semiconductor integrated circuit | |
| JP2001332577A (en) | Method of manufacturing semiconductor device | |
| JP3036086B2 (en) | Method for manufacturing semiconductor device | |
| JP2000357701A (en) | Semiconductor device and manufacture thereof | |
| JPH0590271A (en) | Bump forming method | |
| KR100571265B1 (en) | Package Method of Semiconductor Device | |
| JPH05243217A (en) | Manufacture of semiconductor device | |
| JPH02140955A (en) | Semiconductor device | |
| JPS582451B2 (en) | Seizouhouhou | |
| JPH09213700A (en) | Manufacture of bump electrode | |
| JPS59121954A (en) | Manufacture of semiconductor device | |
| JPH05343408A (en) | Tab semiconductor chip | |
| JPH0451050B2 (en) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |