KR100571265B1 - Package Method of Semiconductor Device - Google Patents
Package Method of Semiconductor DeviceInfo
- Publication number
- KR100571265B1 KR100571265B1 KR1019980061371A KR19980061371A KR100571265B1 KR 100571265 B1 KR100571265 B1 KR 100571265B1 KR 1019980061371 A KR1019980061371 A KR 1019980061371A KR 19980061371 A KR19980061371 A KR 19980061371A KR 100571265 B1 KR100571265 B1 KR 100571265B1
- Authority
- KR
- South Korea
- Prior art keywords
- metal layer
- via hole
- semiconductor device
- forming
- film
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
- H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/036—Manufacturing methods by patterning a pre-deposited material
- H01L2224/03618—Manufacturing methods by patterning a pre-deposited material with selective exposure, development and removal of a photosensitive material, e.g. of a photosensitive conductive resin
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/036—Manufacturing methods by patterning a pre-deposited material
- H01L2224/03622—Manufacturing methods by patterning a pre-deposited material using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05083—Three-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05171—Chromium [Cr] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05181—Tantalum [Ta] as principal constituent
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 패키지 방법에 관한 것으로, 칩 스케일 패키지(Chip Scale Package) 공정에서 패드를 노출시키기 위한 보호막 패터닝 공정후 감광막 패턴을 형성하고 금속을 증착하므로써 공정의 단순화를 이를 수 있으며, 또한 알루미늄(Al)합금/탄탈(Ta) 또는 니오브(Nb)/크롬(Cr)을 이용하여 금속층을 형성하므로써 구리(Cu)의 사용으로 인한 불량의 발생이 방지되고, 금속배선과 납과의 접착성이 향상되어 공정의 안정성 및 수율 향상을 이룰 수 있는 반도체 소자의 패키지 방법이 개시된다.The present invention relates to a method for packaging a semiconductor device, and to simplify the process by forming a photoresist pattern and depositing a metal after a protective film patterning process for exposing a pad in a chip scale package process. Formation of the metal layer using (Al) alloy / tantalum (Ta) or niobium (Nb) / chromium (Cr) prevents the occurrence of defects due to the use of copper (Cu), and the adhesion between metal wiring and lead Disclosed is a method for packaging a semiconductor device that can be improved to achieve process stability and yield improvement.
Description
본 발명은 반도체 소자의 패키지 방법에 관한 것으로, 특히 칩 스케일 패키지(Chip Scale Package) 공정에 이용되는 반도체 소자의 패키지 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for packaging a semiconductor device, and more particularly, to a method for packaging a semiconductor device used in a chip scale package process.
일반적으로 반도체 소자의 제조 공정이 완료되면 최종 단계로서 최상부에 보호막을 형성하고 상기 보호막을 패터닝하여 각각의 패드영역를 노출시킨다. 그리고 웨이퍼로부터 각각의 칩(Chip)을 분리하여 리드 프레임(Lead Frame)에 부착시킨 후 칩에 형성된 패드와 리드 프레임을 연결시키기 위한 와이어 본딩(Wire Bonding) 공정을 실시한다. 이후 각각의 칩이 부착된 리드 프레임을 폴리머(Polymer) 또는 세라믹(Ceramic) 등으로 몰딩(Moulding)한 후 경화(Sintering)시킨다. 이와 같이 패키지(Package)된 반도체 소자는 리드 프레임이 가지는 형태에 따라 TSOP형, SOJ형 등과 같은 형태로 분류된다.In general, when the fabrication process of the semiconductor device is completed, as a final step, a protective film is formed on the top and the protective film is patterned to expose each pad area. Each chip is separated from the wafer and attached to a lead frame, and then a wire bonding process is performed to connect the pad formed on the chip to the lead frame. Then, the lead frame to which each chip is attached is molded by polymer or ceramic and then sintered. The packaged semiconductor device is classified into a TSOP type, a SOJ type, and the like according to the shape of the lead frame.
그런데 반도체 소자가 초고집적화되고, 그 적용 분야도 더욱 넓어짐에 따라 사용자의 요구를 충족시키기 위한 새로운 패키지 방법이 요구되는데, 근래에는 칩 스케일 패키지 공정이 개발중이다.However, as semiconductor devices are highly integrated and their applications are further widened, new packaging methods are required to meet the needs of users. In recent years, chip scale package processes are being developed.
칩 스케일 패키지는 사용자의 요구에 따른 규격화된 형태의 패키지를 제공하기 위한 것인데, 상기 TSOP형, SOJ형 등과 같은 형태를 갖는 것이 아닌 칩 형태로 제공된다. 이를 위하여 소자의 제조 공정에서 보호막을 형성한 후 보호막을 패터닝하여 패드를 노출시키고 금속배선을 이용하여 상기 패드와 사용자의 요구에 따라 형성된 다른 패드를 연결시킨다. 그러면 종래 반도체 소자의 패키지 방법을 설명하면 다음과 같다.The chip scale package is intended to provide a package in a standardized form according to a user's request. The chip scale package is provided in a chip form, rather than having a form such as the TSOP type or the SOJ type. To this end, after forming a protective film in the manufacturing process of the device, the protective film is patterned to expose the pad, and the metal wiring is used to connect the pad with another pad formed according to the user's request. The following describes a conventional method for packaging a semiconductor device.
도 1a 내지 1d는 종래 반도체 소자의 패키지 방법을 설명하기 위한 소자의 단면도로서,1A to 1D are cross-sectional views of devices for explaining a method of packaging a conventional semiconductor device.
도 1a는 소정의 소자 제조 공정을 거쳐 최상부에 도전층(3)이 형성된 반도체기판(1)상에 보호막(4)을 형성한 후 상기 도전층(3)의 패드영역이 노출되도록 상기 보호막(4)을 패터닝하여 제 1 비아홀(8)을 형성한 상태의 단면도이다.FIG. 1A illustrates a protective film 4 formed on a semiconductor substrate 1 having a conductive layer 3 formed on top thereof through a predetermined device fabrication process so that the pad region of the conductive layer 3 is exposed. ) Is a cross-sectional view of the first via hole 8 formed by patterning.
도 1b는 상기 제 1 비아홀(8)을 통해 상기 도전층(3)과 접속되도록 상기 보호막(4)상에 금속층(5)을 형성한 후 상기 금속층(5)상에 감광막(9)을 형성하고 상기 감광막(9)을 패터닝한 상태의 단면도로서, 상기 금속층(5)은 알루미늄(Al)/니켈(Ni)-바나듐(V)합금/구리(Cu)가 적층된 다층 구조로 형성된다.FIG. 1B illustrates forming a metal layer 5 on the passivation layer 4 so as to be connected to the conductive layer 3 through the first via hole 8, and then forming a photosensitive layer 9 on the metal layer 5. As a cross-sectional view of the patterned state of the photosensitive film 9, the metal layer 5 is formed in a multilayer structure in which aluminum (Al) / nickel (Ni) -vanadium (V) alloy / copper (Cu) is laminated.
도 1c는 패터닝된 상기 감광막(9)을 마스크로 이용한 식각 공정으로 노출된 부분의 상기 금속층(5)을 식각하여 금속배선(5A)을 형성한 후 상기 감광막(9)을 제거하고 전체 상부면에 절연막(6)을 형성한 다음 상기 금속배선(5A)의 패드영역이 노출되도록 상기 절연막(6)을 패터닝하여 제 2 비아홀(10)을 형성한 상태의 단면도이다.FIG. 1C illustrates that the metal layer 5 of the exposed portion is etched by the etching process using the patterned photoresist 9 as a mask to form a metal wiring 5A, and then the photoresist 9 is removed and the entire upper surface is removed. After the insulating film 6 is formed, the second via hole 10 is formed by patterning the insulating film 6 to expose the pad region of the metal wiring 5A.
도 1d는 상기 제 2 비아홀(10)내에 납(Solder; 7)을 매립한 후 열처리한 상태의 단면도로서, 이후 웨이퍼로부터 칩을 분리시켜 패키지를 완성한다.FIG. 1D is a cross-sectional view of a state in which a lead 7 is embedded in the second via hole 10 and then heat treated, and then a chip is separated from a wafer to complete a package.
상기와 같은 방법을 이용하는 경우 상기 금속층(5)은 낮은 자체 저항값을 가지며 접착 특성이 우수한 금속 재료로 형성되어야 한다. 또한, 상기와 같이 납(7)을 사용함에 따라 납(7)의 확산이 발생될 수 있으므로 납의 확산을 차단할 수 있는 금속재료를 사용해야 한다. 그러나 상기 금속배선(5A)은 알루미늄(Al)/니켈(Ni)-바나듐(V)합금/구리(Cu)로 이루어지기 때문에 상기 납(7)의 확산을 차단하지 못하며, 또한, 상기 금속배선(5A)에 함유된 구리(Cu)는 소자의 제조시 가해지는 열 또는 소자의 동작시 발생되는 열에 의해 외부로 확산되어 소자의 신뢰성에 영향을 미칠 수 있으며, 구리(Cu)의 산화에 의해 상기 금속배선(5A)과 상기 납(7)과의 접착력이 저하될 수 있다.In the case of using the above method, the metal layer 5 should be formed of a metal material having low self-resistance and excellent adhesive properties. In addition, the use of lead (7) as described above may lead to the diffusion of lead (7) must be used a metal material that can block the diffusion of lead. However, since the metal wire 5A is made of aluminum (Al) / nickel (Ni) -vanadium (V) alloy / copper (Cu), the metal wire 5A does not block diffusion of the lead 7, and the metal wire ( Copper (Cu) contained in 5A) is diffused to the outside by the heat applied during the manufacture of the device or the heat generated during the operation of the device may affect the reliability of the device, and by the oxidation of copper (Cu) The adhesion between the wiring 5A and the lead 7 may decrease.
따라서 본 발명은 패드를 노출시키기 위한 보호막 패터닝 공정후 감광막 패턴을 형성하고 금속을 증착하므로써 상기한 단점을 해소할 수 있는 반도체 소자의 패키지 방법을 제공하는 데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of packaging a semiconductor device which can solve the above-mentioned disadvantages by forming a photoresist pattern and depositing a metal after the protective film patterning process for exposing the pad.
상기한 목적을 달성하기 위한 본 발명은 소정의 소자 제조 공정을 거쳐 최상 부에 도전층이 형성된 반도체 기판상에 보호막을 형성한 후 상기 도전층의 패드영역이 노출되도록 상기 보호막을 패터닝하여 제 1 비아홀을 형성하는 단계와, 상기 단계로부터 전체 상부면에 감광막을 형성한 후 금속배선 마스크를 이용하여 상기 감광막을 패터닝하는 단계와, 상기 단계로부터 상기 제 1 비아홀을 통해 상기 도전층과 접속되도록 전체 상부면에 금속층을 형성한 후 상기 감광막 및 상기 감광막상에 형성된 금속층을 제거하는 단계와, 상기 단계로부터 전체 상부면에 절연막을 형성한 후 상기 금속층의 패드영역이 노출되도록 상기 절연막을 패터닝하여 제 2 비아홀을 형성하는 단계와, 상기 단계로부터 상기 제 2 비아홀내에 납을 매립한 후 열처리하는 단계로 이루어지는 것을 특징으로 하며, 상기 금속층은 알루미늄(Al)합금/탄탈(Ta) 또는 니오브(Nb)/크롬(Cr)이 적층된 구조로 형성되고, 상기 절연막은 포토 BCB 산화막으로 형성된 것을 특징으로 한다.In order to achieve the above object, the present invention provides a first via hole by forming a protective film on a semiconductor substrate on which a conductive layer is formed on the top through a predetermined device fabrication process, and then patterning the protective film to expose a pad region of the conductive layer. Forming a photoresist film on the entire upper surface from the step; patterning the photoresist film using a metallization mask; and connecting the entire upper surface to be connected to the conductive layer through the first via hole from the step. Removing the photoresist film and the metal layer formed on the photoresist film after forming a metal layer on the photoresist layer; forming an insulating film on the entire upper surface from the step; patterning the insulating film to expose the pad region of the metal layer, thereby forming a second via hole. Forming and filling a lead in the second via hole from the step; The metal layer is formed of a structure in which aluminum (Al) alloy / tantalum (Ta) or niobium (Nb) / chromium (Cr) are laminated, and the insulating layer is formed of a photo BCB oxide film. .
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2a 내지 2e는 본 발명에 따른 반도체 소자의 패키지 방법을 설명하기 위한 소자의 단면도로서, 도 3을 참조하여 설명하면 다음과 같다.2A through 2E are cross-sectional views of devices for describing a method of packaging a semiconductor device according to the present invention, which will be described below with reference to FIG. 3.
도 2a는 소정의 소자 제조 공정을 거쳐 최상부에 도전층(13)이 형성된 반도체 기판(11)상에 보호막(14)을 형성한 후 상기 도전층(13)의 패드영역이 노출되도록 상기 보호막(14)을 패터닝하여 제 1 비아홀(18)을 형성한 상태의 단면도이다.FIG. 2A illustrates a passivation layer 14 formed on a semiconductor substrate 11 having a conductive layer 13 formed on top thereof through a predetermined device fabrication process so that the pad region of the conductive layer 13 is exposed. ) Is a cross-sectional view of the first via hole 18 formed by patterning.
도 2b는 전체 상부면에 감광막(19)을 형성한 후 금속배선 마스크를 이용하여 상기 감광막(19)을 패터닝한 상태의 단면도로서, 이때 상기 감광막(19)은 도 3에 도시된 바와 같이 상기 제 1 비아홀(18)로부터 제 2 비아홀이 형성될 위치까지 소저의 폭으로 상기 보호막(14)이 노출되도록 패터닝된다.FIG. 2B is a cross-sectional view of the photoresist layer 19 patterned using a metallization mask after the photoresist layer 19 is formed on the entire upper surface, wherein the photoresist layer 19 is formed as shown in FIG. 3. The passivation layer 14 is patterned to expose the passivation layer 14 from the first via hole 18 to the position where the second via hole is to be formed.
도 2c는 상기 제 1 비아홀(18)을 통해 상기 도전층(13)과 접속되도록 전체 상부면에 금속층(15)을 형성한 후 상기 감광막(9) 및 상기 감광막(9)상에 형성된 금속층(15)을 제거하므로써 금속배선(15A)이 형성된 상태의 단면도로서, 상기 금속층(15)은 알루미늄(Al)합금/탄탈(Ta) 또는 니오브(Nb)/크롬(Cr)이 적층된 다층 구조로 형성되며, 상기 알루미늄(Al)합금은 알루미늄(Al)에 실리콘(Si), 하프늄(Hf), 구리(Cu) 등이 첨가된다. 또한 상기 금속층(15)은 상온 내지 150 ℃의 온도 및 1 내지 5 mTorr의 압력 상태의 챔버(Chamber)에서 스퍼터링(Sputtering) 방법으로 증착되며, 이때 상기 챔버에는 1 내지 5 KW의 전력이 인가된다.FIG. 2C illustrates that the metal layer 15 is formed on the photoresist film 9 and the photoresist film 9 after the metal layer 15 is formed on the entire upper surface thereof so as to be connected to the conductive layer 13 through the first via hole 18. Is a cross-sectional view of a metal wiring 15A formed by removing the metal layer 15. The metal layer 15 is formed in a multilayer structure in which aluminum (Al) alloy / tantalum (Ta) or niobium (Nb) / chromium (Cr) are stacked. In the aluminum (Al) alloy, silicon (Si), hafnium (Hf), copper (Cu), and the like are added to aluminum (Al). In addition, the metal layer 15 is deposited by a sputtering method in a chamber at a temperature of room temperature to 150 ° C. and a pressure of 1 to 5 mTorr, and power of 1 to 5 KW is applied to the chamber.
도 2d는 전체 상부면에 절연막(16)을 형성한 후 상기 금속배선(15A)의 패드영역이 노출되도록 상기 절연막(16)을 패터닝하여 제 2 비아홀(20)을 형성한 상태의 단면도로서, 상기 절연막(16)은 포토(Photo) BCB 산화막으로 형성한다.FIG. 2D is a cross-sectional view of the second via hole 20 formed by forming the insulating film 16 on the entire upper surface and patterning the insulating film 16 to expose the pad region of the metal wiring 15A. The insulating film 16 is formed of a photo BCB oxide film.
도 2e는 상기 제 2 비아홀(20)내에 납(17)을 매립한 후 열처리한 상태의 단면도로서, 이후 웨이퍼로부터 칩을 분리시켜 패키지를 완성한다.FIG. 2E is a cross-sectional view of a state in which the lead 17 is embedded in the second via hole 20 and then heat-treated. Then, the chip is separated from the wafer to complete the package.
상기와 같이 본 발명은 종래와는 달리 상기 도전층의 패드영역을 노출시키기 위한 제 1 비아홀(18)을 형성한 후 상기 보호막(14)상에 감광막 패턴(19)을 형성하고 금속층(15)을 형성한다. 그러므로 상기 감광막(19)의 패터닝된 부분에 금속(15)이 매립되어 상기 감광막(19)을 제거하는 동시에 금속배선(15A)이 형성된다. 따라서 금속배선을 형성하기 위한 공정이 단순해지며, 제조 비용이 절감된다. 또한 상기 금속층(15)을 알루미늄(Al)합금/탄탈(Ta) 또는 니오브(Nb)/크롬(Cr)이 적층된 다층 구조로 형성하므로써 구리(Cu)가 함유되지 않아 구리(Cu)의 부식으로 인한 불량의 발생이 방지되며, 상기 금속배선(15A)과 납(17)의 접착성이 향상된다.As described above, according to the present invention, after forming the first via hole 18 for exposing the pad region of the conductive layer, the photosensitive film pattern 19 is formed on the passivation layer 14 and the metal layer 15 is formed. Form. Therefore, the metal 15 is embedded in the patterned portion of the photoresist film 19 to remove the photoresist film 19 and to form the metal wiring 15A. Therefore, the process for forming the metal wiring is simplified, and the manufacturing cost is reduced. In addition, since the metal layer 15 is formed in a multilayer structure in which aluminum (Al) alloy / tantalum (Ta) or niobium (Nb) / chromium (Cr) is laminated, copper (Cu) is not contained and corrosion of copper (Cu) is caused. Due to the occurrence of the defect is prevented, the adhesion between the metal wiring 15A and the lead 17 is improved.
상술한 바와 같이 본 발명에 의하면 금속층을 형성한 후 상기 금속층상에 금속층을 패터닝하기 위한 감광막 패턴을 형성하지 않고, 감광막 패턴을 형성한 후 금속을 증착하므로써 공정의 단순화가 이루어진다. 또한 본 발명은 금속층으로써 알루미늄(Al)합금/탄탈(Ta) 또는 니오브(Nb)/크롬(Cr)을 이용하므로써 종래의 구리(Cu)의 사용으로 인한 불량의 발생이 방지되고, 금속배선과 납과의 접착성이 향상된다. 그러므로 본 발명을 이용하면 공정의 안정성 및 수율이 향상될 수 있다.As described above, according to the present invention, the process is simplified by forming a photoresist pattern and then depositing a metal without forming a photoresist pattern for patterning the metal layer on the metal layer after forming the metal layer. In addition, by using aluminum (Al) alloy / tantalum (Ta) or niobium (Nb) / chromium (Cr) as the metal layer, the present invention prevents the occurrence of defects due to the use of conventional copper (Cu), and the metal wiring and lead Adhesion with is improved. Therefore, using the present invention can improve the stability and yield of the process.
도 1a 내지 1d는 종래 반도체 소자의 패키지 방법을 설명하기 위한 소자의 단면도.1A to 1D are cross-sectional views of a device for explaining a method of packaging a conventional semiconductor device.
도 2a 내지 2e는 본 발명에 따른 반도체 소자의 패키지 방법을 설명하기 위한 소자의 단면도.2A to 2E are cross-sectional views of devices for explaining a method for packaging a semiconductor device according to the present invention.
도 3은 도 2b를 설명하기 위한 평면도.3 is a plan view for explaining FIG. 2B;
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for main parts of the drawings>
1 및 11: 반도체 기판 3 및 13: 도전층1 and 11: semiconductor substrates 3 and 13: conductive layer
4 및 14: 보호막 5 및 15: 금속층4 and 14: protective films 5 and 15: metal layer
6 및 16: 절연막 7 및 17: 납6 and 16: insulating films 7 and 17: lead
8 및 18: 제 1 비아홀 9 및 19: 감광막8 and 18: first via hole 9 and 19: photosensitive film
10 및 20: 제 2 비아홀10 and 20: second via hole
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980061371A KR100571265B1 (en) | 1998-12-30 | 1998-12-30 | Package Method of Semiconductor Device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980061371A KR100571265B1 (en) | 1998-12-30 | 1998-12-30 | Package Method of Semiconductor Device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20000044868A KR20000044868A (en) | 2000-07-15 |
| KR100571265B1 true KR100571265B1 (en) | 2007-12-07 |
Family
ID=19568123
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980061371A KR100571265B1 (en) | 1998-12-30 | 1998-12-30 | Package Method of Semiconductor Device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100571265B1 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19980032007A (en) * | 1995-11-29 | 1998-07-25 | 가네꼬 히사시 | Interconnect Structures and Methods of Manufacturing the Same |
-
1998
- 1998-12-30 KR KR1019980061371A patent/KR100571265B1/en not_active IP Right Cessation
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19980032007A (en) * | 1995-11-29 | 1998-07-25 | 가네꼬 히사시 | Interconnect Structures and Methods of Manufacturing the Same |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20000044868A (en) | 2000-07-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6518092B2 (en) | Semiconductor device and method for manufacturing | |
| KR100500010B1 (en) | Semiconductor device and method for fabricating the same | |
| US7468292B2 (en) | Method of making wafer level package structure by grinding the backside thereof and then forming metal layer on the ground side | |
| CA1282188C (en) | Multilayer metallization method for integrated circuits | |
| EP0411165B1 (en) | Method of forming of an integrated circuit chip packaging structure | |
| JP2943805B1 (en) | Semiconductor device and manufacturing method thereof | |
| JP3848080B2 (en) | Manufacturing method of semiconductor device | |
| KR100659801B1 (en) | Wire bonding to copper | |
| JPH0778826A (en) | Preparation of chip bump | |
| EP0583877B1 (en) | Bond pad structure of an integrated circuit and manufacturing method thereof | |
| US5705856A (en) | Semiconductor device | |
| JPH11330231A (en) | Metal coat structure | |
| US6818539B1 (en) | Semiconductor devices and methods of fabricating the same | |
| EP0275588B1 (en) | Method of fabricating a semiconductor device with reduced packaging stress | |
| US7381636B2 (en) | Planar bond pad design and method of making the same | |
| US7015129B2 (en) | Bond pad scheme for Cu process | |
| KR100571265B1 (en) | Package Method of Semiconductor Device | |
| CN101308829B (en) | Semiconductor device and method for manufacturing BOAC/COA | |
| US7163884B2 (en) | Semiconductor device and fabrication method thereof | |
| JP4686962B2 (en) | Manufacturing method of semiconductor device | |
| JP3997554B2 (en) | Manufacturing method of semiconductor device | |
| KR100374300B1 (en) | Copper layer for semiconductor fabrication method | |
| JP2005129862A (en) | Semiconductor package and method for manufacturing the same | |
| TW516136B (en) | Manufacturing method for aluminum bump | |
| KR100876286B1 (en) | Semiconductor device and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20110325 Year of fee payment: 6 |
|
| LAPS | Lapse due to unpaid annual fee |