JP3087819B2 - Terminal electrode formation method for solder bump mounting - Google Patents
Terminal electrode formation method for solder bump mountingInfo
- Publication number
- JP3087819B2 JP3087819B2 JP07226220A JP22622095A JP3087819B2 JP 3087819 B2 JP3087819 B2 JP 3087819B2 JP 07226220 A JP07226220 A JP 07226220A JP 22622095 A JP22622095 A JP 22622095A JP 3087819 B2 JP3087819 B2 JP 3087819B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- bump
- solder
- mounting
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体素子等をは
んだバンプ実装するための端子電極の形成方法に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a terminal electrode for mounting a semiconductor element or the like on a solder bump.
【０００２】[0002]
【従来の技術】従来のはんだバンプ実装するための端子
電極形成方法としては、一般的に図２に示すような例が
ある。先ず、図２（ａ）に示すように絶縁性基板１上に
例えば、銅からなる配線電極パッド２、および絶縁保護
膜３をフォトリソ工程、電解めっき工程等により製作す
る。2. Description of the Related Art As a conventional method for forming a terminal electrode for mounting a solder bump, there is generally an example as shown in FIG. First, as shown in FIG. 2A, for example, a wiring electrode pad 2 made of copper and an insulating protective film 3 are manufactured on an insulating substrate 1 by a photolithography process, an electrolytic plating process, or the like.
【０００３】次に、この上に、図２（ｂ）に示すよう
に、絶縁保護膜３の開口部内の配線電極パッド２とが電
気的に接合するように、密着性、相互拡散、はんだ濡れ
性を考慮したバリアメタル６を形成し、該バリアメタル
６の上部に接着層５を形成する。更に、その上に、図２
（ｃ）に示すような、液状レジスト７をスピナ等で塗布
し、絶縁性基板１上に形成した配線電極パッド２上に所
望の大きさのバンプ径を開口する。Next, as shown in FIG. 2B, adhesion, mutual diffusion, and solder wetting are performed so that the wiring electrode pads 2 in the openings of the insulating protective film 3 are electrically connected to each other. A barrier metal 6 is formed in consideration of the properties, and an adhesive layer 5 is formed on the barrier metal 6. Furthermore, FIG.
As shown in (c), a liquid resist 7 is applied with a spinner or the like, and a desired diameter of the bump is formed on the wiring electrode pad 2 formed on the insulating substrate 1.
【０００４】引続き、図２（ｄ）に示すように、この液
状レジスト７をめっきマスクとし、露出したはんだバン
プ接着層５にのみ、はんだを析出させ、加熱処理しては
んだを球状に成形し、はんだバンプ４を形成する。最後
に、図２（ｅ）に示すように、液状レジスト７を除去
し、不要なバリアメタル６、バンプ接着層５をエッチン
グ除去する。[0004] Subsequently, as shown in FIG. 2 (d), using the liquid resist 7 as a plating mask, the solder is deposited only on the exposed solder bump adhesive layer 5, and heat-treated to form the solder into a spherical shape. A solder bump 4 is formed. Finally, as shown in FIG. 2E, the liquid resist 7 is removed, and the unnecessary barrier metal 6 and unnecessary bump adhesive layer 5 are removed by etching.
【０００５】[0005]
【発明が解決しようとする課題】図２に示す従来のはん
だバンプ実装用端子電極形成方法では、絶縁保護膜３と
配線電極パッド２との界面へのはんだ流れ込みを抑える
ことが出来るが、しかし、製作工程数が増加し、はんだ
バンプ実装用端子電極を製作する歩留りが低下すること
や、コストが高くなる等の問題があった。According to the conventional method of forming a terminal electrode for mounting a solder bump shown in FIG. 2, it is possible to suppress the flow of solder into the interface between the insulating protective film 3 and the wiring electrode pad 2. There are problems such as an increase in the number of manufacturing steps, a reduction in the yield of manufacturing the terminal electrodes for solder bump mounting, and an increase in cost.
【０００６】一方、図３に示すように、予めバンプ接着
層形成用として液状レジスト７を塗布し、フォトプロセ
スにより所望の大きさに開口し、その後にニッケルと金
とからなるバンプ接着層５を形成することにより、はん
だバンプ実装用端子電極構造を製作することが考えられ
ている（特願平６−３２４４４５号）。先ず、図３
（ａ）に示すように、絶縁性基板１上に例えば、銅から
なる配線電極パッド２を形成した後、酸化処理を行い、
酸化処理層８を形成する。On the other hand, as shown in FIG. 3, a liquid resist 7 is applied in advance for forming a bump adhesive layer, an opening is formed to a desired size by a photo process, and then a bump adhesive layer 5 made of nickel and gold is removed. The formation of a terminal electrode structure for mounting a solder bump by forming the same has been considered (Japanese Patent Application No. 6-324445). First, FIG.
As shown in (a), after forming a wiring electrode pad 2 made of, for example, copper on an insulating substrate 1, an oxidation process is performed,
An oxidation treatment layer 8 is formed.
【０００７】次に、酸化処理層８上に、図３（ｂ）に示
すように、バンプ接着層形成用として液状レジスト７を
塗布し、露光、現像等のフォトプロセスにより所望の大
きさに開口し、その後ニッケルと金からなるバンプ接着
層５を形成する。引き続き、図３（ｃ）に示すように、
不要になった液状レジスト７を除去した後、図３（ｄ）
に示すように、バンプ接着層５の周囲を取り囲むように
絶縁保護膜３を形成して、バンプ接着層５の表面を開口
する。Next, as shown in FIG. 3B, a liquid resist 7 is applied on the oxidized layer 8 for forming a bump adhesive layer, and the opening is formed to a desired size by a photo process such as exposure and development. Then, a bump adhesive layer 5 made of nickel and gold is formed. Subsequently, as shown in FIG.
After removing the unnecessary liquid resist 7, FIG.
As shown in (2), the insulating protective film 3 is formed so as to surround the periphery of the bump bonding layer 5, and the surface of the bump bonding layer 5 is opened.
【０００８】更に、図３（ｅ）に示すように、露出した
バンプ接着層５上のみに、加熱処理層の手段により選択
的にはんだバンプ４を形成する。Further, as shown in FIG. 3E, the solder bumps 4 are selectively formed only on the exposed bump bonding layer 5 by means of a heat treatment layer.
【０００９】このような方法により製作されたはんだバ
ンプ実装用端子電極構造は、配線電極パッド２の表面に
酸化処理層８を形成して、配線電極パッド２のはんだ濡
れ性を低下させ、バンプ接着層５以外へのはんだ濡れ込
みを防止することが可能であり、更に、前述した従来技
術と比較して、バリアメタル６を不要とできるため、製
作工程数を削減することができる。In the terminal electrode structure for mounting a solder bump manufactured by such a method, an oxidized layer 8 is formed on the surface of the wiring electrode pad 2 to reduce the solder wettability of the wiring electrode pad 2 and to reduce the bump adhesion. It is possible to prevent solder wetting into portions other than the layer 5, and furthermore, it is possible to eliminate the need for the barrier metal 6 as compared with the above-described conventional technology, so that the number of manufacturing steps can be reduced.
【００１０】本発明は、上記従来技術に鑑みて成された
ものであり、その目的は、はんだバンプ形成或いはバン
プ実装時に、配線電極パッドと絶縁保護膜の界面にはん
だが流れ込むのを防ぐとともに、製作工程の短縮化が図
れ、更に製作コストを低減することが可能な、信頼性の
高いはんだバンプ実装用端子電極形成方法を提供するこ
とにある。SUMMARY OF THE INVENTION The present invention has been made in view of the above prior art, and has as its object to prevent solder from flowing into an interface between a wiring electrode pad and an insulating protective film during solder bump formation or bump mounting. An object of the present invention is to provide a highly reliable method for forming a terminal electrode for solder bump mounting, which can shorten the manufacturing process and further reduce the manufacturing cost.
【００１１】[0011]
【課題を解決するための手段】上記本発明の目的を達成
する本発明の構成は、絶縁性基板或いは半導体素子と他
の基板或いは素子と電気的・機械的に接続するための電
極端子であって、前記絶縁性基板或いは半導体素子上に
形成された信号用電極、バイアス供給用電極又は接地用
電極と、前記電極上を覆うように形成され、かつ前記電
極上に少なくとも１個以上の開口部を設けた絶縁保護膜
とから構成されるはんだバンプ実装用端子電極構造にお
いて、前記絶縁性基板或いは半導体素子上の各電極と、
該電極表面に形成する酸化処理層と、該酸化処理層上の
バンプ実装用端子電極形成部分のみに少なくとも１個以
上の開口部を設ける絶縁保持膜とを、この順に形成し、
その後に該絶縁保護膜の開口部内に金属導体層からなる
バンプ接着層をめっき形成することを特徴とする。The structure of the present invention which achieves the object of the present invention is an electrode terminal for electrically and mechanically connecting an insulating substrate or semiconductor element to another substrate or element. A signal electrode, a bias supply electrode, or a ground electrode formed on the insulating substrate or the semiconductor element; and at least one opening formed on the electrode and covering the electrode. In the terminal electrode structure for solder bump mounting comprising an insulating protective film provided with, each electrode on the insulating substrate or semiconductor element,
Forming an oxidation treatment layer formed on the electrode surface and an insulating holding film providing at least one opening only in a bump mounting terminal electrode formation portion on the oxidation treatment layer,
Thereafter, a bump adhesive layer made of a metal conductor layer is formed by plating in the opening of the insulating protective film.
【００１２】ここで、前記バンプ接着層は、はんだ濡れ
性及び耐蝕性を有する金属導体層であることを特徴とす
る。本発明のはんだバンプ実装用端子電極形成方法にお
いては、絶縁保護膜を形成し、その後に、該絶縁保護膜
をめっきレジストとして機能させてバンプ接着層を形成
することから、はんだバンプ実装用端手電極を製作する
工程数を減らすことができる。Here, the bump bonding layer is a metal conductor layer having solder wettability and corrosion resistance. In the method of forming a terminal electrode for mounting a solder bump according to the present invention, an insulating protective film is formed, and then the insulating protective film functions as a plating resist to form a bump adhesive layer. The number of steps for manufacturing the electrode can be reduced.
【００１３】[0013]
【発明の実施の形態】以下、本発明の実施例を図面に従
い更に詳細に説明する。図１に本発明の一実施例を示
す。図１は、本発明の一実施例に係るバンプ実装用端子
電極の形成方法の手順を示す工程図である。まず、図１
（ａ）に示すように、絶縁性基板１上に例えば銅からな
る配線電極パッド２を形成した後、酸化処理を行い、酸
化処理層８を形成する。酸化処理層８は、絶縁性基板１
上の銅で形成した配線電極パッド２を酸化処理して作製
して酸化銅が主成分の層である。Embodiments of the present invention will be described below in more detail with reference to the drawings. FIG. 1 shows an embodiment of the present invention. FIG. 1 is a process chart showing a procedure of a method for forming a bump mounting terminal electrode according to one embodiment of the present invention. First, FIG.
As shown in FIG. 1A, after forming a wiring electrode pad 2 made of, for example, copper on an insulating substrate 1, an oxidation treatment is performed to form an oxidation treatment layer 8. The oxidation treatment layer 8 is formed on the insulating substrate 1.
The wiring electrode pad 2 made of copper above is produced by oxidizing treatment and is a layer mainly composed of copper oxide.
【００１４】次に、図１（ｂ）に示すように、絶縁保護
膜３を酸化処理層８の表面の一部が露出するように開口
し形成する。例えば、感光性ポリイミドをスピンナで回
転塗布し、フォトプロセス工程で開口部を形成すること
ができる。絶縁保護膜３は、はんだバンプ４をバンプ接
着層５に接着する際に、絶縁保護膜３の開口部のみには
んだを溜めるために作製する。Next, as shown in FIG. 1B, an insulating protective film 3 is formed so as to have an opening so that a part of the surface of the oxidation treatment layer 8 is exposed. For example, the photosensitive polyimide can be spin-coated with a spinner, and an opening can be formed in a photo process step. The insulating protective film 3 is formed so that when the solder bump 4 is bonded to the bump bonding layer 5, the solder is stored only in the opening of the insulating protective film 3.
【００１５】引き続き、図１（ｃ）に示すように、絶縁
保護膜３内の酸化処理層８上に、ニッケルと金からなる
バンプ接着層５を形成する。バンプ接着層５は、無電解
めっき工程或いは電界めっき工程により製作する。バン
プ接着層５は、酸化処理層８の上に直接作製した金属導
体層であり、ニッケルと金の金属導体膜構成としてい
る。更に、図１（ｄ）に示すように、露出したバンプ接
着層５上のみに、加熱処理等の手段により選択的にはん
だバンプ４を形成する。Subsequently, as shown in FIG. 1C, a bump bonding layer 5 made of nickel and gold is formed on the oxidation treatment layer 8 in the insulating protection film 3. The bump bonding layer 5 is manufactured by an electroless plating process or an electrolytic plating process. The bump bonding layer 5 is a metal conductor layer directly formed on the oxidation treatment layer 8, and has a metal conductor film structure of nickel and gold. Further, as shown in FIG. 1D, the solder bumps 4 are selectively formed only on the exposed bump bonding layer 5 by means such as a heat treatment.
【００１６】本実施例は、バンプ実装用端子電極形成部
分のみを開口した絶縁保護膜３を予め形成し、めっきレ
ジストとして機能させるため、そのままバンプ接着層５
のめっき工程に移すことができ、容易にはんだバンプ実
装用端子電極を形成することができる。そのため、予め
バンプ接着層形成用として液状レジスト７を塗布する必
要があった図２に示す方法に比較して、製作工程数を一
層削減し、製作コストを低減することが可能となる。In this embodiment, in order to form an insulating protective film 3 in which only a portion for forming a bump mounting terminal electrode is opened and to function as a plating resist, the bump bonding layer 5 is directly used.
And the solder bump mounting terminal electrode can be easily formed. Therefore, as compared with the method shown in FIG. 2 in which the liquid resist 7 needs to be applied in advance for forming the bump adhesive layer, the number of manufacturing steps can be further reduced, and the manufacturing cost can be reduced.
【００１７】更に、配線電極パッド２の表面に酸化処理
層８を形成して、配線電極パッド２のはんだ濡れ性を低
下させていることから、図３に示すバンプはんだバンプ
実装用端子電極構造のように（特願平６−３２４４４５
号）、接着層５以外のはんだ濡れ込みを防止する利点を
損なうこともない。尚、本実施例のバンプ接着層５の金
属導体膜構成は、ニッケルと金の金属膜構成としたが、
はんだ濡れ性及びはんだ耐蝕性を有する金属であれば、
ニッケルに変えて使用できる。Further, since an oxidized layer 8 is formed on the surface of the wiring electrode pad 2 to reduce the solder wettability of the wiring electrode pad 2, the terminal electrode structure for bump solder bump mounting shown in FIG. Yo (Japanese Patent Application No. 6-324445)
No.), the advantage of preventing solder wetting other than the adhesive layer 5 is not impaired. Although the metal conductor film configuration of the bump bonding layer 5 of the present embodiment was a nickel and gold metal film configuration,
If the metal has solder wettability and solder corrosion resistance,
Can be used instead of nickel.
【００１８】[0018]
【発明の効果】以上、実施例に基づいて詳細に説明した
ように、半導体素子等をはんだバンプ実装するのに、本
発明のはんだバンプ実装用端子電極形成方法を使用する
ことによって、はんだバンプ実装用端子電極を作製する
工程数を減らすことができるため、製作歩留まりを向上
することができるとともに、生産性、コスト、信頼性か
らみて工業的価値は極めて高い。As described above in detail based on the embodiments, the method of forming a terminal electrode for mounting a solder bump according to the present invention is used for mounting a semiconductor element or the like with a solder bump. Since the number of steps for manufacturing the terminal electrode can be reduced, the manufacturing yield can be improved, and the industrial value is extremely high in terms of productivity, cost and reliability.
【図１】本発明の一実施例に係るはんだバンプ実装用端
子電極形成方法の製作工程の概要を示す断面図である。FIG. 1 is a cross-sectional view showing an outline of a manufacturing process of a method for forming a terminal electrode for solder bump mounting according to an embodiment of the present invention.
【図２】従来例で例示したはんだバンプ実装用端子電極
形成方法の製作工程の概要を示す断面図である。FIG. 2 is a cross-sectional view illustrating an outline of a manufacturing process of a method of forming a terminal electrode for mounting a solder bump illustrated in a conventional example.
【図３】先願に係るはんだバンプ実装用端子電極形成方
法の製作工程の概要を示す断面図である。FIG. 3 is a cross-sectional view illustrating an outline of a manufacturing process of a method of forming a terminal electrode for mounting a solder bump according to the prior application.
１ 絶縁性基板 ２ 配線電極パッド ３ 絶縁保護膜 ４ はんだバンプ ５ バンプ接着層 ６ バリアメタル ７ 液状レジスト ８ 酸化処理層 DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Wiring electrode pad 3 Insulation protective film 4 Solder bump 5 Bump adhesion layer 6 Barrier metal 7 Liquid resist 8 Oxidation treatment layer
フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/60 Continuation of front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21/60
Claims (2)
或いは素子と電気的・機械的に接続するための電極端子
であって、前記絶縁性基板或いは半導体素子上に形成さ
れた信号用電極、バイアス供給用電極又は接地用電極
と、前記電極上を覆うように形成され、かつ前記電極上
に少なくとも１個以上の開口部を設けた絶縁保護膜とか
ら構成されるはんだバンプ実装用端子電極構造におい
て、 前記絶縁性基板或いは半導体素子上の各電極と、該電極
表面に形成する酸化処理層と、該酸化処理層上のバンプ
実装用端子電極形成部分のみに少なくとも１個以上の開
口部を設ける絶縁保持膜とを、この順に形成し、その後
に該絶縁保護膜の開口部内に金属導体層からなるバンプ
接着層をめっき形成することを特徴とするはんだバンプ
実装用端子電極形成方法。An electrode terminal for electrically and mechanically connecting an insulating substrate or a semiconductor element to another substrate or an element, comprising: a signal electrode formed on the insulating substrate or the semiconductor element; A terminal electrode structure for mounting a solder bump, comprising: a bias supply electrode or a ground electrode; and an insulating protective film formed so as to cover the electrode and having at least one opening on the electrode. In the above, at least one or more openings are provided only in each electrode on the insulating substrate or the semiconductor element, an oxidized layer formed on the surface of the electrode, and only a bump mounting terminal electrode forming portion on the oxidized layer. Forming an insulating holding film in this order, and thereafter plating a bump adhesive layer made of a metal conductor layer in an opening of the insulating protective film. Method.
耐蝕性を有する金属導体層であることを特徴とする請求
項１記載のはんだバンプ実装用端子電極形成方法。2. The method according to claim 1, wherein the bump adhesive layer is a metal conductor layer having solder wettability and corrosion resistance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP07226220A JP3087819B2 (en) | 1995-09-04 | 1995-09-04 | Terminal electrode formation method for solder bump mounting |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP07226220A JP3087819B2 (en) | 1995-09-04 | 1995-09-04 | Terminal electrode formation method for solder bump mounting |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0974096A JPH0974096A (en) | 1997-03-18 |
| JP3087819B2 true JP3087819B2 (en) | 2000-09-11 |
Family
ID=16841783
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP07226220A Expired - Fee Related JP3087819B2 (en) | 1995-09-04 | 1995-09-04 | Terminal electrode formation method for solder bump mounting |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3087819B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11340265A (en) | 1998-05-22 | 1999-12-10 | Sony Corp | Semiconductor device and its manufacture |
| US6162718A (en) * | 1998-09-04 | 2000-12-19 | Advanced Micro Devices | High speed bump plating/forming |
| JP3767821B2 (en) * | 2003-01-22 | 2006-04-19 | 松下電器産業株式会社 | Semiconductor device design method |
| JP4061506B2 (en) * | 2005-06-21 | 2008-03-19 | セイコーエプソン株式会社 | Manufacturing method of semiconductor device |
-
1995
- 1995-09-04 JP JP07226220A patent/JP3087819B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0974096A (en) | 1997-03-18 |
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