JPH03253061A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03253061A JPH03253061A JP5097290A JP5097290A JPH03253061A JP H03253061 A JPH03253061 A JP H03253061A JP 5097290 A JP5097290 A JP 5097290A JP 5097290 A JP5097290 A JP 5097290A JP H03253061 A JPH03253061 A JP H03253061A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- film
- diffusion layer
- insulating film
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 239000010410 layer Substances 0.000 claims abstract description 62
- 238000009792 diffusion process Methods 0.000 claims abstract description 32
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 14
- 239000011229 interlayer Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 230000010354 integration Effects 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract description 2
- 238000005530 etching Methods 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device.
従来の半導体装置は、第３図に示す如く、拡散層２と接
続するコンタクト電極７と配線１０とを接続するために
設けたヴィアホール９は拡散層２の上に配置しない構造
となっていた。In the conventional semiconductor device, as shown in FIG. 3, the via hole 9 provided for connecting the contact electrode 7 connected to the diffusion layer 2 and the wiring 10 was not placed above the diffusion layer 2. .
上述した従来の半導体装置はヴィアホールを拡散層上に
配置した場合には、ヴィアホール直下の配線層にピンホ
ールが発生するとヴィアホール形成のエツチングにより
このピンホールが拡散層まで達し、拡散層をエツチング
する。エツチング量は少量でも浅いＰＮ接合を形成して
いる場合はこれを破壊する恐れがある。In the conventional semiconductor device described above, when a via hole is placed on a diffusion layer, if a pinhole occurs in the wiring layer directly under the via hole, the pinhole will reach the diffusion layer due to the etching of the via hole formation, and the diffusion layer will be damaged. etching. Even if the amount of etching is small, if a shallow PN junction is formed, it may be destroyed.
また、拡散層とコンタクト電極を接続するコンタクトホ
ールがヴィアホールの下にあり、しかもコンタクト部が
白金等のバリヤメタルで覆われている場合は、ヴィアホ
ール形成のエツチングによってバリヤメタルがエツチン
グされる恐れがある。そのため、ヴィアホールを配置す
るための領域を拡散層上以外の別の位置に設ける必要が
あり、集積回路装置のレイアウト高密度化が困難になる
という欠点がある。Additionally, if the contact hole that connects the diffusion layer and the contact electrode is located below the via hole, and the contact part is covered with a barrier metal such as platinum, there is a risk that the barrier metal will be etched during the etching to form the via hole. . Therefore, it is necessary to provide a region for arranging the via hole at a position other than on the diffusion layer, which has the disadvantage that it becomes difficult to increase the density of the layout of the integrated circuit device.
本発明の半導体装置は、−導電型半導体基板上に設けた
一導電型又は逆導電型の拡散層と、前記拡散層上の中央
部に設けた多結晶シリコン層と、前記多結晶シリコン層
を含む表面に設けた絶縁膜と、前記拡散層上の中央部に
設けた環状のコンタクトホールと、前記コンタクトホー
ルの前記拡散層と接続して前記中央部の前記絶縁膜上に
設けたコンタクト電極と、前記コンタクト電極を含む表
面に設けた層間絶縁膜と、前記拡散層上の中央部の前記
層間絶縁膜上に設けたヴィアホールと、前記ヴィアホー
ルの前記コンタクト電極と接続して前記層間絶縁膜上を
延在する配線とを有する。The semiconductor device of the present invention includes a diffusion layer of one conductivity type or an opposite conductivity type provided on a -conductivity type semiconductor substrate, a polycrystalline silicon layer provided in a central portion on the diffusion layer, and the polycrystalline silicon layer. an insulating film provided on a surface containing the diffusion layer, an annular contact hole provided in a central portion above the diffusion layer, and a contact electrode provided on the insulating film in the central portion connected to the diffusion layer of the contact hole; , an interlayer insulating film provided on a surface including the contact electrode, a via hole provided on the interlayer insulating film at a central portion above the diffusion layer, and an interlayer insulating film connected to the contact electrode in the via hole. and wiring extending thereover.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）、（ｂ）は本発明の第１の実施例の平面図
及びＡ−Ａ′線断面図である。FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along line A-A' of a first embodiment of the present invention.
第１図（ａ）、（ｂ）に示すように、Ｐ型シリコン基板
１の上にＮ型の不純物を拡散させて選択的に拡散層２を
設け、拡散層２を含む表面に酸化シリコン膜３を設ける
６次に、拡散層２の中央部の酸化シリコン膜３の上に選
択的に多結晶シリコン層６を形成する。次に、多結晶シ
リコン層６を含む表面に絶縁膜４を設け、多結晶シリコ
ン層６の外周の絶縁膜４及び酸化シリコン膜３を順次エ
ツチングして環状のコンタクトホール５を形成する。次
に、コンタクトホール５を含む表面に選択的にアルミニ
ウム層のコンタクト電極７を設けてコンタクトホール５
の拡散層３と接続する。次に、コンタクト電極７を含む
表面に酸化シリコン膜等の層間絶縁膜８を設け、拡散層
２の上の層間絶縁膜８にヴィアホール９を設ける。次に
、ヴィアホール９のコンタクト電極７と接続して層間絶
縁膜８の上に延在するアルミニウム層等の配線１０を設
ける。As shown in FIGS. 1(a) and 1(b), a diffusion layer 2 is selectively provided by diffusing N-type impurities on a P-type silicon substrate 1, and a silicon oxide film is formed on the surface including the diffusion layer 2. Next, a polycrystalline silicon layer 6 is selectively formed on the silicon oxide film 3 at the center of the diffusion layer 2. Next, an insulating film 4 is provided on the surface including the polycrystalline silicon layer 6, and the insulating film 4 and the silicon oxide film 3 on the outer periphery of the polycrystalline silicon layer 6 are sequentially etched to form an annular contact hole 5. Next, a contact electrode 7 of an aluminum layer is selectively provided on the surface including the contact hole 5, and the contact hole 5 is
It is connected to the diffusion layer 3 of. Next, an interlayer insulating film 8 such as a silicon oxide film is provided on the surface including the contact electrode 7 , and a via hole 9 is provided in the interlayer insulating film 8 above the diffusion layer 2 . Next, a wiring 10 made of an aluminum layer or the like is provided to connect to the contact electrode 7 in the via hole 9 and extend over the interlayer insulating film 8 .
通常、このヴィアホール９を設けるためのエツチングに
は酸化シリコン膜、窒化シリコン膜に対してエツチング
量が多く、シリコン層に対してエツチング量の少ない異
方性エツチング法を使用する。ここで、アルミニウム層
はピンホールが生じ易く、ヴィアホール９の下の部分で
コンタクト電［７にピンホールが生じた場合、エツチン
グにより生じたピンホールが絶縁膜４をつき抜ける。し
かし直下の多結晶シリコン層６はエツチング量が少ない
ため、エツチングストッパーとなって、酸化シリコン膜
３には達しない。従って拡散層２がエツチングされるの
を防止できる。Normally, for etching to provide this via hole 9, an anisotropic etching method is used in which the amount of etching is large for the silicon oxide film and the silicon nitride film, and the amount of etching is small for the silicon layer. Here, pinholes are likely to occur in the aluminum layer, and if a pinhole is generated in the contact electrode [7] below the via hole 9, the pinhole generated by etching will penetrate through the insulating film 4. However, since the polycrystalline silicon layer 6 immediately below is etched in a small amount, it acts as an etching stopper and does not reach the silicon oxide film 3. Therefore, the diffusion layer 2 can be prevented from being etched.
第２図（ａ）、（ｂ）は本発明の第２の実施例の平面図
及びＢ−Ｂ’線断面図である。FIGS. 2(a) and 2(b) are a plan view and a sectional view taken along the line BB' of a second embodiment of the present invention.
第２図（ａ）、（ｂ）に示すように、拡散層２を含む表
面に設けた酸化シリコン膜３の拡散層２の上に開孔部を
設け、開孔部の拡散層２の表面にのみ多結晶シリコン層
６を設け、全面に絶縁膜４を堆積し、選択的にエツチン
グして多結晶シリコン層６の上の絶縁Ｍ４に環状のコン
タクトホール５を設けた以外は第１の実施例と同し構成
を有している。As shown in FIGS. 2(a) and 2(b), an opening is provided on the diffusion layer 2 of the silicon oxide film 3 provided on the surface including the diffusion layer 2, and the surface of the diffusion layer 2 in the opening is The first implementation except that a polycrystalline silicon layer 6 was provided only on the polycrystalline silicon layer 6, an insulating film 4 was deposited on the entire surface, and an annular contact hole 5 was formed in the insulating layer M4 on the polycrystalline silicon layer 6 by selective etching. It has the same configuration as the example.
第１の実施例と同様に、コンタクト電極７に生じたピン
ホールが絶縁膜４をつき抜けても、同様に多結晶シリコ
ン層６によってスト１され拡散層２がエツチングされる
のを防止できる。As in the first embodiment, even if a pinhole formed in the contact electrode 7 passes through the insulating film 4, the polycrystalline silicon layer 6 can similarly prevent the diffusion layer 2 from being etched.
以上説明したように本発明によれば、信頼性を損うこと
なく配線層間接続のヴィアホールを拡散層上に配置でき
るので、半導体集積回路の高集積化を向上させるという
効果かある。As described above, according to the present invention, a via hole for interconnection layer connection can be placed on a diffusion layer without impairing reliability, so that it has the effect of improving the degree of integration of semiconductor integrated circuits.
第１図（ａ）、（ｂ）は本発明の第１の実施例の平面図
及びＡ−Ａ’１ｌｉｆｒ面図、第２図（ａ）。
（ｂ）は本発明の第２の実施例の平面図及びＢ−Ｂ′線
断面図、第３図は従来の半導体装置の一例を示す平面図
である。
１・・・シリコン基板、２・・・拡散層、３・・・酸化
シリコン膜、４・・・絶縁膜、５・・・コンタクトホー
ル、６多結晶シリコン層、
７・・・コンタク
ト電極、
８・・・
層間絶縁膜、
９・・・ヴィアホール、
○・・・配線。FIGS. 1(a) and 1(b) are a plan view and an A-A'1lifr plane view of a first embodiment of the present invention, and FIG. 2(a) is a plan view of a first embodiment of the present invention. (b) is a plan view and a sectional view taken along the line B-B' of the second embodiment of the present invention, and FIG. 3 is a plan view showing an example of a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2... Diffusion layer, 3... Silicon oxide film, 4... Insulating film, 5... Contact hole, 6 Polycrystalline silicon layer, 7... Contact electrode, 8 ... Interlayer insulating film, 9... Via hole, ○... Wiring.
Claims (1)
の拡散層と、前記拡散層上の中央部に設けた多結晶シリ
コン層と、前記多結晶シリコン層を含む表面に設けた絶
縁膜と、前記拡散層上の中央部に設けた環状のコンタク
トホールと、前記コンタクトホールの前記拡散層と接続
して前記中央部の前記絶縁膜上に設けたコンタクト電極
と、前記コンタクト電極を含む表面に設けた層間絶縁膜
と、前記拡散層上の中央部の前記層間絶縁膜上に設けた
ヴィアホールと、前記ヴィアホールの前記コンタクト電
極と接続して前記層間絶縁膜上を延在する配線とを有す
ることを特徴とする半導体装置。A diffusion layer of one conductivity type or an opposite conductivity type provided on a semiconductor substrate of one conductivity type, a polycrystalline silicon layer provided at the center of the diffusion layer, and an insulating film provided on the surface including the polycrystalline silicon layer. a ring-shaped contact hole provided in a central portion above the diffusion layer; a contact electrode connected to the diffusion layer of the contact hole and provided on the insulating film in the central portion; and a surface including the contact electrode. an interlayer insulating film provided on the interlayer insulating film, a via hole provided on the interlayer insulating film at a central portion above the diffusion layer, and a wiring connected to the contact electrode of the via hole and extending on the interlayer insulating film. A semiconductor device characterized by having:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5097290A JPH03253061A (en) | 1990-03-01 | 1990-03-01 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5097290A JPH03253061A (en) | 1990-03-01 | 1990-03-01 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03253061A true JPH03253061A (en) | 1991-11-12 |
Family
ID=12873729
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5097290A Pending JPH03253061A (en) | 1990-03-01 | 1990-03-01 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03253061A (en) |
-
1990
- 1990-03-01 JP JP5097290A patent/JPH03253061A/en active Pending
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