JP2002351937A - Layout method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce noise from inside LSI and prevent wrong operation of LSI by the noise by laying out with taking reduction of noise generation into consideration. SOLUTION: An instance is arranged with taking noise into consideration in a layout and wiring process 130 using noise amount and degree of noise reduction found in a noise amount calculation process 100 and a wiring information extraction process 120. Thus, automatic layout with consideration of noise can be realized, and wrong operation of LSI by the noise can be prevented by reducing the noise from the inside LSI.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a layout method for a semiconductor integrated circuit device (hereinafter, referred to as an LSI).

[0002]

2. Description of the Related Art Conventionally, in an automatic layout of an LSI, a layout has been performed in consideration of an area and timing restrictions.

However, with the recent increase in the speed of the LSI, the influence of noise (EMI) generated by the LSI has caused
The SI often malfunctions. In the conventional automatic layout method, the problem of noise generated by the LSI was not taken into consideration. Therefore, even if the layout of the LSI satisfying the design constraints of the area and the timing was performed,
In an actual device, malfunction due to the influence of noise has often become a problem.

[0004]

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems. By performing a layout in consideration of a reduction in the amount of generated noise, noise generated from inside the LSI is reduced, and An object of the present invention is to prevent a malfunction of an LSI.

[0005]

In order to achieve the above object, a layout method according to the first aspect of the present invention performs a layout by calculating a noise amount when performing automatic layout in consideration of the influence of noise. A step of obtaining noise amount data for each specific circuit; a step of dividing the semiconductor integrated circuit device into a plurality of arrangement regions to determine a degree of noise reduction in each arrangement region; and each of the circuits according to the noise amount data The method includes a step of determining the divided placement area to be placed, a step of arranging the circuit in the determined placement area and wiring each circuit, and a step of confirming that a noise constraint condition is satisfied.

A layout method according to a second aspect is characterized in that, in the layout method according to the first aspect, a noise amount is calculated from a current capability of the cell. A layout method according to a third aspect is characterized in that, in the layout method according to the second aspect, the amount of noise is calculated based on the number of switching times for each circuit obtained by simulation.

A layout method according to a fourth aspect is characterized in that, in the layout method according to the second aspect, the amount of noise is calculated based on the number of times of switching for each circuit previously obtained.

A layout method according to a fifth aspect is characterized in that, in the layout method according to the second aspect, a noise amount is calculated based on a frequency of a signal input to each circuit. A layout method according to a sixth aspect is the layout method according to the first aspect, wherein a noise amount is calculated for each group including a plurality of instances as a specific circuit.

A layout method according to a seventh aspect is characterized in that, in the layout method according to the first aspect, a noise amount is calculated for each block as a specific circuit. In a layout method according to an eighth aspect, in the layout method according to the first aspect, the degree of noise reduction in each arrangement region is calculated from the position information of the terminal.

According to a ninth aspect of the present invention, in the layout method of the eighth aspect, a power supply terminal is used as the terminal. A layout method according to a tenth aspect is the layout method according to the eighth aspect, wherein an analog terminal is used as the terminal.

[0011] A layout method according to an eleventh aspect is characterized in that, in the layout method according to the first aspect, a wiring length of a power supply wiring is used in calculating the degree of noise reduction.

According to a twelfth aspect of the present invention, in the layout method of the first aspect, the wiring length and the wiring width of the power supply wiring are used in calculating the degree of noise reduction.

According to a thirteenth aspect of the present invention, in the layout method according to the first aspect, the wiring length, the wiring width, and the number of wiring regions having different wiring widths are used in calculating the degree of noise reduction. It is characterized by.

A layout method according to a fourteenth aspect is characterized in that, in the layout method according to the first aspect, the circuits having a large amount of noise are preferentially arranged in a region where the degree of noise reduction is large.

In a layout method according to a fifteenth aspect, in the layout method according to the first aspect, the total noise calculated from the noise amount and the degree of noise reduction is compared with a constraint to confirm that the noise constraint is satisfied. .

In a layout method according to a sixteenth aspect, in a semiconductor integrated circuit device having a plurality of clock systems, circuits operating with different clock signals are arranged adjacent to each other when performing automatic layout in consideration of the influence of noise. It is characterized by the following.

According to the above method, noise generated inside the LSI can be reduced, and malfunction of the LSI due to the noise can be prevented.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a configuration diagram of a layout system according to an embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a layout system of the present invention, D10 denotes data input to the layout system 1 of the present invention, and D11 denotes data and output data handled inside the layout system 1 of the present invention.

In the input data D10, D100 is a simulation input pattern used to calculate cell switching frequency information. D101 is a netlist used to check the connection relation of the circuits. D
Reference numeral 102 denotes a constraint having information such as a maximum allowable area value and a timing constraint in the layout. The constraint determines the performance of the LSI after the layout. D103 is a library having information on cells constituting D101 and information such as layout design rules. The cell information includes not only the physical structure of the cell but also the current capability of the cell required for calculating the amount of noise. Such information is also included. D104 is terminal information indicating a terminal name and a terminal position of the LSI.

In the internal data D11, D110 is noise index information having noise amount data for each instance or instance group. D111 is layout information having graphic information such as arrangement and wiring information and other information necessary for layout, and is used in the entire layout system.

In the layout system 1, a noise amount calculation unit 100 calculates an amount of noise generated by an instance or a block arranged on a layout by using an input pattern D100, a netlist D101 and a library D103 as input and calculates noise index information. It is a process. 1
Numeral 10 estimates the degree of noise reduction in the LSI area from the arrangement of the power supply terminals, using as input the netlist D101, the constraint condition D102, the library D103, the terminal information D104, and the noise index information D110 calculated in the noise amount calculation step 100. This is a floor plan creation process for arranging blocks and schematic arrangement of instances inside the blocks, and further performing power supply wiring, analog wiring, and the like. In the floor plan creation step 110, first, the terminal information D1
The terminal position information including the power supply terminal is determined by inputting the position information of the terminal from the power supply terminal 04, and the degree of noise reduction in the entire chip is determined from the determined position of the power supply terminal. Are arranged, and finally, the blocks and the instance groups having a large amount of noise are sequentially arranged in the arrangement region having a large degree of noise reduction. Reference numeral 120 denotes a wiring information extraction step, which calculates a detailed degree of noise reduction based on information on wiring lengths and wiring widths of power supplies and analogs wired from the floor plan creation step 110, and determines an instance arrangement position. This is the step of obtaining parameters for 13
Reference numeral 0 denotes a placement and routing step, which is a step of performing detailed placement and routing of instances based on the parameters obtained in the routing information extraction step 120. 140 is a noise constraint confirmation step,
This is a step of calculating the total amount of noise at the stage when the layout of the placement and routing is completed and confirming whether or not the constraint is satisfied. Thereby, by calculating the wiring impedance by using the value of the capacitor or the like inserted in the power supply wiring, which was not considered in the placement and wiring process 130,
It is possible to determine whether the constraint is satisfied by using the more accurate total noise amount.

Hereinafter, each step of the layout system 1 will be described in detail with reference to the drawings. First, the process of calculating the amount of noise will be described with reference to FIG. FIG. 2A is a table showing noise amount data of the instance output terminal.

Here, reference numeral 200 denotes an instance name of a cell used in the netlist D101, and reference numeral 201 denotes output terminals of all instances listed in the instance name 200. Reference numeral 202 denotes the number of times of switching for each output terminal of the instance obtained from the result of the logic simulation based on the logic information of the cells stored in the simulation input pattern D100, the netlist D101 and the library D103 necessary for the simulation. . Reference numeral 203 denotes a current capability obtained by calculating the amount of current for each output terminal of each instance from the output current capability of the cell stored in the library D103, and 204 denotes the number of switching times 202 and the current capability of each instance calculated from the current capability 203. Shows the amount of noise for each output terminal.

FIG. 2B is a table showing parameters used for calculating a noise amount for each output terminal. In the present embodiment, the noise amount 204 is obtained by multiplying the number of switching times 202 by the weight α and the current capacity 203 by the weight β.

FIG. 2C is a table showing the noise amount for each instance. The noise amount 2 for each instance output terminal is shown in FIG.
The amount of noise for each instance is calculated based on 04.

Here, reference numeral 220 denotes an instance name of a cell used in the netlist D101, and reference numeral 221 denotes a noise amount for each instance. In the present embodiment, in the instance I2 having two output terminals X and Y, the average value of the noise amount N2X of the output terminal X and the noise amount N2Y of the output terminal Y is NI2.

FIG. 2D is a table showing the amount of noise for each instance group. Reference numeral 230 denotes a group name of a group in which some instances are put together, and reference numeral 231 denotes a noise amount obtained by adding the noise amounts of the instances constituting each group. By calculating the noise amount for each group, it is possible to perform the arrangement in consideration of the noise amount even when arranging the grouped instances.

In the noise amount calculation step 100, the noise amount is obtained from the input pattern D100, so that a layout can be performed in consideration of the noise amount optimized in a specific operation situation.

Although the noise amount calculated in the noise amount calculation step 100 is calculated by simulation,
Using the number of switching times calculated in advance as input,
The noise amount may be calculated.

Further, a simulation pattern can be omitted by inputting the frequency of a limited specific signal such as a clock signal without calculating the number of times of switching by simulation based on the input pattern.

Further, by using only the current capability of the cell as a parameter for calculating the amount of noise, the amount of noise can be calculated in a short time without performing a simulation.

The process of dividing the entire chip according to the degree of noise reduction will be described below with reference to FIG. FIG.
(A) is a layout area division diagram according to the degree of noise reduction in the chip internal area by the power supply terminal VDD0. Here, since the degree of noise reduction depends on the distance from the power supply terminal due to the power supply decoupling effect, the inside of the chip is A00, depending on the distance from the power supply terminal VDD0.
The area is divided into four areas A01, A02, and A03 having different degrees of noise reduction.

FIG. 3B is a layout area division diagram according to the degree of noise reduction in the chip internal area by the power supply terminal VDD1. In the case of an LSI having multiple power supplies, blocks and instances are arranged using a plurality of arrangement area division diagrams as shown in FIGS. 3 (a) and 3 (b). For the blocks and instances connected to the power supply VDD0, the arrangement area division diagram of FIG. 3A is applied, and for the blocks and instances connected to the power supply VDD1, the arrangement area division diagram of FIG. 3B applies.

FIG. 3C is a layout area division diagram according to the degree of noise reduction in the chip internal area by the power supply VDD0 having a plurality of power supply terminals. Also in this case, the arrangement area is divided according to the distance from the power supply terminal VDD0.

A process of arranging a hard macro or an instance group by using an arrangement area division diagram will be described below with reference to FIG. FIG. 4A is a diagram showing arrangement area data of a hard macro. Reference numeral 400 denotes a hard macro name of a hard macro, 401 denotes a previously calculated noise amount unique to each hard macro, and 402 denotes an arrangement area determined according to the arrangement area division diagram of the hard macro name 401 in FIG. In the present embodiment, the hard macro name 402 automatically determines the arrangement area in ascending order of the noise amount 401.

It should be noted that the designer may specify the arrangement position of the hard macro, and in that case, the arrangement area where the hard macro is arranged is recorded in the arrangement area 402. FIG.
FIG. 7B is a diagram illustrating the arrangement area data of the grouped instances. Reference numeral 410 denotes a group name, 411 denotes a noise amount for each group, and 412 denotes an arrangement area. By using FIG. 4B, the arrangement position of the grouped instances can be determined in consideration of the noise amount, similarly to the arrangement of the hard macros.

After all the arrangements are completed, power supply wiring and analog wiring inside the chip are performed. In addition,
In the noise index information D110, similar processing is performed not only for the power supply but also for the analog terminal, so that noise interference with the analog signal can be reduced as in the case of the power supply signal.

The step of extracting wiring information will be described with reference to FIG. FIG. 5A is a conceptual diagram showing a configuration of a power supply terminal and a power supply wiring in an LSI. In FIG. 5A, reference numeral 50 denotes an LSI;
01 denotes a power supply terminal.

FIG. 5B is a layout diagram of the LSI, and shows a layout diagram of the LSI 50. In each of the divided arrangement regions, the degree of noise reduction is calculated based on the positions of the power supply wiring 500 and the power supply terminal 501 in FIG. The division of the arrangement area is not limited to the number of divisions shown in FIG. 5B, but the more finely divided the more the degree of noise reduction can be calculated.

FIG. 5C is a table showing the degree of noise reduction corresponding to the divided arrangement areas. 520 represents the divided area, and 521 represents the degree of noise reduction corresponding to the area.

FIG. 5D is a calculation formula for calculating the degree of noise reduction. Numeral 530 indicates the value of the noise reduction degree 521 using the wiring length from the power supply terminal. Here, the effect of reducing the noise in the area in proportion to the wiring length from the power supply terminal is increasing. In 531, the calculation is performed by multiplying the square of the wiring length multiplied by the weighting coefficient γ and the wiring width multiplied by the weighting coefficient θ. Here, the effect of reducing noise in the area in proportion to the wiring length and the wiring width from the power supply terminal is increasing. At 532, a correction term is added to 531. In the case of a wiring having a partially different wiring width in the middle of the wiring, the effect of decoupling can be expected, so that the noise reduction degree 521 is corrected by the number of places where the wiring width is different. . In 533, the degree 521 of noise reduction is obtained by using only the distance from the terminal regardless of the wiring. By diverting the arrangement area division diagram obtained in the floor plan creation step 110, the extraction of wiring information can be omitted, and the calculation time can be reduced.

The present invention can be applied to an LSI having a plurality of power supplies by creating a plurality of tables showing the degree of noise reduction corresponding to the divided arrangement areas in FIG. .

Next, the arrangement and wiring process will be described with reference to FIG. FIG. 6A is a table showing instance arrangement data. Reference numeral 600 denotes an instance name, and 601 denotes a noise amount.
This corresponds to 0 and the noise amount 221. Reference numeral 602 denotes a region where the instance is arranged. Reference numeral 603 indicates the degree of noise reduction in the arrangement area where the instances are arranged.

FIG. 6B is a flowchart of the processing for determining the arrangement area. First, the initial arrangement position of each instance is determined (S610). As the noise reduction degree 603, the noise reduction degree at the initial arrangement position is stored.
Next, the total noise amount of the entire LSI is calculated from the noise reduction degree 603 and the noise amount 601 at the initial arrangement position determined in S610 (S611). In the present embodiment, a value obtained by subtracting the noise reduction degree 603 from the noise amount 601 for each instance is defined by a function f, and the sum of the functions f of all instances is obtained. Thus, the total noise amount of the entire LSI is calculated in consideration of the degree of noise reduction. Next, it is determined whether the total noise amount satisfies the design constraint value (S612), and the constraint value input from the constraint condition (D102 in FIG. 1) is compared with the total noise amount calculated in S611. If the constraint is violated in S612, the arrangement position of the instance is changed so as to satisfy the constraint (S613). The changed arrangement position is reflected in the area 602, and the degree of noise reduction 603 is changed accordingly. After the instance arrangement data is updated, the process returns to step S611 again to calculate the total noise amount. If there is no constraint violation in S612, the arrangement position of the instance determined to satisfy the constraint condition is determined as the final arrangement position. As a result, a layout that satisfies the design constraint of the noise amount can be performed.
In addition, by setting the constraint value to 0, it is possible to perform an arrangement in which the total amount of noise is minimized.

FIG. 6C shows a flowchart for determining an arrangement area by another method. First, the table representing the instance arrangement data of FIG. 6C is rearranged in descending order of the noise amount (S620). Next, the table showing the degree of noise reduction corresponding to the divided arrangement areas in FIG. 5C is rearranged in descending order of the degree of noise reduction (S62).
1). Finally, based on the tables rearranged in S620 and S621, the instances are arranged in an area where the degree of noise reduction is large in order from the instance with the largest noise amount (S622). This makes it possible to realize a layout that takes noise reduction into account without performing complicated calculations.

Further, another method of arranging cells for reducing noise will be described. FIG. 6D shows two clock signals A,
FIG. 3 is a diagram showing a cell arrangement of an LSI operating in synchronization with B. Clock A and clock B are clocks that operate at different timings, such as a non-overlapping two-phase clock. Reference numeral 630 denotes a cell that operates in synchronization with the clock A, and reference numeral 631 denotes a cell that operates in synchronization with the clock B. Here, when one cell operates by arranging the cell 630 operating according to the clock A and the cell 631 operating according to the clock B side by side, the other cell functions as a capacitor. Thus, noise can be effectively reduced.

In determining the arrangement position of the instances in the actual layout, there are other restrictions such as timing, and the arrangement must be performed so as to satisfy the restrictions. With the above layout method, noise generated inside the LSI can be reduced, and malfunction of the LSI due to the noise can be prevented.

[0049]

As described above, according to the layout method of the present invention, it is possible to perform an automatic layout in consideration of noise by obtaining the amount of noise and the degree of noise reduction.
By reducing the noise generated inside the LSI,
Malfunction of the LSI due to noise can be prevented.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a layout system.

2A is a table showing noise amount data of an instance output terminal; FIG. 2B is a table showing parameters used for calculating a noise amount for each output terminal; FIG. 2C is a table showing a noise amount for each cell; Table showing the amount of noise for each

FIG. 3A is a layout area division diagram according to the degree of noise reduction in the chip internal area by the power supply terminal VDD0. FIG. 3B is a layout area division view according to the noise reduction degree in the chip internal area by the power supply terminal VDD1. FIG. 4 is a layout area division diagram according to the degree of noise reduction in the chip internal area by the power supply VDD0 having a plurality of power supply terminals.

FIG. 4A is a diagram showing arrangement region data of a hard macro; FIG. 4B is a diagram showing arrangement region data of grouped cells;

5A is a conceptual diagram showing the configuration of a power supply terminal and a power supply wiring in an LSI. FIG. 5B is a diagram showing a layout of an LSI. FIG. ) Formula for calculating the degree of noise reduction

6A is a table showing instance arrangement data. FIG. 6B is a flowchart for determining an arrangement area. FIG. 6C is a flowchart for determining an arrangement area. FIG. 6D is an L that operates in synchronization with two clock signals A and B.
Diagram showing cell layout of SI

[Explanation of symbols]

 Reference Signs List 1 layout system 100 noise amount calculation step 110 floor plan creation step 120 wiring information extraction step 130 placement and wiring step 140 noise constraint confirmation step D10 input data D100 input pattern D101 netlist D102 constraint condition D103 library D104 terminal information D11 internal data D110 noise index Information D111 Layout information 200 Instance name 201 Output terminal 202 Switching frequency 203 Current capability 204 Noise amount 210 Switching frequency 211 Current capability 220 Instance name 221 Noise amount 230 Group name 231 Noise amount 400 Hard macro name 401 Noise amount 402 Placement area 410 Group name 411 Noise amount 412 Placement area 50 LSI 500 Power supply wiring 501 Power supply terminal 520 Band 521 noise reduction degree 530 noise reduction degree calculation formula 531 noise reduction degree calculation formula 532 degree equation 600 instance name 601 noise amount 602 region 63 LSI 630 cells 631 cells degree equation 533 the noise reduction of the noise reduction

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Takashi Yoneda 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture F-term in Matsushita Electric Industrial Co., Ltd. 5B046 AA08 BA04 JA01 5F064 BB21 DD02 DD03 DD05 DD25 EE02 EE08 EE09 EE43 EE45 EE52 EE54 HH06 HH09 HH12

Claims (16)

[Claims] A step of obtaining noise amount data for each specific circuit to be laid out by calculating a noise amount when performing automatic layout in consideration of the influence of noise; and dividing the semiconductor integrated circuit device into a plurality of arrangement regions. Determining the degree of noise reduction in each of the arrangement regions; determining the divided arrangement regions in which the circuits are arranged according to the noise amount data; and determining the circuit in the determined arrangement regions. And a step of arranging the respective circuits by wiring and a step of confirming that the noise constraint condition is satisfied. 2. The layout method according to claim 1, wherein the amount of noise is calculated from the current capability of the cell. 3. The layout method according to claim 2, wherein the amount of noise is calculated based on the number of switching times of each circuit obtained by simulation. 4. The layout method according to claim 2, wherein the amount of noise is calculated based on a switching frequency of each circuit obtained in advance. 5. The layout method according to claim 2, wherein the amount of noise is calculated based on the frequency of a signal input to each circuit. 6. The layout method according to claim 1, wherein a noise amount is calculated for each group constituted by a plurality of instances as a specific circuit. 7. The layout method according to claim 1, wherein a noise amount is calculated for each block as a specific circuit. 8. The method according to claim 1, wherein a degree of noise reduction in each arrangement region is calculated from the terminal position information.
The layout method described. 9. The layout method according to claim 8, wherein a power supply terminal is used as said terminal. 10. The layout method according to claim 8, wherein an analog terminal is used as said terminal. 11. The power supply wiring according to claim 1, wherein the degree of noise reduction is calculated.
The layout method described. 12. The layout method according to claim 1, wherein a wiring length and a wiring width of a power supply wiring are used in calculating the degree of noise reduction. 13. The layout method according to claim 1, wherein the degree of noise reduction is calculated by using a wiring length of the power supply wiring, a wiring width, and the number of wiring regions having different wiring widths. 14. The layout method according to claim 1, wherein the circuits having a large amount of noise are preferentially arranged in an area having a large degree of noise reduction. 15. The layout method according to claim 1, wherein the total noise calculated from the noise amount and the degree of noise reduction is compared with a constraint to confirm that the noise constraint is satisfied. 16. A layout method in a semiconductor integrated circuit device having a plurality of clock systems, wherein circuits operating with different clock signals are arranged adjacent to each other when performing automatic layout in consideration of the influence of noise. .