JPH09319775A - Design method and system for semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the delay time without increasing the area of an IC (integrated circuit) and also to shorten the design time of the IC by correcting only the wiring path having the delay time that does not satisfy a standard. SOLUTION: This method/device consists of a storage 101, a controller 102, an input device 103 and a display device 104. The storage 101 stores the processing procedure of the controller 102 and a data base necessary for the wiring placement design of an IC. Then the controller 102 operates based on the processing procedure stored in the storage 101 to generate the display contents of the device 104 and also generate the placement wiring data based on the contents inputted to the device 103 by an IC designer. At the same time, the controller 102 confirms whether the delay time of every wiring path is smaller than the prescribed value set previously and then shows the result of this confirmation on the device 104 after a placement wiring is designed. When a correction mode is inputted to the device 103, the delay time is shortened (corrected) for only the wiring path having the delay time that exceeds the prescribed value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for designing a semiconductor integrated circuit including placement and wiring, and more particularly to a method and an apparatus for designing a semiconductor integrated circuit in consideration of delay time.

[0002]

2. Description of the Related Art A semiconductor integrated circuit (hereinafter, IC: Integrat
ed circuit), especially LSI (Large Scale In)
These integrated circuits are required to be downsized in order to realize a large capacity, and high-speed operation is required because the software using a large-capacity IC becomes large in capacity. The demand for miniaturization and high-speed operability is increasing year by year, and it is the most important factor in IC design.

The operating frequency of the designed IC is determined by the long delay time of each wiring path. For example, the delay time of all wiring paths is 10 ns
If it is within ec, the manufactured IC is 100MHz
However, if even one of the wiring paths has a delay time of 20 nsec, the operating frequency of the entire IC will be 50 MHz.

Currently, when designing an IC, CAD (Computer-Aided Design) is often used to shorten the design time. A cell-based method is generally used as a CAD-based design method. A plurality of cells are arranged in accordance with their respective functions, and thereafter, a wiring route connecting the cells is determined.

In the design by CAD, in the arrangement of a plurality of cells and the determination of the wiring route, the miniaturization of the IC and the guarantee of the operation speed are prioritized for the above-mentioned reasons.
It is determined that the chip area is minimized, the wiring length is minimized, and the delay time of each wiring path is shortened.

After that, the delay time of each wiring path is obtained, and it is confirmed whether the delay time is within the required delay time. If there is a wiring path that exceeds the required delay time, the placement and routing is performed again. Done.

As a conventional technique for designing in consideration of the delay time of the above wiring path, there is one disclosed in Japanese Patent Laid-Open No. 7-14927.

The object disclosed in the above publication is to adjust the delay time by using a plurality of delay cells having different delay times for the purpose of reducing the design time. Specifically, the layout of each cell is determined, the wiring route is determined, and then the delay time of a predetermined signal route is calculated to determine whether the delay time satisfies the required uniformity. As a result of this judgment, when the delay time of a predetermined signal path does not satisfy the required uniformity, a delay cell is inserted, replaced or deleted so that the signals on the predetermined signal path arrive at the same time. Is.

[0009]

In the conventional CAD design, if there is a wiring path that exceeds the required delay time among the delay times of the respective wiring paths, the placement and routing is performed again. There was a problem that it took time.

The method disclosed in Japanese Patent Application Laid-Open No. 7-14927 corrects only the wiring path exceeding the required delay time, and the modification to be performed has a different delay time for the purpose of delaying. Insert multiple delay cells,
By exchanging or deleting, the signals in a predetermined signal path are made simultaneous. Therefore, the correction direction is to enlarge the area of the IC and lengthen the delay time. Therefore, the manufactured IC cannot be downsized, and the delay time of the wiring path cannot be reduced. There is a problem.

Further, it is possible to correct the one having a short delay time, but the correction cannot be made when the delay time is long, and the layout and wiring are required again and the design time becomes long. There is.

The present invention has been made in view of the problems of the above-mentioned conventional techniques, and it is possible to shorten the delay time and the design time without increasing the area of the IC. It is an object of the present invention to realize a semiconductor integrated circuit designing method and device that can be realized.

[0013]

A semiconductor device designing method of the present invention is a semiconductor integrated circuit designing method for designing the layout and wiring of transistors constituting a semiconductor integrated circuit based on a netlist. After that, it is confirmed that the delay time of each wiring path is within a predetermined value set in advance, and correction is performed to reduce the delay time only for the wiring path having a delay time exceeding the predetermined value.

In this case, the delay time of the wiring path may be shortened by replacing the transistor in the wiring path with a transistor having a short delay time.

Further, the delay time of the wiring path may be shortened by thickening the metal layer of the wiring in the wiring path.

The delay time of the wiring path may be shortened by increasing the thickness of the interlayer film of the wiring in the wiring path.

In a method of manufacturing a semiconductor device according to another aspect of the present invention, the layout and wiring are designed in the method of designing the layout and wiring of the MOS transistors forming the semiconductor integrated circuit based on the netlist. After that, it is confirmed whether or not the delay time of each wiring route is within a predetermined value set in advance, and delaying is performed by changing the threshold voltage of the transistor in the wiring route only for the wiring route having the delay time exceeding the predetermined value. It is characterized by making corrections that shorten the time.

In this case, only for the wiring path having a delay time exceeding a predetermined value, the delay time is shortened by changing the threshold voltage of the transistor in the wiring path. It is also possible to make a correction to reduce the current consumption by changing the threshold voltage of the transistor in the wiring path only for the wiring path having the current consumption exceeding the second predetermined value as compared with the second predetermined value.

The semiconductor device manufacturing method according to the present invention includes a storage device, a display device, an input device, a netlist content input to the input device, a program stored in the storage device, and data to be stored. Works based on
In a semiconductor integrated circuit design device comprising a control device for designing output of display contents to the display device and layout and wiring of transistors constituting a semiconductor integrated circuit, the control device designs each wiring and Confirm that the delay time is within a predetermined value set in advance, display it on the display device, and then input an input to the input device to make a correction, the delay time exceeding the predetermined value It is characterized in that the correction is performed to shorten the delay time only for the wiring route of.

In this case, the control device may shorten the delay time of the wiring path by replacing the transistor in the wiring path with a transistor having a short delay time.

Further, the control device may reduce the delay time of the wiring path by thickening the metal layer of the wiring in the wiring path.

Further, the control device may reduce the delay time of the wiring path by increasing the thickness of the interlayer film of the wiring in the wiring path.

Further, when the transistor forming the semiconductor integrated circuit is a MOS transistor, the control device changes the threshold voltage of the transistor in the wiring path only for the wiring path having a delay time exceeding a predetermined value. Modifications may be made to reduce the delay time.

In this case, the control device corrects only the wiring path having the delay time exceeding the predetermined value by changing the threshold voltage of the transistor in the wiring path to shorten the delay time, and then, in each wiring path. The current consumption is compared with the second predetermined value and displayed on the display device.
When an input for making a correction is made to the input device, the current consumption is reduced by changing the threshold voltage of the transistor in the wiring path only for the wiring path having the current consumption exceeding the second predetermined value. May be performed.

[Operation] In the present invention configured as described above, when there is a wiring path with a delay time that does not meet the standard, the layout and wiring design is not performed again as in the conventional case, and the standard is not met. Since only the wiring route of the delay time is corrected, the redesign time is shortened.

As a method for shortening the delay time, the transistors used are replaced, the metal layer of the wiring is thickened, the interlayer film of the wiring is thickened, and when the MOS transistor is used, the threshold voltage Since the layout such as change is not changed, the area will not be increased.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the construction of an embodiment of an IC designing apparatus according to the present invention, FIG. 2 is a flow chart showing its operation, and FIGS. 3 to 8 are for explaining the operation in this embodiment. FIG.

In this embodiment, an I-type MOS transistor is used.
This is for designing C, and includes a storage device 101, a control device 102, an input device 103, and a display device 104. The storage device 101 is a control device 102.
It stores a database necessary for the processing procedure and the wiring layout design of the IC. The control device 102 is the storage device 101.
The display contents of the display device 104 are generated, and the layout and wiring data is generated according to the contents input to the input device 103 by the IC designer. In the case of this embodiment, as described above, the MOS
Since the IC design is performed by the transistor of the type, the program and the database read from the storage device 101 are suitable for it, and the flow chart shown in FIG. 2 follows it.

The operation of this embodiment will be described with reference to the flowchart of FIG. FIG. 2 shows the control operation of the control device 102 in this embodiment.

At the start of the operation, the IC designer inputs the netlist which is the connection information of the circuit having the desired function into the input device 10.
Enter 3 The control device 102 accepts the input (step S201), arranges cells based on the accepted netlist, and designs wiring for connecting the cells (step S202).

Next, the operation timing of each part of the circuit by the designed layout and wiring is verified (step S203), and then it is checked whether the circuit operates normally at the verified operation timing (step S204).

As a result of the check in step S204, if it is confirmed that the circuit does not operate normally, the process returns to step S202 to perform the placement and routing again. If it is confirmed that the circuit operates normally, the delay times of all the created wiring routes are calculated (step S205), and it is confirmed whether the delay time of each wiring route is within the standard (step S206). ).

The operation of confirming the delay time of the above wiring path will be described with reference to FIG.

FIG. 3 is a block diagram showing a schematic structure of the inside of the IC to be manufactured. A combination circuit 302 including a plurality of transistors is provided between a plurality of input side flip-flop circuits 301 and output side flip-flop circuits 303 used as signal holding means, and the input side flip-flop circuit 301 and the output side flip-flop circuit are provided. Three
The signal passing through 03 is switched by the plurality of transistors that form the combinational circuit 302. The wiring paths that are paths that connect the input-side flip-flop circuit 301 and the output-side flip-flop circuit 303 are different from each other, and the delay time of each wiring path is not fixed. In FIG. 3, the delay times t ₁ are different from each other.
Three types of wiring paths, which are up to t ₃ , are shown.

In the IC design, in order to operate the manufactured IC at the time t ₀ which is the clock rate, all the delay times t _{1 to} t ₃ of each wiring path are within the time t ₀ which is the clock rate. Must be present, step S
At 206, it is confirmed whether the delay time of each wiring path is within a predetermined clock rate. In addition, it may be described in the netlist that the delay times of the predetermined wiring paths are made constant, and in this case, it is a condition that the arrival times are the same within the time t ₀ .

When it is confirmed in step S206 that the delay time of each wiring route is within the standard, it is confirmed whether the manufactured IC satisfies the electrical characteristics shown in the netlist. After (step S211),
The designed layout and wiring data is output (step S21).
3). After that, a mask pattern for making a circuit based on the layout and wiring data is produced (step S21).
4) Finish.

If it is confirmed in step S206 that there is a wiring route whose delay time is out of the standard, the display device 104 is caused to perform a display for confirming to the IC designer whether or not the layout and wiring should be performed again. It prompts the IC designer to input an instruction (step S207). The operation when it is confirmed that the IC manufactured in step S211 does not satisfy the electrical characteristics shown in the netlist will be described later.

When the IC designer inputs in step S207 that the placement and routing are to be performed again, step S207 is performed.
Returning to 202, the above operation is repeated. Further, when the input indicating that the placement and wiring is not performed is made, all the wiring paths whose delay time is out of the standard are extracted (step S208), and the threshold voltage of the transistor in the extracted wiring path is changed (step S209). ).

Steps S208 and S described above
The operation performed in 209 will be described with reference to FIGS. 4 to 6.

FIG. 4 and FIG. 5 are views showing an example of delay time distribution of a wiring path designed by automatic placement and wiring, and FIG. 6 shows the delay time by lowering the threshold voltage of the MOS type transistor. It is a figure which shows a mode that it is shortened.

In this embodiment, the delay time in FIG. 4 is time t _0.
The wiring path exceeding the above is extracted and is corrected so that the delay time is within the time t _{0 as} shown in FIG.

This embodiment uses a MOS transistor, and as a method for shortening the delay time, lowering the threshold voltage of the transistor is used. In the MOS type transistor shown in FIG.
The delay time is shortened by about 6% each time [V] is lowered.
Generally, the delay time is shortened by 5% to 8% each time the voltage is lowered by 0.1 [V].

In step S209, the above phenomenon is used.
Then, the delay time of each wiring route is time t ₀Each to be within
The threshold voltage of the transistor on the wiring path is lowered. After this,
Simulates the circuit operation of a transistor whose threshold voltage is changed
(Step S210), and based on the simulation result.
The ICs manufactured by
It is confirmed whether the characteristics are satisfied (step S21).
1).

Although there are various electric characteristics confirmed in step S211, in this embodiment, the delay time is shortened by lowering the threshold voltage of the transistor as described above, Checking the current consumption is especially important. This is because in the case of a MOS transistor, the leak current increases as the threshold value is lowered, and the current consumption increases.

FIG. 7 is a diagram showing how leakage current increases when the threshold value of the MOS type transistor is lowered. As shown in the figure, the threshold voltage is changed from 0.2 [V] to 0.1.
When it is set to [V], it increases by about 1 μA and the threshold voltage becomes 0.1
If it is less than or equal to [V], it increases exponentially.

When it is confirmed that the IC manufactured in step S211 satisfies the electrical characteristics, the designed placement and routing data is output (step S21).
3) Then, a mask pattern for actualizing the circuit based on the layout and wiring data is produced (step S214), and the process is ended. If it is confirmed that the electrical characteristics are not satisfied, the display device 104 is caused to perform a display for confirming to the IC designer whether to change the design of the transistor or redesign the layout and wiring. The IC designer is prompted to input an instruction (step S212). As a result, if the IC designer inputs an instruction to perform layout and wiring again, the process returns to step S202, and if an instruction input to perform the transistor design again is made, the process returns to step S208 to return to each of the above. Repeat the operation.

The layout and wiring and the transistor redesign performed as a result of the confirmation in steps S204 and S212 are performed based on the result once created.

The same applies when the transistor is redesigned. When the transistor is redesigned, at least the delay time characteristic has been cleared, so step S20
Extraction of non-standard wiring route performed in step 8 and step S
The change of the threshold voltage of the transistor performed at 209 is
It will be conducted from a different perspective from the last time based on the cause of the non-standard. For example, in the case where the current consumption is out of the standard as described above, a wiring path with a large current consumption is extracted in step S208, and the threshold voltage of the transistor is increased in step S209.

In the embodiment described above, M
This is a case where the OS type transistor is used, and the threshold voltage is lowered in order to shorten the delay time of the wiring path, but in addition to this, in addition to this, (1) the delay time is short. Replace with a transistor. (2) The capacitance and resistance of the wiring itself are reduced. Therefore, the correction operation performed in step S209 may be configured as described above.

The signal delay time depends on the wiring resistance R and capacitance C,
It depends on the impedance of the driving source and the load impedance. To reduce the wiring delay time, the time constant R
It suffices to reduce C. The following method can be considered in order to shorten the wiring delay time without changing the layout and wiring, that is, to reduce the time constant RC.

The resistance R is reduced by increasing the thickness of the metal layer of the wiring.

The capacitance C is reduced by thickening the interlayer film of the wiring.

When either of the above methods (1) and (2) is used, the transistor used is not limited to the MOS type. Also, each of these methods may be used in combination. However, since it is the easiest to change the threshold voltage shown in this embodiment in a later manufacturing process, first, the threshold voltage is changed,
If the standard is still not satisfied, it is desirable to use either or both of the methods (1) and (2).

In the present embodiment configured as described above, when the correction is made in step S209, the layout and wiring data created will contain information indicating that the threshold voltage of the transistor is changed. . In addition, the above (1),
When any one of the methods (2) is used, the information on the changed transistor or the information to thicken the wiring metal layer or the interlayer film is included.

The threshold voltage of the MOS transistor is determined by the amount of ions implanted in the gate. In the case of manufacturing an IC in which transistors having different threshold voltages are mixed, a plurality of mask patterns are manufactured in order to manufacture transistors having different threshold voltages in step S214.

FIG. 8 is a diagram for explaining a state in which a plurality of mask patterns are produced in step S214. The mask pattern 801 shown in FIG.
The correction operation is not performed at 09, and the amount of ions irradiated to the gate of the transistor is equal.
Although 12 holes are formed in the mask pattern 801 shown in FIG. 8A, if it is necessary to make different threshold values for predetermined 3 transistors of these holes,
Two mask patterns 802 and 803 shown in FIGS. 8B and 8C, respectively, are formed and used for ion irradiation at different times.

The division of the mask pattern, which is usually one as described above, into a plurality of patterns is also performed when the wiring metal layer or the interlayer film is thickened.

In this embodiment, as described above, the delay time of the predetermined wiring path can be shortened, and this shortening work can partially correct the predetermined wiring path. In addition, it is possible to shorten the time required for the layout and wiring design, and I
The C design time could be shortened.

[0060]

As described above, according to the present invention, since only the wiring path having the delay time which does not meet the standard is corrected,
The delay time can be shortened without increasing the area of C, which has the effect of shortening the design time. Further, since the cell base is partially modified, the cell base is rarely changed, and the critical path can be protected as much as possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of an IC design apparatus according to the present invention.

FIG. 2 is a flowchart showing the operation of the embodiment shown in FIG.

FIG. 3 is a block diagram showing a schematic configuration inside an IC to be manufactured.

FIG. 4 is a diagram showing an example of a delay time distribution of a wiring path.

FIG. 5 is a diagram showing an example of a delay time distribution of a wiring path.

FIG. 6 is a diagram showing how the delay time is shortened by lowering the threshold voltage of a MOS transistor.

FIG. 7 is a diagram showing how leakage current increases when the threshold value of a MOS transistor is lowered.

FIG. 8 is a diagram for explaining a state of forming a plurality of mask patterns in step S214 in FIG.

[Explanation of symbols]

 101 storage device 102 control device 103 input device 104 display device 301 input side flip-flop circuit 302 combination circuit 303 output side flip-flop circuit 801 to 803 mask pattern S201 to S214 steps

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] June 18, 1996

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Full text

[Correction method] Change

[Correction contents]

[Document Name] Statement

Title: Method and apparatus for designing semiconductor integrated circuit

[Claims]

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for designing a semiconductor integrated circuit including placement and wiring, and more particularly to a method and an apparatus for designing a semiconductor integrated circuit in consideration of delay time.

[0002]

2. Description of the Related Art A semiconductor integrated circuit (hereinafter, IC: Integrat
ed circuit), especially LSI (Large Scale In)
Since the tegrated circuit), downsizing is required to realize a large scale, also the high speed is required for the operation because the large-scale software also used large-scale has been IC, these The demand for miniaturization and high-speed operability is increasing year by year, and it is the most important factor in IC design.

The operating frequency of the designed IC is determined by the long delay time of each wiring path. For example, the delay time of all wiring paths is 10 ns
If it is within ec, the manufactured IC is 100MHz
However, if even one of the wiring paths has a delay time of 20 nsec, the operating frequency of the entire IC will be 50 MHz.

Currently, when designing an IC, CAD (Computer-Aided Design) is often used to shorten the design time. A cell-based method is generally used as a CAD-based design method. A plurality of cells are arranged in accordance with their respective functions, and thereafter, a wiring route connecting the cells is determined.

In the design by CAD, in the arrangement of a plurality of cells and the determination of the wiring route, the miniaturization of the IC and the guarantee of the operation speed are prioritized for the above-mentioned reasons.
It is determined that the chip area is minimized, the wiring length is minimized, and the delay time of each wiring path is shortened.

After that, the delay time of each wiring path is obtained, and it is confirmed whether the delay time is within the required delay time. If there is a wiring path that exceeds the required delay time, the placement and routing is performed again. Done.

As a conventional technique for designing in consideration of the delay time of the above wiring path, there is one disclosed in Japanese Patent Laid-Open No. 7-14927.

What is disclosed in the above publication is the design cost.
In order to reduce the delay time, the delay time is adjusted by using a plurality of delay cells having different delay times. Specifically, the layout of each cell is determined, the wiring route is determined, and then the delay time of a predetermined signal route is calculated to determine whether the delay time satisfies the required uniformity. As a result of this judgment, when the delay time of a predetermined signal path does not satisfy the required uniformity, a delay cell is inserted, replaced or deleted so that the signals on the predetermined signal path arrive at the same time. Is.

[0009]

In the conventional CAD design, if there is a wiring path that exceeds the required delay time among the delay times of the respective wiring paths, the placement and routing is performed again. There was a problem that it took time.

The method disclosed in Japanese Patent Application Laid-Open No. 7-14927 corrects only the wiring path exceeding the required delay time, and the modification to be performed has a different delay time for the purpose of delaying. Insert multiple delay cells,
By exchanging or deleting, the signals in a predetermined signal path are made simultaneous. Therefore, the correction direction is to enlarge the area of the IC and lengthen the delay time. Therefore, the manufactured IC cannot be downsized, and the delay time of the wiring path cannot be reduced. There is a problem.

Further, it is possible to correct the one having a short delay time, but the correction cannot be made when the delay time is long, and the layout and wiring are required again and the design time becomes long. There is.

The present invention has been made in view of the problems of the above-mentioned conventional techniques, and it is possible to shorten the delay time and the design time without increasing the area of the IC. It is an object of the present invention to realize a semiconductor integrated circuit designing method and device that can be realized.

[0013]

A semiconductor device designing method of the present invention is a semiconductor integrated circuit designing method having a plurality of wiring paths having one or more transistors in the middle thereof.
After designing the circuit using transistors with a threshold value or more, calculate the delay time of each wiring path and correct the wiring path exceeding the specified delay time so that the threshold value of the transistor in it is lowered And

In this case, with respect to the wiring path exceeding the predetermined delay time, after correcting the delay time by lowering the threshold value of the transistor in the wiring path, the current consumption in each wiring path is calculated and predetermined. It is also possible to correct the wiring path that exceeds the current consumption of the above so as to increase the threshold value of the transistor therein.

A semiconductor integrated circuit designing apparatus according to the present invention is based on a storage device, a display device, an input device, contents of the input netlist, a program stored in the storage device, and data to be stored. In a semiconductor integrated circuit design device comprising a control device that operates and outputs display contents to the display device and layout and wiring of transistors constituting the semiconductor integrated circuit,

After designing the layout and wiring, the control device
After confirming whether the delay time of each wiring path is within a predetermined value set in advance, the display is displayed on the display device, and thereafter, when an input for making a correction is made to the input device, the predetermined value is set. It is characterized in that correction is performed to reduce the delay time by lowering the threshold value of the transistor for the wiring path having the delay time exceeding.

In this case, the control device calculates the current consumption of each wiring after correcting the wiring path having a delay time exceeding a predetermined value by reducing the threshold voltage of the transistor in the wiring path to shorten the delay time. However, a wiring path that exceeds a predetermined value of current consumption may be corrected by increasing the threshold voltage of a transistor in the wiring path to reduce the current consumption.

[Operation] In the present invention configured as described above, if there is a wiring path with a delay time that does not meet the standard, the layout and wiring design is not performed again as in the conventional case, and the standard is not met. Since only the wiring route of the delay time is corrected, the redesign time is shortened.

As a method for reducing the delay time, only changing the threshold voltage of the MOS transistor is necessary.
In, it does not change the arrangement never area increases.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the construction of an embodiment of an IC designing apparatus according to the present invention, FIG. 2 is a flow chart showing its operation, and FIGS. 3 to 8 are for explaining the operation in this embodiment. FIG.

In this embodiment, an I-type MOS transistor is used.
This is for designing C, and includes a storage device 101, a control device 102, an input device 103, and a display device 104. The storage device 101 is a control device 102.
It stores a database necessary for the processing procedure and the wiring layout design of the IC. The control device 102 is the storage device 101.
It operates according to the processing procedure stored in, and generates the display contents of the display device 104 and also generates the placement and routing data according to the input contents to the input device 103 by the IC designer. In the case of this embodiment, as described above, the MOS
Since it is an IC design using a transistor of the type, the program and database read from the storage device 101 are suitable for it, and the flowchart shown in FIG. 2 follows it.

The operation of this embodiment will be described with reference to the flowchart of FIG. FIG. 2 shows the control operation of the control device 102 in this embodiment.

The IC designer inputs the netlist which is the connection information of the circuit having the desired function at the start of the operation of the input device 10.
Enter 3 At that time, a MOS type transistor with a high threshold voltage
Register the data of DIST. The control device 102 accepts the input (step S201), arranges cells based on the accepted netlist, and designs wiring for connecting the cells (step S202).

Next, the operation timing of each part of the circuit by the designed layout and wiring is verified (step S203), and then it is checked whether the circuit operates normally at the verified operation timing (step S204).

When it is confirmed as a result of the check in step S204 that the circuit does not operate normally, the process returns to step S202 and the placement and wiring is performed again. If it is confirmed that the circuit operates normally, the delay times of all the created wiring routes are calculated (step S205), and it is confirmed whether the delay time of each wiring route is within the standard (step S206). ).

The operation of confirming the delay time of the above wiring path will be described with reference to FIG.

FIG. 3 is a block diagram showing a schematic structure of the inside of the manufactured IC. A combination circuit 302 including a plurality of transistors is provided between a plurality of input side flip-flop circuits 301 and output side flip-flop circuits 303 used as signal holding means, and the input side flip-flop circuit 301 and the output side flip-flop circuit are provided. Three
The signal passing through 03 is switched by the plurality of transistors that form the combinational circuit 302. The wiring paths that are paths that connect the input-side flip-flop circuit 301 and the output-side flip-flop circuit 303 are different from each other, and the delay time of each wiring path is not fixed. In FIG. 3, the delay times t ₁ are different from each other.
Three types of wiring paths, which are up to t ₃ , are shown.

In the IC design, in order to operate the manufactured IC at the time t ₀ which is the clock rate, all the delay times t _{1 to} t ₃ of each wiring path are within the time t ₀ which is the clock rate. Must be present, step S
At 206, it is confirmed whether the delay time of each wiring path is within a predetermined clock rate. In addition, it may be described in the netlist that the delay times of the predetermined wiring paths are made constant, and in this case, it is a condition that the arrival times are the same within the time t ₀ .

When it is confirmed in step S206 that the delay time of each wiring route is within the standard, it is confirmed whether the manufactured IC satisfies the electrical characteristics shown in the netlist. After (step S211),
The designed layout and wiring data is output (step S21).
3). After that, a mask pattern for making a circuit based on the layout and wiring data is produced (step S21).
4) Finish. The IC manufactured in step S211
Do not satisfy the electrical characteristics shown in the netlist
The operation in the case of is confirmed will be described later.

When it is confirmed in step S206 that there is a wiring route with a delay time out of the standard, the display device 104 is caused to display a message for confirming to the IC designer whether or not the layout and wiring should be performed again. It prompts the IC designer to input an instruction (step S207).

When the IC designer inputs in step S207 that the placement and routing are to be performed again, step S207
Returning to 202, the above operation is repeated. Further, when the input indicating that the placement and wiring is not performed is made, all the wiring paths whose delay time is out of the standard are extracted (step S208), and the threshold voltage of the transistor in the extracted wiring path is changed (step S209). ).

Steps S208 and S above
The operation performed in 209 will be described with reference to FIGS. 4 to 6.

FIG. 4 and FIG. 5 are diagrams showing an example of delay time distribution of a wiring route designed by automatic placement and wiring, and FIG. 6 shows the delay time by lowering the threshold voltage of the MOS type transistor. It is a figure which shows a mode that it is shortened.

In this embodiment, the delay time in FIG. 4 is time t _0.
The wiring path exceeding the above is extracted and is corrected so that the delay time is within the time t _{0 as} shown in FIG.

This embodiment uses a MOS transistor, and as a method for shortening the delay time, lowering the threshold voltage of the transistor is used. In the MOS type transistor shown in FIG.
The delay time is shortened by about 6% each time [V] is lowered.
Generally, the delay time is shortened by 5% to 8% each time the voltage is lowered by 0.1 [V].

In step S209, the above phenomenon is used.
Then, the delay time of each wiring route is time t ₀Each to be within
The threshold voltage of the transistor on the wiring path is lowered. After this,
Simulates the circuit operation of a transistor whose threshold voltage is changed
(Step S210), and based on the simulation result.
The ICs manufactured by
It is confirmed whether the characteristics are satisfied (step S21).
1).

Although there are various electric characteristics confirmed in step S211, in this embodiment, the delay time is shortened by lowering the threshold voltage of the transistor as described above, Checking the current consumption is especially important. This is because in the case of a MOS transistor, the leak current increases as the threshold value is lowered, and the current consumption increases.

FIG. 7 is a diagram showing how the leak current increases when the threshold value of the MOS transistor is lowered. As shown in the figure, the threshold voltage is changed from 0.2 [V] to 0.1.
When it is set to [V], it increases by about 1 μA and the threshold voltage becomes 0.1
If it is less than or equal to [V], it increases exponentially.

When it is confirmed that the IC manufactured in step S211 satisfies the electrical characteristics, the designed placement and routing data is output (step S21).
3) Then, a mask pattern for laying out a circuit based on the layout and wiring data is produced (step S214), and the process ends. When it is confirmed that the IC manufactured in step S211 does not satisfy the electrical characteristics, the IC designer is asked whether to change the design of the transistor or redesign the layout and wiring. The display is displayed on the display device 104, and the IC designer is prompted to input an instruction (step S212). As a result, if the IC designer inputs an instruction to perform the placement and routing again, step S20.
Returning to step 2, when an instruction input to redesign the transistor is made, the process returns to step S208 and the above-described operations are repeated.

The layout and wiring and the transistor redesign performed as a result of the confirmation in steps S204 and S212 are performed based on the result once created.

The same applies when the transistor is redesigned. When the transistor is redesigned, at least the delay time characteristic has been cleared, so step S20
Extraction of non-standard wiring route performed in step 8 and step S
The change of the threshold voltage of the transistor performed at 209 is
It will be conducted from a different perspective from the last time based on the cause of the non-standard. For example, in the case where the current consumption is out of the standard from the viewpoint of the current consumption as described above, the wiring path having the large current consumption is extracted in step S208, and the threshold voltage of the transistor is increased in step S209.

In the present embodiment configured as described above, when the correction is made in step S209, the layout and wiring data created will contain information indicating that the threshold voltage of the transistor is changed. .

The threshold voltage of the MOS transistor is determined by the amount of ions implanted in the gate. In the case of manufacturing an IC in which transistors having different threshold voltages are mixed, a plurality of mask patterns are manufactured in order to manufacture transistors having different threshold voltages in step S214.

FIG. 8 is a diagram for explaining a state in which a plurality of mask patterns are produced in step S214. The mask pattern 801 shown in FIG.
The correction operation is not performed at 09, and the amount of ions irradiated to the gate of the transistor is equal.
Although 12 holes are formed in the mask pattern 801 shown in FIG. 8A, if it is necessary to make different threshold values for predetermined 3 transistors of these holes,
Two mask patterns 802 and 803 shown in FIGS. 8B and 8C, respectively, are formed and used for ion irradiation at different times.

In this embodiment, the delay time of the predetermined wiring route can be shortened as described above, and this shortening work can partially correct the predetermined wiring route. In addition, it is possible to shorten the time required for the layout and wiring design, and I
The C design time could be shortened.

[0047]

As described above, according to the present invention, since only the wiring path having the delay time which does not meet the standard is corrected,
The delay time can be shortened without increasing the area of C, which has the effect of shortening the design time. Further, since the cell base is changed and a partial correction is performed, it is possible to protect the critical path as much as possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of an IC design apparatus according to the present invention.

FIG. 2 is a flowchart showing the operation of the embodiment shown in FIG.

FIG. 3 is a block diagram showing a schematic configuration inside an IC to be manufactured.

FIG. 4 is a diagram showing an example of a delay time distribution of a wiring path.

FIG. 5 is a diagram showing an example of a delay time distribution of a wiring path.

FIG. 6 is a diagram showing how the delay time is shortened by lowering the threshold voltage of a MOS transistor.

FIG. 7 is a diagram showing how leakage current increases when the threshold value of a MOS transistor is lowered.

FIG. 8 is a diagram for explaining a state of forming a plurality of mask patterns in step S214 in FIG.

[Explanation of reference numerals] 101 storage device 102 control device 103 input device 104 display device 301 input side flip-flop circuit 302 combination circuit 303 output side flip-flop circuit 801 to 803 mask pattern S201 to S214 steps

Claims (12)

[Claims] 1. A method of designing a semiconductor integrated circuit for designing the layout and wiring of transistors constituting a semiconductor integrated circuit based on a netlist, wherein a delay time of each wiring path is predetermined after designing layout and wiring. A method for designing a semiconductor integrated circuit, comprising: checking whether the delay time is within a predetermined value, and correcting the delay time only for a wiring path having a delay time exceeding the predetermined value. 2. The semiconductor integrated circuit designing method according to claim 1, wherein the delay time of the wiring path is reduced by replacing a transistor in the wiring path with a transistor having a short delay time. Circuit design method. 3. The method for designing a semiconductor integrated circuit according to claim 1, wherein the delay time of the wiring path is shortened by thickening the metal layer of the wiring in the wiring path. Design method. 4. The semiconductor integrated circuit designing method according to claim 1, wherein the delay time of the wiring path is shortened by increasing the thickness of the interlayer film of the wiring in the wiring path. Design method. 5. A method of designing a semiconductor integrated circuit for designing the layout and wiring of MOS transistors constituting a semiconductor integrated circuit based on a netlist, wherein a delay time of each wiring path is preset after designing layout wiring. It is confirmed that the delay time is shortened by changing the threshold voltage of the transistor in the wiring path only for the wiring path having the delay time exceeding the predetermined value. Design method of semiconductor integrated circuit. 6. The method for designing a semiconductor integrated circuit according to claim 5, wherein a delay time is shortened by changing a threshold voltage of a transistor in the wiring path only for a wiring path having a delay time exceeding a predetermined value. After that, the consumption current in each wiring path is compared with a second predetermined value, and only the wiring path having the consumption current exceeding the second predetermined value is consumed by changing the threshold voltage of the transistor in the wiring path. A method for designing a semiconductor integrated circuit, characterized by performing a correction for reducing a current. 7. A storage device, a display device, an input device,
An operation based on the contents of the netlist input to the input device, the program stored in the storage device, and the data to be stored, the display contents are output to the display device, and the arrangement of the transistors forming the semiconductor integrated circuit; In a semiconductor integrated circuit design device including a control device for designing wiring, the control device designs the layout wiring, and then confirms whether the delay time of each wiring path is within a predetermined value set in advance and displays the display. A semiconductor integrated device characterized by displaying on a device, and thereafter, when an input for making a correction is made to the input device, a correction for reducing the delay time is made only for a wiring path having a delay time exceeding the predetermined value. Circuit design equipment. 8. The semiconductor integrated circuit design device according to claim 7, wherein the control device shortens the delay time of the wiring path by replacing a transistor in the wiring path with a transistor having a short delay time. A semiconductor integrated circuit design device. 9. The semiconductor integrated circuit design device according to claim 7, wherein the control device shortens the delay time of the wiring path by thickening the metal layer of the wiring in the wiring path. Semiconductor integrated circuit design device. 10. The semiconductor integrated circuit design device according to claim 7, wherein the control device shortens the delay time of the wiring path by thickening the interlayer film of the wiring in the wiring path. Semiconductor integrated circuit design device. 11. The semiconductor integrated circuit design device according to claim 7, wherein the control device, when the transistor forming the semiconductor integrated circuit is a MOS transistor, applies only to a wiring path having a delay time exceeding a predetermined value. A device for designing a semiconductor integrated circuit, wherein correction is performed to shorten a delay time by changing a threshold voltage of a transistor in a wiring path. 12. The semiconductor device design apparatus according to claim 11, wherein the control device shortens the delay time by changing the threshold voltage of the transistor in the wiring path only for the wiring path having a delay time exceeding a predetermined value. After making corrections to
When the current consumption in each wiring path is compared with the second predetermined value and displayed on the display device, and thereafter, an input for making a correction is made to the input device, the current consumption exceeding the second predetermined value. The device for designing a semiconductor integrated circuit, wherein the correction is performed to reduce the current consumption by changing the threshold voltage of the transistor in the wiring path only.