JP2002151594A - Design method for semiconductor integrated circuit and design support apparatus for semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a design method of a semiconductor integrated circuit and a design support apparatus of the semiconductor integrated circuit suitable for preventing a wiring length from becoming long at the time of design change. SOLUTION: As cells constituting a circuit element, a part of the circuit element is constituted of standard cells C11-C21 and C23-C42, the remaining part of the circuit element is constituted of the cells composed by wiring a plurality of basic cells C22, D16 and D25 in a prescribed pattern, the cells constituting the circuit element are arranged in a cell arranging area and the plurality of the basic cells are arranged in a non-arranging area in the cell arranging area. In the case of changing the design for the semiconductor integrated circuit, the basic cells in the arranging area and the non-arranging area are wired corresponding to the functions after changing the design on the basis of design change data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit design method and a semiconductor integrated circuit design support apparatus.
In particular, the present invention relates to a semiconductor integrated circuit design method and a semiconductor integrated circuit design support device that are suitable for preventing an increase in wiring length when performing a design change.

[0002]

2. Description of the Related Art Custom LSI (Large Scale Integration) circuits designed in accordance with the purpose of a customer are roughly classified into full custom and semi-custom. Among them, the latter includes a standard system using a standard cell and a gate array system using a gate array.

In the gate array system, a semiconductor chip in which basic cells composed of a combination of logic gates are regularly arranged is prepared in advance, and a wiring pattern corresponding to a circuit according to a customer's request is added to the semiconductor chip. This is to complete a typical LSI circuit. Therefore, although the gate array method shortens the design period, there are many cells that are not used depending on the contents of the circuit, and the basic cell itself has a redundant shape, so that the size of the semiconductor integrated circuit is reduced. Not very suitable for

On the other hand, in the standard method, data for constructing standard cells having various functions is stored in a storage device called a cell library in advance. A desired semiconductor integrated circuit is configured by selecting a standard cell having a desired function from a cell library and wiring-connecting the selected standard cell corresponding to the function of the semiconductor integrated circuit desired by the designer. Is what you do.

[0005] The standard system has features such as being free from functional restrictions at all, having a 100% utilization rate of basic elements, and preventing useless areas, as compared with the gate array system.

Here, when the function of the semiconductor integrated circuit once designed is changed (including the case where the function is added), if the whole semiconductor integrated circuit is redesigned, the development time is extended. As a result, the development cost is further increased.

Therefore, as a method of preventing these problems and smoothly changing the functions, a standard cell (hereinafter, referred to as a dummy cell) irrelevant to the functions to be provided in the semiconductor integrated circuit corresponds to the functions to be provided. A plurality of standard cells are placed separately in the same semiconductor chip in advance, and when a design change is made to the semiconductor integrated circuit, those dummy cells are selected based on the function to be changed, and the selected dummy cells and A method for reducing the development cost by re-connecting the standard cell to minimize the design change of the original standard cell and reducing the development cost (hereinafter referred to as a first design method using the conventional standard method). Is commonly done.

Further, when a plurality of basic cells are arranged in advance in an area other than the area where the standard cells are arranged in the cell arrangement area, and the design of the semiconductor integrated circuit is changed, the basic cell is determined based on the function to be changed. Then, wire those basic cells according to the function after the design change,
A method to reduce the development cost by minimizing the design change of the original standard cell by reconnecting the original standard cell with the cell having the specified function by wiring the basic cell , A second standard design method based on the conventional standard method) is also generally performed.

[0009]

However, in the first design method based on the conventional standard system, the dummy cell and the standard cell are reconnected when the design is changed. The standard cells are not always arranged in the vicinity of the selected dummy cell, and in such a case, if these cells are wired, the wiring length becomes unnecessarily long.

In addition, the second standard according to the conventional standard method is used.
The same applies to the design method of the above, and the standard cells to be connected are not always arranged in the vicinity of cells having a predetermined function formed by wiring basic cells. If the wires are connected to each other, there is a problem that the wire length becomes longer than necessary. For example, as a design change to the semiconductor integrated circuit shown in FIG. 5A, cells D ₁₆ and D ₂₅ are formed as additional cells by arranging basic cells previously arranged in a non-arranged area, and the standard cells C ₁₁ and C ₂₅ are formed. when wiring a standard cell C ₂₂ and the cell D ₁₆ as well as wiring and D _25, as shown in FIG. 5 (b), standard cell C _11, C ₂₂ cell D _25, D ₁₆
The wiring length becomes extremely large as a result of the design change because it is located away from the wiring.

In particular, in recent years, with the miniaturization of design rules,
By making the design change, the wiring length becomes longer,
There is a problem that specifications that were satisfied before the design change are not satisfied after the design change.

Therefore, the present invention has been made in view of such an unsolved problem of the conventional technology, and is suitable for preventing an increase in the wiring length when making a design change. It is an object of the present invention to provide a semiconductor integrated circuit design method and a semiconductor integrated circuit design support device.

[0013]

According to a first aspect of the present invention, there is provided a method for designing a semiconductor integrated circuit, comprising: arranging a cell constituting a circuit element in a cell arrangement region; A plurality of basic cells are arranged in a non-arranged area other than the arranged area in which the cells constituting the circuit element are arranged in the arranged area, and the basic cells in the non-arranged area are determined based on design change data relating to the function after the design change. In the method of designing a semiconductor integrated circuit for wiring corresponding to the function after the design change, as a cell constituting the circuit element, a part of the circuit element is constituted by a functional cell having a predetermined function, and The method includes a cell configuration step in which the remainder is configured by a cell formed by wiring a plurality of basic cells in a predetermined pattern.

According to such a method, through a cell forming step, as a cell constituting a circuit element, a part of the circuit element is constituted by a functional cell having a predetermined function, and the rest of the circuit element is constituted by a plurality of cells. It is composed of cells formed by wiring basic cells in a predetermined pattern. Then, these cells are arranged in the cell arrangement area, and a plurality of basic cells are arranged in the non-arrangement area. When a design change is performed on a semiconductor integrated circuit designed in this way, the basic cells in the non-placement area and the basic cells in the cell placement area are wired according to the function after the design change based on the design change data. Is done.

For example, in such a wiring process, if the wiring length between the basic cell in the non-placement area and the functional cell or the basic cell in the placement area becomes large only by the wiring of the basic cell in the non-placement area, If wiring is performed not only for the basic cells in the placement area but also for the basic cells in the placement area, the wiring length can be reduced.

Here, specific methods of the present method include:
For example, the following method can be used. That is, the design change data is read from a storage unit for storing the design change data.

According to such a method, when a design change is made to the semiconductor integrated circuit, the design change data is read from the storage means, and based on the read design change data, the non-arranged area is changed. The basic cells are wired according to the function after the design change.

Further, according to a second aspect of the present invention, in the method of designing a semiconductor integrated circuit according to the first aspect, the arrangement area and the non-arrangement are arranged based on the design change data. Includes a wiring step of wiring the basic cells in the area corresponding to the function after the design change.

According to such a method, the basic cells in the placement area and the non-placement area are wired according to the function after the design change based on the design change data through the wiring step.

On the other hand, in order to achieve the above object, a semiconductor integrated circuit design support apparatus according to claim 3 of the present invention arranges cells constituting circuit elements in a cell arrangement area,
A plurality of basic cells are arranged in a non-arrangement area other than an arrangement area in which cells constituting the circuit elements are arranged in the cell arrangement area, and based on design change data relating to a function after a design change, the In a semiconductor integrated circuit design support apparatus for wiring a basic cell corresponding to a function after a design change, as a cell constituting the circuit element, a part of the circuit element is constituted by a function cell having a predetermined function, and There is provided cell configuration means for configuring the remainder of the circuit element by a cell in which a plurality of basic cells are wired in a predetermined pattern.

According to this structure, the cell constituting means constitutes a circuit element as a cell constituting a circuit element, a part of the circuit element is constituted by a functional cell having a predetermined function, and the rest of the circuit element comprises a plurality of basic cells. It is composed of cells formed by wiring cells in a predetermined pattern. Then, those cells are arranged in a cell arrangement area, and a plurality of basic cells are arranged in a non-arrangement area in the cell arrangement area. When a design change is performed on the semiconductor integrated circuit designed in this way, the basic cells in the non-arranged area are wired according to the function after the design change based on the design change data.

For example, in such a wiring process, when the wiring length of the basic cell in the non-arranged area alone and the wiring length between the basic cell in the non-arranged area and the functional cell or the basic cell in the arranged area becomes large, If wiring is performed not only for the basic cells in the placement area but also for the basic cells in the placement area, the wiring length can be reduced.

Here, as a specific configuration of the present apparatus,
For example, the following configuration is given. That is, the design change data is read from a storage unit for storing the design change data.

With this configuration, when a design change is performed on the semiconductor integrated circuit, the design change data is read from the storage means, and the non-arranged area is read out based on the read design change data. The basic cells are wired according to the function after the design change.

Here, the storage means stores the design change data by any means and at any time.
The design change data may be stored in advance,
The design change data may be stored during the operation of the present apparatus.

According to a fourth aspect of the present invention, there is provided a semiconductor integrated circuit design support apparatus according to the third aspect of the present invention, wherein the placement area and the semiconductor device are arranged based on the design change data. There is provided wiring means for wiring the basic cells in the non-placement area in accordance with the function after the design change.

With such a configuration, the wiring means routes the basic cells in the arrangement area and the non-arrangement area in accordance with the function after the design change based on the design change data.

In the above, a semiconductor integrated circuit design method and a semiconductor integrated circuit design support device for achieving the above object have been proposed. However, the present invention is not limited thereto. Also, a storage medium storing a design support program for the second semiconductor integrated circuit can be proposed.

In the storage medium storing the first semiconductor integrated circuit design support program, cells constituting circuit elements are arranged in a cell arrangement area, and cells constituting the circuit elements are arranged in the cell arrangement area. A semiconductor integrated circuit in which a plurality of basic cells are arranged in a non-arranged area other than the arranged area, and the basic cells in the non-arranged area are wired corresponding to the function after the design change based on design change data on the function after the design change. A storage medium storing a circuit design support program,
As a cell constituting the circuit element, a cell configuration in which a part of the circuit element is configured by a functional cell having a predetermined function, and the remainder of the circuit element is configured by a cell in which a plurality of basic cells are wired in a predetermined pattern. As means, a computer-readable storage medium storing a program for causing a computer to function.

With such a configuration, the program stored in the storage medium is read by the computer,
When the computer functions according to the read program, the same operation as the semiconductor integrated circuit design support device according to the third aspect is obtained.

Therefore, when the design of the semiconductor integrated circuit is changed, the cell to be connected to the placement area may be located near the basic cell in the non-placement area. In making the change, the effect that the increase in the wiring length can be relatively prevented can be obtained.

The storage medium storing the second semiconductor integrated circuit design support program is the storage medium storing the first semiconductor integrated circuit design support program based on the design change data. A computer-readable storage medium storing a program for causing a computer to function as wiring means for wiring the basic cells in the non-placement area in accordance with the function after the design change.

With such a configuration, the program stored in the storage medium is read by the computer,
When the computer functions according to the read program, the same operation as the semiconductor integrated circuit design support device according to the fourth aspect is obtained.

[0034]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 4 are diagrams showing an embodiment of a semiconductor integrated circuit design method and a semiconductor integrated circuit design support apparatus according to the present invention.

In the present embodiment, as shown in FIG. 4, a semiconductor integrated circuit design method and a semiconductor integrated circuit design support apparatus according to the present invention are provided by using cells (standard cells and Basic cell) and a plurality of basic cells are arranged in the non-arranged area.
This is applied to a case where basic cells in the arrangement area and the non-arrangement area are wired according to the function after the design change.

First, the configuration of a computer system to which the present invention is applied will be described with reference to FIG. FIG. 1 is a block diagram showing a configuration of a computer system to which the present invention is applied.

As shown in FIG. 1, the computer 100 has a CPU 30 for controlling the operation and the whole system based on the control program, and a CPU 30
A ROM 32 storing a control program and the like for 30;
A RAM 34 for storing data read from the ROM 32 and the like and calculation results required in the calculation process of the CPU 30;
A CRTC 36 that converts data stored in a specific area of the RAM 34 into an image signal and outputs the image signal to the display device 44;
I / F 38 for mediating data input / output to / from external devices
These are mutually connected by a bus 39, which is a signal line for transferring data, so that data can be exchanged.

The I / F 38 includes, as external devices, an input device 40 such as a keyboard and a mouse capable of inputting data as a human interface, a storage device 42 for storing data and tables as files, and an image signal for image signals. A display device 44 for displaying a screen based on the information is connected.

The RAM 34 is a VRAM that stores display data to be displayed on the display device 44 as a specific area.
The VRAM 35 includes a CPU 30 and a CR.
Access is possible independently with the TC 36.

The CRTC 36 sequentially reads display data stored in the VRAM 35 from a start address at a predetermined period, converts the read display data into an image signal, and outputs the image signal to the display device 44.

The storage device 42 has a role as a cell library for storing arrangement data for constructing standard cells having various functions in advance, and when making a design change to the semiconductor integrated circuit, The storage device 42 stores design change data relating to functions after the design change. Specifically, the design change data is configured to include placement data on the placement of cells to be added, deleted or changed, and wiring data on the wiring of those cells.

When designing a semiconductor integrated circuit, the CPU 30 starts up a predetermined program stored in a predetermined area of the ROM 32 and, in accordance with the program, executes the design shown in the flowchart of FIG. When executing the support processing and performing a design change on the semiconductor integrated circuit designed by the design support processing, a predetermined program stored in a predetermined area of the ROM 32 is started, and according to the program,
The design change support processing shown in the flowchart of FIG. 3 is executed.

First, the design support processing will be described with reference to FIG. FIG. 2 is a flowchart showing the design support processing.

The design support processing generates chip mask pattern data necessary for manufacturing a semiconductor chip in a semiconductor integrated circuit and wiring mask pattern data necessary for forming a wiring pattern in the semiconductor integrated circuit. When the processing is executed by the CPU 30, the processing shown in FIG.
As shown in (1), the process first proceeds to step S100.

In step S100, some of the elements in the library are registered as standard cells.
Move to 2. In this step S100, the designer selects a standard cell having a desired function from the storage device 42, and defines a connection relationship for the selected standard cell corresponding to the function of the semiconductor integrated circuit desired by the designer. It is done by doing. The configuration here is performed in a space virtually formed on the computer 100. Hereinafter, the same applies to the configuration of the basic cell.

In step S102, another part of the elements in the library is registered in the gate array, and step S10
Move to 4. This step S102 is performed by defining the connection relation of a plurality of basic cells corresponding to the function of the semiconductor integrated circuit desired by the designer.
Note that the ratio of the standard cell and the basic cell in the circuit element is appropriately set according to an empirical rule or the like.

In step S104, step S10
On the basis of the configurations in steps S0 and S102, cells constituting circuit elements are arranged and wired in the cell arrangement area of the semiconductor chip by an automatic wiring algorithm or the like. And the other part is constituted by a gate array.), Step S10
In step S108, a plurality of basic cells are arranged in a non-arranged area other than the arranged area in which the cells forming the circuit elements are arranged in the cell arranged area of the semiconductor chip.
Move to Here, the basic cell in the non-arranged area is
It is arranged in advance assuming that a new circuit will be added after the design change.

In step S108, step S10
4. The chip mask pattern data and the wiring mask pattern data are generated based on the arrangement / wiring result in S106, and the process proceeds to step S110 to store the generated chip mask pattern data and the wiring mask pattern data in the storage device 42. Then, a series of processing ends.

Next, the design change support processing will be described with reference to FIG. FIG. 3 is a flowchart showing the design change support processing.

The design change support process is a process for generating wiring mask pattern data after a design change based on the design change data.
As shown in FIG. 3, the process first proceeds to step S150.

In step S150, the design change data is read from the storage device 42, and the process proceeds to step S152, where the basic cells in the arrangement area and the non-arrangement area are wired based on the read design change data (in this case, the standard cell). The part does not move.) Then, the process proceeds to step S154, and based on the wiring result in step S152,
Wiring mask pattern data is generated, and step S156 is performed.
Then, the generated wiring mask pattern data is stored in the storage device 42, and a series of processing ends.

Next, the operation of the above embodiment will be described with reference to FIG. FIG. 4 is a diagram for explaining a case where a design change is performed on a semiconductor integrated circuit according to the present invention.

First, a case of designing a semiconductor integrated circuit will be described.

When designing a semiconductor integrated circuit, the designer goes through steps S100 and S102 and goes to the storage device 42.
By selecting a standard cell having a desired function from among the standard cells and defining the connection relation of the selected standard cell corresponding to the function of the semiconductor integrated circuit to be realized, a part of the circuit elements can be standard cell. Then, by defining the connection relationship for a plurality of basic cells corresponding to the function of the semiconductor integrated circuit to be realized, the rest of the circuit elements are cells formed by wiring a plurality of basic cells in a predetermined pattern. Constitute.

When the circuit elements are configured in this manner, the CPU 30 goes through steps S104 and S106 and, based on the configuration performed by the designer, uses an automatic wiring algorithm or the like to execute the standard configuration of the circuit elements in the cell placement area of the semiconductor chip. Cells and basic cells are arranged and wired, and a plurality of basic cells are arranged in a non-arranged region of the semiconductor chip.

In the example of FIG. 4A, the cell of the semiconductor chip is
A circuit element is formed in the first cell column of the arrangement region.
Cell C composed of standard cells among cells₁₁~ C
_FifteenAre arranged in that order from the left, and multiple basic
Cell D consisting of cells₁₆Are arranged in the non-arranged area.
The second cell column in the cell arrangement region of the semiconductor chip
The standard cell among the cells that constitute the circuit element
Cell C composed of_{twenty one}And the cells that constitute the circuit elements
Cell C composed of a plurality of basic cells_{twenty two}And the circuit
It consists of standard cells among the cells that make up the device.
Cell C_{twenty three}, C _{twenty four}Are arranged in that order from the left,
Cell D composed of a plurality of basic cells_{twenty five}Is in the non-placed area
Are located.

In the third cell column of the cell arrangement region of the semiconductor chip, cells C ₃₁ and C ₃₂ composed of standard cells among the cells constituting the circuit element are arranged in this order from the left. In the fourth cell column of the cell arrangement region of the semiconductor chip, cells C ₄₁ and C ₄₂ constituted by standard cells among the cells constituting the circuit element are arranged in this order from the left.

Next, through steps S108 and S110, chip mask pattern data and wiring mask pattern data are generated based on the placement and wiring results in steps S104 and S106, and the generated chip mask pattern data and wiring mask pattern are generated. The data is stored in the storage device 42.

Then, a semiconductor integrated circuit is manufactured based on the chip mask pattern data and the wiring mask pattern data. Specifically, a semiconductor chip is manufactured by forming bulk layers of standard cells and basic cells on a substrate using a mask pattern manufactured based on chip mask pattern data. Then, a wiring layer for wiring standard cells and basic cells is formed on the manufactured semiconductor chip by a mask pattern manufactured based on the wiring mask pattern data, whereby a semiconductor integrated circuit is manufactured.

Next, a case where a design change is made to the semiconductor integrated circuit thus designed will be described. here,
For example, as a design change to the semiconductor integrated circuit shown in FIG. 4A, cells D ₁₆ and D ₂₅ are formed as additional cells by arranging basic cells previously arranged in a non-arranged area, and the standard cells C ₁₁ and C ₂₅ are formed. a case in which wiring and standard cells C ₂₂ and cell D ₁₆ with wiring and D ₂₅ will be described as an example.

When the above-described design change is performed on the semiconductor integrated circuit shown in FIG.
After 0, S152, the CPU 30 reads the design change data from the storage device 42, and based on the read design change data, the basic cells in the placement area and the non-placement area are reduced so that the wiring length is reduced. Wired according to the function after the design change.

Here, the standard cell C ₁₁ and the cell D ₂₅
The door, and it is a than simply wiring the standard cells C ₁₁ and the cell D _25, as shown in FIG. 5 (b), standard cell C _11, C ₂₂ is separated from the cell D _25, D ₁₆ position Therefore, the wiring length becomes extremely large. Therefore, as shown in FIG. 4 (b), the arranged basic cells in the blank region of the second cell row wiring as a cell C _22, the arranged basic cells in arrangement region of the second cell row by wiring the cell D _25, the basic cell arrangement areas and blank region is the wiring in response to function after the design change. Thereby, located near a cell D ₂₅ is a standard cell C ₁₁ to be the target for connection of the additional cell, since the cell C ₂₂ to be connected is positioned in the vicinity of the cell D ₁₆ as additional cell And the wiring length is reduced.

Next, after steps S154 and S156, the wiring mask pattern data after the design change is generated based on the wiring result in step S152, and the generated wiring mask pattern data is stored in the storage device 42.

Then, a semiconductor integrated circuit is manufactured based on the wiring mask pattern data after the design change. More specifically, a new wiring layer for wiring standard cells and basic cells is formed by using a mask pattern manufactured based on the wiring mask pattern data after the design change. ), A semiconductor integrated circuit is manufactured.

As described above, in the present embodiment, as a cell constituting a circuit element, a part of the circuit element is constituted by a standard cell, and the rest of the circuit element is formed by wiring a plurality of basic cells in a predetermined pattern. When design changes are made to a semiconductor integrated circuit by placing cells constituting circuit elements in the cell placement area and placing a plurality of basic cells in the non-placement area, Based on the data, the basic cells in the placement area and the non-placement area are wired according to the function after the design change.

Thus, the cell D ₂₅ as an additional cell is located near the standard cell C ₁₁ to be connected, and the cell C ₂₂ to be connected is the cell D ₂₅ as an additional cell.
Since it is located in the vicinity of ₁₆ , it is possible to relatively prevent an increase in the wiring length when making a design change as compared with the related art.

In the above embodiment, the basic cell corresponds to the basic cell described in claims 1 to 4, and the standard cell corresponds to the functional cell having a predetermined function according to claim 1 or 3.

Although the above embodiment has not been described with particular consideration for the wiring between cells in the arrangement region,
When a design change is performed on the semiconductor integrated circuit, the layout area is set so that the total wiring length of the wiring connecting the cells in the layout area and the cells in the non-layout area and the wiring length connecting the cells in the layout area is reduced. The basic cells in the non-arranged area may be wired according to the function after the design change.

Further, in the above-described embodiment, the case where the control program stored in the ROM 32 is executed in executing the processes shown in the flowcharts of FIGS. 2 and 3 has been described. Instead, the program may be read from the storage medium storing the program indicating these procedures into the RAM 34 and executed.

Here, the storage medium is a semiconductor storage medium such as a RAM or a ROM, a magnetic storage type storage medium such as an FD or HD, an optical read type storage medium such as a CD, CDV, LD, or DVD, or an MO storage medium. A magnetic storage type / optical readout type storage medium includes any storage medium that can be read by a computer regardless of an electronic, magnetic, optical, or other read method.

Further, in the above-described embodiment, as shown in FIG. 4, the semiconductor integrated circuit design method and the semiconductor integrated circuit design support apparatus according to the present invention are applied to the cells (cells) constituting circuit elements in the cell arrangement region. Standard cells and basic cells) are arranged, and a plurality of basic cells are arranged in the non-arranged area. When the design of the semiconductor integrated circuit is changed, the basic cells in the arranged area and the non-arranged area are changed after the design change. However, the present invention is not limited to this case, and may be applied to other cases without departing from the gist of the present invention.

[0072]

As described above, according to the method for designing a semiconductor integrated circuit according to the first or second aspect of the present invention, when a design change is made to the semiconductor integrated circuit, the connection target of the arrangement region is changed. May be located near the basic cell in the non-arranged area.
An effect is obtained in that it is possible to relatively prevent an increase in the wiring length when making a design change.

On the other hand, according to the semiconductor integrated circuit design support apparatus according to the third or fourth aspect of the present invention, when a design change is performed on the semiconductor integrated circuit, the cells to be connected to the placement area are not connected. Since it may be located in the vicinity of the basic cell in the arrangement region, it is possible to obtain an effect that it is possible to relatively prevent an increase in the wiring length when making a design change as compared with the related art.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a computer system to which the present invention is applied.

FIG. 2 is a flowchart illustrating a design support process.

FIG. 3 is a flowchart illustrating a design change support process.

FIG. 4 is a diagram for explaining a case where a design change is performed on a semiconductor integrated circuit according to the present invention.

FIG. 5 is a diagram for explaining a case where a design change is performed on a semiconductor integrated circuit by a second conventional design method using a standard method.

[Explanation of symbols]

100 Computer 30 CPU 32 ROM 34 RAM 38 I / F 40 input device 42 storage device 44 display device C ₁₁ -C ₂₁ standard cells C ₂₃ -C ₄₂ standard cell C ₂₂ basic cell D _16, D ₂₅ basic cells

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B046 AA08 BA05 BA06 5F064 AA03 AA04 DD02 DD14 DD20 DD26 DD50 EE02 EE08 EE60 HH02 HH06 HH11 HH12

Claims (4)

[Claims] 1. A cell constituting a circuit element is arranged in a cell arrangement area, and a plurality of basic cells are arranged in a non-arrangement area other than an arrangement area in which a cell constituting the circuit element is arranged in the cell arrangement area. A method for designing a semiconductor integrated circuit in which the basic cells in the non-placement area are wired in accordance with the functions after the design change based on the design change data on the functions after the design change, A semiconductor comprising a step of forming a part of the circuit element by a functional cell having a predetermined function and forming a remainder of the circuit element by a cell formed by wiring a plurality of basic cells in a predetermined pattern. How to design integrated circuits. 2. The method according to claim 1, further comprising the step of wiring the basic cells in the placement area and the non-placement area in accordance with the function after the design change based on the design change data. A method for designing a semiconductor integrated circuit. 3. A cell constituting a circuit element is arranged in a cell arrangement area, and a plurality of basic cells are arranged in a non-arranged area of the cell arrangement area other than an arrangement area in which cells constituting the circuit element are arranged. A semiconductor integrated circuit design support apparatus for wiring a basic cell in the non-placement area in accordance with the function after the design change based on the design change data on the function after the design change; A cell configuration means for configuring a part of the circuit element with a functional cell having a predetermined function and configuring the remainder of the circuit element with a cell formed by wiring a plurality of basic cells in a predetermined pattern. Design support equipment for semiconductor integrated circuits. 4. The device according to claim 3, further comprising wiring means for wiring the basic cells in the placement area and the non-placement area in accordance with the function after the design change based on the design change data. Design support equipment for semiconductor integrated circuits.