JP3476688B2 - Netlist generation method and netlist generation device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a device to change the parameters in the circuit design data necessary for the design of the circuit, in particular, with facilitated the design work, aims to improve the reliability of the design , moreover it relates net list generating apparatus that can the be managing the cell library easily.

[0002]

2. Description of the Related Art Generally, when designing a semiconductor LSI,
Due to its large scale, the circuit to be designed is divided into multiple functional blocks, and these functional blocks are further divided into smaller cells. Are designed. Therefore, the circuit design data of each cell is recorded in each individual module, but the circuit design data of the functional block designed by using these cells is recorded in the module by referring to the module of each cell. Further, the circuit design data of the circuit to be designed which is designed by using these functional blocks is recorded in the module by referring to the module of each functional block. Therefore, finally, the circuit design data of the circuit to be designed is stored in a storage device or the like in a state in which a plurality of modules in which the circuit design data is recorded are hierarchically linked. When shifting from the circuit design stage to the layout stage, the circuit design data of each module are associated with each other to generate a netlist, and the layout design is performed using this netlist.

On the other hand, in a semiconductor LSI, in order to minimize the influence of power supply noise, a plurality of power supplies may be used in the circuit, and the connection state of these power supplies is changed in the layout design stage after the circuit design stage. May need to be done. In such a case, the power supply connection setting is performed again after returning to the circuit design stage.However, conventionally, when changing the power supply name, which is one of the parameters in the circuit design data, after designing, for example, change the name. It is said that each circuit module that uses the power supply to be changed is read out one by one and displayed on the screen of a computer, etc., and the power supply name is changed to a new power supply name while inputting with the keyboard etc. on the screen. The change work was done for all usage points.

[0004]

As described above, in the conventional method for changing the parameters, when the scale of the circuit to be designed is small and the number of circuits using the power supply whose name is to be changed is small. Although the change work does not require much labor, if the scale of the circuit to be designed becomes large and there are many circuits using the power supply whose name is to be changed, not only will the change work become enormous. , It is easy to make mistakes and oversights during the change process. In particular, the power supply
Since it varies depending on the circuit design specifications, it is difficult to centrally manage it by providing a common library.

Therefore, the present invention has been made by paying attention to such unsolved problems of the conventional techniques, and facilitates design work and improves design reliability. Moreover it is an object to provide a net list generation apparatus that can the be managing the cell library easily.

[0006]

[0007]

[0008]

[0009]

[0010]

[0011]

To achieve the above Symbol purposes SUMMARY OF THE INVENTION, the net list generating apparatus according to claim 1, wherein according to the present invention, a plurality of modules including a circuit design data necessary for designing the circuit A device for generating a netlist, which is hierarchically linked and stored in a storage unit, and is given a predetermined identifier to the module name of the module to associate the circuit design data of each of the modules with each other, Identifier acquisition means for acquiring the identifier from the module name of the module, module reading means for reading the module from the storage means, circuit hierarchy of the module that has acquired the identifier, and circuit design data of the module in a hierarchy lower than the hierarchy. Parameter change to change the parameters in the batch with reference to the acquired identifier It comprises a stage, wherein the storage means, before
Write a table that associates identifier types with change rules.
Recall that the parameter changing means has acquired the
Change rule is determined from the table based on the identifier
Of the module based on the determined change rule.
The parameters in the circuit design data have been changed
There is .

With such a configuration, when an identifier is given to the module name of any one of the modules of the storage unit, the identifier acquisition unit acquires the identifier from the module to which the identifier is given, and reads the module. Each module is read from the storage means by the means. When each module is read, the parameter changing unit creates a table based on the acquired identifier.
The change rule is determined by the
In addition , among the read modules, the parameters in all the circuit design data of the module hierarchy to which the identifier is given and the module hierarchy lower than this are collectively changed with reference to the acquired identifier. Is
A netlist is generated based on the changed parameters.

If identifiers are given to the module names of a plurality of modules in different layers,
When changing the parameters in the circuit design data of each module, the identifier given to the module name of the module in the closest hierarchy when referring to the upper hierarchy from its own hierarchy is referred to. There is.

Further, a netlist generating device according to a second aspect of the present invention is the netlist generating device according to the first aspect , in which the module among the modules to which the identifier is given is selected.
Before in the hierarchy above and below
Change the parameters in the circuit design data of the module.
When you look at the upper hierarchy from your own hierarchy,
The module of the module of the nearest hierarchy of the number identifier
Process that refers to the one given to the
The hierarchy of the highest module among the modules that gave identifiers
And the circuit of the module in a lower hierarchy
The parameters in the design data are the parameters that are given the identifier.
Refer to the identifier given to the top of the
And the method of setting either one of the processing to change all at once
And the parameter changing means is based on the setting.
Change the parameters by any of the above
Growling .

With such a configuration, the setting means
If any of the above processing is set, the parameters will be changed.
By means of any of the above processes based on its settings
The parameters are changed .

Further, the netlist generating device according to claim 3 of the present invention is the netlist generating device according to claim 1 or 2 , wherein the module name includes a module name and a module suffix. It is included, and the identifier is given as the module suffix, and the identifier acquisition means acquires the module suffix of the module.

With such a configuration, the module suffix of the module is obtained by the identifier obtaining means.

Further, a netlist generating device according to a fourth aspect of the present invention is the netlist generating device according to any of the first to third aspects, in which the parameter is a power supply name.

With such a configuration, the parameter changing means collectively changes the power supply name in the read circuit design data of the module with reference to the acquired identifier.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. 1 to 5 are diagrams showing an embodiment of a net list generating device according to the present invention.

In this embodiment, the netlist generating apparatus according to the present invention is applied to realize a global net assigning function for generating a netlist necessary for all CAD tools including layouts. Specifically, in the state in which a plurality of modules including circuit design data necessary for designing a circuit are hierarchically linked, net assignment is designated for each module, so that This is applied when collectively changing the power supply name of.

First, the structure of the net list generating apparatus according to the present invention will be described. FIG. 1 is a block diagram showing the configuration of a netlist generation device according to the present invention.

The computer 10, as shown in FIG.
A CPU 12 that controls arithmetic operations and the entire system based on a predetermined program, and a CPU 1 in a predetermined area in advance.
ROM 14 which stores the program of 2 and the like
RAM 16 for storing data read from the CPU 14 and the like, and a calculation result necessary for the calculation process of the CPU 12, and a RAM
It is composed of a CRTC 18 that converts data stored in 16 specific areas into an image signal and outputs the image signal, and an I / F 20 that mediates input / output of data to / from an external device, and these transfer data. Bus 29 which is a signal line for
They are connected to each other and can exchange data.

The I / F 20 is connected as an external device with an input device 30 such as a keyboard and a mouse that can input data as a human interface, and a storage device 40 that stores modules and the like.

The RAM 16 is a VRAM for storing display data to be displayed on the display device 50 as a specific area.
VRAM 17 has a CPU 12 and a CR.
It can be accessed independently from TC18.

A display device 50 for displaying the output image signal on the screen is connected to the CRTC 18, and the CRTC 18 is connected to the CRTC 18.
18 sequentially reads the display data stored in the VRAM 17 from the head address at a predetermined cycle, converts the read display data into an image signal, and outputs the image signal to the display device 50.

Next, the data stored in the storage device 40 will be described with reference to FIG. FIG. 2 is a diagram showing the structure of the net assignment definition table.

A plurality of modules are hierarchically linked and stored in the storage device 40. The circuit design data of a module may include a circuit element (instance) that uses another module. In this case, the module has its module name in order to identify the module that is the instance to be used. Is recorded. That is, the state in which the modules are linked hierarchically means a state in which the circuit design data of a certain module includes an instance, and the circuit design data of the module that is the instance further includes an instance.

Further, in the storage device 40, as shown in FIG. 2, a net assignment definition table that defines how to change the power supply name in the circuit design data of the module by the net assignment designation given to the module. T
B is stored. The net assignment designation given to the module is to give an assign suffix for instructing to change the power supply name in the circuit design data of the module according to a predetermined change rule as the suffix name of the module. That is, the net assignment definition table TB is a table in which a plurality of such correspondences of assignment suffixes and change rules are registered. For example, in FIG. 2, the assignment suffix “.
In the case of “A”, the power supply name “V _DD ” is changed to the power supply name “DRV _DD ”, the power supply name “V _SS ” is changed to the power supply name “DRV _SS ”, and the power supply name “BV _DD ” is changed to the power supply name “DRV _DD It is for instructing to change to ".

Next, the configuration of the CPU 12 and the processing executed here will be described with reference to FIG. FIG. 3 is a flowchart showing a process for designing and laying out a circuit.

The CPU 12 is composed of a micro processing unit MPU or the like, and when designing and laying out a circuit, it activates a predetermined program stored in a predetermined area of the ROM 14 and executes the processing shown in the flowchart of FIG. It is like this.

First, a process for designing and laying out a circuit will be described with an example. CPU12
When this process is executed in, as shown in FIG.
The process proceeds to step S100 to perform circuit design and design verification using a general power supply name, the process proceeds to step S102 to create the net assignment definition table TB, the process proceeds to step S104, and the highest hierarchy The net assignment is designated only for the module in step S106, the process proceeds to step S106, the net list generation process according to the present invention is performed to change the power supply name in the circuit design data of the module in each layer, and the process proceeds to step S108. It is supposed to do.

In step S108, layout and layout verification are performed, and the process proceeds to step S110.
If it is determined that there is a correction related to the power supply name (Yes), the process proceeds to step S112, the net assignment is specified only for the module in the highest hierarchy, and the step is performed. The process returns to S106. On the other hand, when it is determined in step S110 that there is no correction regarding the power supply name (No), a series of processing is ended.

Next, in steps S102, S104,
Details of each processing of S106 and S112 will be described with reference to FIG.

The net assignment definition table creating step S102 will be described in detail in steps S200 and S20 of FIG.
2, the processing represented by S204, S206, and S208 is performed. That is, in step S102, as shown in FIG. 4, the process proceeds to step S200, the net assignment definition table TB is read from the storage device 40 to the RAM 16, and the process proceeds to step S202 to update the contents of the net assignment definition table TB. Display to the designer whether to do or not. If the content of the net assignment definition table TB is updated (Yes), the process proceeds to step S204, the net assignment definition information defining the change rule for the assignment suffix is input from the input device 30, and the step S204 is performed.
It moves to 206.

In step S206, the net assignment definition table TB is updated based on the input net assignment definition information, the process proceeds to step S208, the updated net assignment definition table TB is stored in the storage device 40, and in step S202. I'm supposed to come back.

Next, a net assign designation step S10.
4 is steps S210, S212, S2 in FIG.
14, the process represented by S218 is performed. That is,
If the contents of the net assignment definition table TB are not updated in step S202 (No), the process proceeds to step S210, and each module is transferred from the storage device 40 to the RAM 16
Read out to step S212 and display to the designer whether or not to update the assignment suffix of the module. When updating (Yes), go to step S214 and input the assignment suffix, Parameters are input from the input device 30, and the process proceeds to step S218. In step S218, the updated module is stored in the storage device 40, and then in step S212.
To return to.

Further, a netlist generation processing step S
At 106, the processes represented by steps S220 and S221 in FIG. 4 are performed. That is, step S212
If the designer decides not to update the assignment suffix of the module in (No), the process proceeds to step S220, and the power supply name change process for generating the netlist while changing the power supply name in the circuit design data of the module. And the process proceeds to step S221 to store the netlist generated in the power supply name changing process in the storage device 40,
The process proceeds to step S222, various verifications and execution of the automatic tool are performed, and the process returns to the original process (step S108).

Next, the power supply name changing process in step S220 will be described with reference to FIG. FIG. 5 is a flowchart showing the power supply name changing process.

In this power supply name changing process, the power supply name in the circuit design data of each module is recursively changed from the upper layer to the lower layer, and the process of step S220 is executed. At this time, the module name of the module in the highest layer and the assignment suffix name of the module when the net assignment is specified for the module are given as arguments to call the process.

When the processing is called in this way, as shown in FIG. 5, the module name given as an argument is stored in the character variable module, and the assignment suffix given as an argument is changed to the character variable ass. -suff
stored in ix, the process proceeds to step S300, and a character variable
The module corresponding to the module name of module is read from the storage device 40 to the RAM 16, the process proceeds to step S302, it is determined whether or not any assignment suffix is stored in the character variable ass-suffix, and the character variable ass-
If it is determined that the suffix is stored in suffix (Yes), the process proceeds to step S304.

In step S304, the character variable ass-suff
Change rules are determined by the net assignment definition table TB based on the assignment suffix of ix, all power supply names in the circuit design data of the module read in step S300 are changed according to the determined change rules, and the process proceeds to step S306. , When an instance in the circuit design data of the module read in step S300 is searched, it is determined in step S308 whether or not there is an instance, and when it is determined that there is an instance
(Yes) is adapted to move to step S310.

In step S310, the character variable cur-suff
The content of the character variable ass-suffix is stored in ix, and step S3
When it is determined that the net assignment is specified for the module that is the target instance and whether or not the net assignment is specified, the process proceeds to 12.
(Yes) moves to step S314 and the character variable ass-
When it is determined whether suffix has any assignment suffix stored, or whether the lower net assignment specification priority setting is valid, and it is determined that the assignment suffix is not stored in the character variable ass-suffix,
Alternatively, when it is determined that the lower net assign designation priority setting is valid (Yes), the process proceeds to step S316.

In this step S314, the lower net assign designation priority setting means that when the net assign designation is already made to the module in the upper hierarchy, a different net assign designation is made to the module in the lower hierarchy. When the power supply name in the circuit design data of the module in the lower hierarchy and the lower hierarchy is changed while This is a setting as to whether or not to give priority to the net assignment designation made to the lower one. In other words, if this setting is enabled, the net assignment specified for the lower one will take precedence, but if this setting is disabled, the net assignment will be specified for the lower one. However, ignoring this, the net assignment designation given to the higher order is prioritized. This valid / invalid setting is performed, for example, by switching flag variables “0” and “1”.

In step S316, the character variable cur-suff
The assignment suffix of the module that is the target instance is stored in ix, the process proceeds to step S318, the module name of the module that is the target instance is stored in the character variable cur-module, and the process proceeds to step S320.
This power supply changing process is recursively called with the character variable cur-module and the character variable cur-suffix as arguments, and when the process returns, the process proceeds to step S322, and the next instance in the circuit design data of the module read in step S300. Is searched and the process returns to step S308.

On the other hand, in step S314, the character variable ass-
If it is determined that the suffix is stored in suffix, or if it is determined that the lower net assign designation priority setting is invalid (No), step S31.
It is designed to move to 8.

On the other hand, when it is determined in step S312 that the module that is the target instance has not been assigned a net assignment (No), the process proceeds to step S318.

On the other hand, when it is determined in step S308 that there is no instance in the circuit design data of the module read in step S300 (No), the original process (step S220 or step S322) is returned to. Has become.

On the other hand, in step S302, the character variable
When it is determined that the assign suffix is not stored in the ass-suffix (No), the process proceeds to step S306.

Next, the operation of the above embodiment will be described with reference to the drawings. 6 to 8 are diagrams for explaining the operation of the embodiment of the netlist generating method according to the present invention.

Now, in step S100, as a result of designing and verifying the circuit using the power supply names "V _DD ", "V _SS ", "BV _DD ", and "BV _SS ", as shown in FIG. It is assumed that the circuit has been designed. That is, as shown in FIG. 6A, the highest hierarchy includes modules BLK-A, modules BLK-B, and modules BLK-C, among which modules As shown in FIG. 6 (b), BLK-A includes, as an instance, a module A1 in which “V _DD ” is set as a power supply name to be used, and a module A2 in which “V _SS ” is set as a power supply name to be used. ,It is included. Furthermore, the module
As shown in FIG. 6C, A1 includes a module DF1 as an instance and a module INV1 as an inverter circuit.
As shown in FIG. 6 (d), the INV1 has a p-type MOS in which "V _DD " and "BV _DD " are set as power source names to be used, and "V _SS " and "BV _SS " as power source names to be used. Set n
Type MOS and are included.

Then, in step S104, as shown in FIG.
As shown in (a), net assignment is designated for each module BLK-A, BLK-B, and BLK-C in the highest layer. Here, it is assumed that the module BLK-A is given the assignment suffix ".A", the module BLK-B is given the assignment suffix ".T", and the module BLK-C is given the assignment suffix ".R".

Then, steps S104 and S10.
6. If it is assumed that the net assignment definition table TB and the parameters in the circuit design data of the module have been appropriately updated through steps S200 to S218, the net assignment definition table TB is referred to in step S220, and The power supply name in the circuit design data of the module in the upper layer and the lower layer is changed. The lower net assign designation priority setting is invalid.

The process of changing the power supply name will be described in detail. First, in step S304, the power supply name is not changed because there is no power supply name to be changed. Since there is an instance, the module BLK-A is first detected in step S308. Next, in step S312, since it is determined that the net assignment designation is made to the module BLK-A, in steps S316 and S318, the assignment suffix ".A" of the module BLK-A.
Is stored in the character variable cur-suffix, and the module name “BLK-A” of module BLK-A is stored in the character variable cur-modu.
Stored in le. Then, the power supply name changing process is recursively called with the character variable cur-module and the character variable cur-suffix as arguments.

When the recursive process is executed, step S30
7, in accordance with the change rule corresponding to the assignment suffix “.A” in the net assignment definition table TB, as shown in FIG. 7B, the power supply name “module A1” in the circuit design data of the module BLK-A is used. The V _DD "is changed to a new power supply name" DRV _DD "and the power supply name" V _SS "used by the module A2 is changed to a new power supply name" DRV _SS ". Next, since module BLK-A has two instances, module A1 is detected first, and the contents of character variable ass-suffix, that is, the assignment suffix “.A” is stored in character variable cur-suffix,
Since it is determined that the net assignment is not specified for A1, the module name “A1” of the module A1 is stored in the character variable cur-module. And this character variable cu
The power supply name change process is recursively called with the r-module and the character variable cur-suffix as arguments.

When the recursive process is executed, the power supply name to be changed does not exist, so the power supply name is not changed.
As shown in FIG. 7C, since module A1 has two instances, module INV1 is detected first,
The contents of the character variable ass-suffix are stored in the character variable cur-suffix. Next, since it is determined that the net assignment is not specified for the module INV1, the module INV1
The module name "INV1" of INV1 is stored in the character variable cur-module. Then, the power supply name changing process is recursively called with the character variable cur-module and the character variable cur-suffix as arguments.

When the recursive process is executed, as shown in FIG. 7 (d), according to the change rule corresponding to the assignment suffix ".A" in the net assignment definition table TB, the p-type in the circuit design data of the module INV1 The power supply names “V _DD ” and “BV _DD ” used by the MOS are the new power supply names “DRV”
_The power supply names "V _SS " and "BV _SS " used by the n-type MOS have been changed to " _DD " and "DRV _DD ".
Changed to V _SS "," DRV _SS ", but module INV1
Since there is no instance in, it can be returned to the original processing.

When the process returns, the process returns to FIG.
The power supply name changing process for the module DF1 of the modules A1 is executed. When the power supply name changing process for the module DF1 is completed, there is no unprocessed instance in the module A1 and the process is returned to the original process. When the processing is restored, the processing returns to FIG. 7B, and the module BLK-A
Of these, the power supply name changing process for the module A2 is executed. When the power name change process for module A2 is completed, there is no unprocessed instance in module BLK-A, so the process is returned to the original process.

When the process further returns, the process returns to FIG. 7A and the power supply name changing process for the module BLK-B is executed at the highest level, but the net assign designation is made for the module BLK-B. Is performed, the power supply name in the circuit design data of the module in the lower hierarchy is changed based on the assignment suffix “.T” of the module BLK-B. Next, the power supply name changing process for the module BLK-C is executed in the highest layer, but since the net assignment is specified for the module BLK-C as well, the module names in the lower layers are lower. The power supply name in the circuit design data is changed based on the assignment suffix ".R" of the module BLK-C. When the power supply name changing process for the module BLK-C is completed, there is no unprocessed instance in the highest hierarchy, so the series of processes is completed.

As described above, the net list is generated while changing the power supply name by referring to the assigned assignment suffix. After the series of processes is completed, the net list is generated in step S221. The list is stored in the storage device 40.

Next, a case will be described in which the net assignment is specified not only for the module in the uppermost layer but also for the module A1 in the lower layer. In this case, the lower net assign designation priority setting is valid.

The operation up to changing the power supply name of the module BLK-A is the same as above, so the description thereof will be omitted.
The subsequent operation will be described. When the module A1 is detected in step S308, as shown in FIG. 8B, it is determined in step S312 that the net assignment is designated for the module A1. .D ”is stored in the character variable cur-suffix and module A1
The module name “A1” of is stored in the character variable cur-module. And this character variable cur-module and character variable cu
The power supply name change process is recursively called with r-suffix as an argument.

When the recursive processing is executed, the power supply name to be changed does not exist, so the power supply name is not changed.
As shown in FIG. 8 (c), since module A1 has two instances, module INV1 is detected first,
The contents of the character variable ass-suffix are stored in the character variable cur-suffix. Next, since it is determined that the net assignment is not specified for the module INV1, the module INV1
The module name "INV1" of INV1 is stored in the character variable cur-module. Then, the power supply name changing process is recursively called with the character variable cur-module and the character variable cur-suffix as arguments.

When the recursive process is executed, as shown in FIG. 8D, according to the change rule corresponding to the assignment suffix ".D" of the net assignment definition table TB, the p-type in the circuit design data of the module INV1 Power supply names “V _DD ” and “BV _DD ” used by MOS are new power supply names “D”
The power supply names "V _SS " and "BV _SS " used by the n-type MOS are changed to V _DD "and" DV _DD "
Although it is changed to V _SS ”and“ DV _SS ”, since there is no instance in the module INV1, it can be returned to the original process. Note that the description is omitted because the process is the same after the process is restored.

In the above description, if nothing is set in the suffix name of the module and an assign suffix is given to the suffix name, the power name is changed with reference to the given assign suffix, and the change is made. A netlist is generated based on the content, but if the suffix name of the module has already been assigned an assignment suffix and the assignment suffix is set to a new assignment suffix, the new assignment suffix will be referenced. Then, the power supply name is changed, and a netlist is generated based on the changed contents.

Further, if the assignment suffix is already given to the suffix name of the module and the assignment suffix is deleted, a netlist is generated with the power supply name set in the circuit design data of the module. To be done.

In this way, the storage device 40 in which a plurality of modules are hierarchically linked and stored is provided, and when the net assignment is designated for the module, the assignment suffix is acquired from the module and the obtained assignment suffix is acquired. The power supply name in the circuit design data of the module hierarchy and the hierarchy lower than that specified in accordance with the change rule corresponding to the above is changed. Design is done without considering the definition and definition, and in the latter half of the design, it is sufficient to change the necessary power supply name by specifying the net assignment for the module that needs power supply division. In addition to being easy, it is easy to modify and change. Further, since the power source names in the circuit design data of the modules in the layers below the layer of the module to which the net assignment is designated are collectively changed, it is possible to reduce the possibility of mistakes and oversights in the changing process. Furthermore, it is only necessary to prepare the cells on the design side for one layout, the cell library can be easily managed, and the correspondence between the design data and the layout is one-to-one, so a design error may occur. It can be reduced.

Therefore, the design work can be performed more easily, the reliability of the design can be improved, and the cell library can be managed more easily than ever before.

Further, when the net assignment is designated for a plurality of modules in different layers, the highest layer of the modules for which the net assignment is designated and the modules in the lower layers are read from the storage device 40, When changing the power supply name in the read circuit design data of each module, refer to the one assigned to the module in the closest hierarchy among those assignment suffixes when you look at the upper hierarchy from your own hierarchy. Since the processing to be performed by the lower net assign designation priority setting is enabled / disabled selectively, the power supply name in the circuit design data of the module can be finely changed.

Further, the net assignment definition table TB
Is stored in the storage device 40, the change rule is determined by the net assignment definition table TB based on the acquired assignment suffix, and the power supply name in the circuit design data of the read module is changed according to the determined change rule. Therefore, it is possible to collectively change the desired power supply names by simply defining the desired change rules in the net assignment definition table TB and giving the assign suffix as the suffix name. It is possible to easily carry out the procedure at the time of performing, and to finely change the power supply name in the circuit design data of the module.

Further, an assign suffix for instructing to change the power supply name in the circuit design data of the module is given as the suffix name of the module, and when changing the power supply name, the suffix of the module is acquired and Since the net assignment can be easily specified for the module, the design work can be further facilitated.

In the above embodiment, the power supply name in the circuit design data of the module is changed. However, the invention is not limited to this, and other parameters in the circuit design data of the module may be changed. You may comprise.

Further, in the above-described embodiments, the case where the program stored in advance in the ROM 14 is executed has been described for executing the processes shown in the flowcharts of FIGS. 3 to 5, but the present invention is not limited to this. Alternatively, the program may be read into the RAM 16 from a recording medium in which the program showing these procedures is recorded and executed.

Here, the recording medium includes a semiconductor storage medium such as RAM and ROM, a magnetic storage type storage medium such as FD and HD, an optical reading type storage medium such as CD, CDV, LD and DVD, and MO. It is a magnetic storage type / optical reading type storage medium, and includes any recording medium as long as it is a computer-readable recording medium regardless of a reading method such as electronic, magnetic, or optical.

In the above embodiment, the assignment suffix corresponds to the identifier according to claims 1 to 3 ,
The storage device 40 corresponds to the storage means described in claim 1 .

[0076]

[0077]

[0078]

[0079]

[0080]

[0081]

As described above, according to the net list generating apparatus according to the first aspect of the present invention, the design work can be performed more easily and the reliability of the design can be improved as compared with the conventional one. Therefore, it is possible to improve the efficiency and easily manage the cell library. In addition, the procedure for changing parameters
Can be performed easily, and in the circuit design data
You can make detailed changes to the parameters of
There is also an effect.

[0082]

Further, according to the netlist generating device according to the third aspect of the present invention, it is possible to obtain the effect that the procedure for changing the parameter can be performed more easily.

Further, according to the netlist generating device of the fourth aspect of the present invention, there is an effect that it can be suitably applied when changing the power supply name in the circuit design data.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a netlist generation device according to the present invention.

FIG. 2 is a diagram showing a configuration of a net assignment definition table.

FIG. 3 is a flowchart showing a process for designing and laying out a circuit.

FIG. 4 is a flowchart showing a netlist generation process.

FIG. 5 is a flowchart showing a power supply name changing process.

FIG. 6 is a diagram for explaining the operation of the embodiment.

FIG. 7 is a diagram for explaining the operation of the embodiment.

FIG. 8 is a diagram for explaining the operation of the embodiment.

[Explanation of symbols]

10 computers 12 CPU 14 ROM 16 RAM 17 VRAM 18 CRTC 29 bus 30 input device 40 storage 50 display TB net assignment definition table

Claims (4)

(57) [Claims] 1. A plurality of modules containing circuit design data necessary for designing a circuit are hierarchically linked and stored in a storage means, and a predetermined identifier is given to the module name of the module, An apparatus for generating a netlist in which circuit design data of each module are associated with each other, and an identifier acquisition unit for acquiring the identifier from the module name of the module, and a module reading unit for reading the module from the storage unit. And a parameter changing unit that collectively changes the parameters in the circuit design data of the module in the hierarchy of the module that has acquired the identifier and the hierarchy lower than that, and the storage unit. Corresponds to the type of the identifier and the change rule
The attached table is stored, and the parameter changing unit is based on the acquired identifier.
Change rules according to the table,
Circuit design data of the module based on the change rule
A netlist generation device characterized in that the parameters therein are changed . 2. The floor of the highest module of the modules given the identifier according to claim 1.
The times of the module in the layer and lower layers
When changing the parameters in the road design data,
When looking at the upper layer from the layer, among the plurality of identifiers
The one given to the module name of the closest module
And the floor of the highest module among the modules given the identifier.
The times of the module in the layer and lower layers
The parameters in the road design data are
Refer to the identifier given to the top of the modules
And a method to set any of the processing to change all at once
And the parameter changing means performs the processing based on the setting.
Or change the above parameters by any reason.
Net list producing device according to claim that you are me. 3. The module name according to claim 1 , wherein the module name includes a module name and a module suffix, and the identifier is given as the module suffix. A netlist generating device, wherein the module suffix of the module is acquired. 4. The netlist generating device according to claim 1 , wherein the parameter is a power supply name.