JPS62121579A - Functional block developing system - Google Patents

Abstract

PURPOSE:To improve a response characteristic at a high speed by converting a macro description stored within a connection generation slot to a description of low-order level, generating and storing a concrete bit of connection information than ever at a connection information slot, and developing to to a functional block. CONSTITUTION:When the hierarchical development process 4 of a fundamental functional block is performed by using the design knowledge 1 of the fundamental functional block in a logic circuit expressed with a frame and utilizing the hierarchical characteristics of the frame, a system inquires and stores a requested hierarchy level to a user. When the development process of a fundamental circuit block is performed, an acquired requested hierarchy level 9 is referred, and when a low-order template frame that becomes an object to be developed is ordered at a level lower than the requested hierarchy level, the development process following that is terminated. The development processing part 4 performs a process a bit of macro description information described or generated within a fundamental circuit block template, for calling and developing the low-order template frame. Therefore, it is possible to perform a design work with high efficiency by a non-veteran designer.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a design support system for logic circuits, and in particular,
The present invention relates to a method that makes it possible to semi-automatically design basic functional blocks such as counters and shift registers in large-scale logic circuits such as MO8LSIs with a small number of parameter inputs.

[Background of the invention]

Designing C-MO5 logic circuits is currently a very time-consuming task, and if the functional blocks are expanded all at once to the final layer using the hierarchical nature of the functional block template knowledge frame, the processing time will be enormous. It may become,
In this case, the user has to wait, and the problem arises that the design process is delayed.

On the other hand, during design work, the user does not always need the final expansion result of the functional block of interest, but often only needs the expansion result up to an intermediate level. Therefore, in order to improve the responsiveness of the system, we devised a method in which the user's desired deployment hierarchy level is registered in the system in advance, and functional blocks are deployed accordingly.

In addition, related methods of this type include:

Although there is Japanese Unexamined Patent Publication No. 59-168545, there is no consideration given to the hierarchical nature of circuit development.

Production rules convert gate-level virtual logic elements into real TTL logic elements,
Deployment was limited to those with a low functional level.

In addition, the same proponents also proposed frames and demons (additional procedures).
Lecture paper on how to develop functional blocks using , 198
2 years, 19th Automatic Design Conference (19thDesign)
Automation Conference), this method uses DDL descriptions for logical design and graphic editors for structure, and requires many users to develop from a high functional level as in this method. It is expected that intervention will be required.

[Purpose of the invention]

The purpose of the present invention is to realize a logic design support system that automatically designs basic functional blocks such as owners and shift registers in logic circuits such as C-MO3LSI by simply inputting necessary parameters. , provides a mechanism for hierarchically deploying functional blocks using frames, and exhibits high-speed responsiveness by limiting the deployment to the hierarchical level requested by the user.

[Summary of the invention]

In the present invention, the system uses the design knowledge of basic functional blocks of a logic circuit expressed by frames and uses the hierarchical nature of frames to provide a user with a hierarchical expansion process for basic functional blocks. The required hierarchy level is queried and stored, and the acquired requirement hierarchy level is referred to when performing basic circuit block expansion processing.

If the lower template frame to be expanded is at a lower level than the requested hierarchy level, further expansion processing is reduced.

By the function of ah, a group of circuit frames up to the requested hierarchical level is generated when the expansion process is completed.

[Embodiments of the invention]

An embodiment of the present invention will be described below based on the drawings.

FIG. 1 shows the basic configuration of an apparatus for implementing the present invention. 1 in the figure is the knowledge base of this system, which is used from the basic circuit block template frame group 2, which expresses the design knowledge of basic functional blocks of logic circuits in frames, and from multiple functional blocks with the same function name. It is composed of an element selection knowledge base 3 expressed in the form of a production rule for selecting only one element according to the user's request.

The expansion processing unit 4 performs processing for expanding macro description information described or generated in a basic circuit block template by calling a lower-level template frame.

The frame operation section 5 is in charge of actual access when exchanging information in slots and facets of each frame with the expansion processing section 4.

The element selection working memory section 6 is a storage device used by the production system interpreter 7.

The instance frame group base 8 is a storage device in which individual circuit frames generated by expansion processing are registered. The desired development hierarchy level storage section 9 stores the hierarchy level of the template frame desired by the user.

The terminal bag [10 is for exchanging information between the user and this system.

The duplicate frame name storage unit 11 is for registering function names when a plurality of template frames having the same function name exist.

The control unit 12 controls each processing unit as a whole.

Hereinafter, the explanation will be given according to the flow of processing shown in FIG.

First, assume that in step 101, the user specifies a shift register as a functional block desired to be developed. After that, the control unit 12
calls the corresponding template frame named "Shift Register" (102) This template frame "Shift Register" is shown in FIG. This is a type of basic circuit block template frame group 2, and it expresses C-MOS shift register design knowledge in a frame. Within this frame, the knowledge is organized by slot, facet, and value. It is given. (See P and H for frames.

In this example, the slots are the hierarchical level slot (a) of this template frame, the bit length slot slot of the shift register (c), and the connection generation slot (d). . However, at the initial stage when specifications are not input, the bit length slot slot does not exist.

However, if the user inputs the bit length, the additional procedure stored in the (b) bit length slot slot fadded facet is activated. This additional procedure is performed according to the user's input.
The bit length data of the shift register stored in the value facet of the it length slot is taken out, and the connection generation procedure stored in the value facet of the connection generation slot (d) of the same template frame is activated. (10
6) On the other hand, bit length of (C) - 1f-nee of slot C
The ded facet is activated when there is a request from the user or the expansion processing unit 4 regarding the bit length of the shift register, and there is no bit length data in the bit length slot slot rue facet. Contains additional procedures. In this example, we want the user to “
Please specify the length of the shift register. 104), and stores the value input by the user in the bij length slot slot facet. (105) Third
The value facet of the connection generation slot shown in (d) of the figure stores a procedure for configuring a shift register. In this case, b is the essential specification information of the shift register.
A basic expansion macro description shown in FIG. 4 is generated using the it length data, and a connection information slot is defined in the same frame for the macro description, and the connection information slot is stored there. FIG. 4 shows the macro description generated in case (107).

Next, if there is a multiple-choice function name in this macro description, the duplicate frame name storage unit 11 is referred to in order to respond to more detailed requests from the user.

Check whether there is a function name registered as a duplicate frame name on this macro description.

In this case, the one-overlap frame storage section is a DFF as shown in FIG. 7, but since this is not included in the macro description shown in FIG. 4, the process proceeds to step (115). Here, the first list [D
FF MS, D, 1°Q, 2. QB, ] [, MCL
K, 3] is retrieved. (115, 116) Next, a template frame having the same name as the circuit function name listed at the beginning of the list is searched.

(117) In this case, the template frame DFF
Assume that an MS exists and is shown in FIG.

Next, the temple root frame “DF” in Fig. 5 was searched.
The hierarchy level slot of "FMS" is referred to, the value 1 is read, and then that value is compared with the value stored in the desired expansion hierarchy level storage section 9. (122) In this case, the above desired Assume that the expanded hierarchy level storage unit is 2. Therefore, it is determined that the currently expanded hierarchy level is still higher than the user's desire.

The expansion processing unit 4 generates the macro description list [DFF
MS, D, 1. Q, 2. Q
B, Ko [.

MCLK, 3]. For this purpose, the node information [D, 1 . Q.

2, QB, QB, ] [, MCLK, 3], and pattern mating is applied to the node variables in the macro description for realizing the configuration method or function stored in the connection generation slot in the template frame with the same name. Assign the corresponding concrete value by checking.

In this case, the template frame DFF shown in FIG.
1.2.3 is assigned to variables -1, 4, and 3 in MS, respectively.

This template frame has external connection terminal slots other than the connection information slot.
It consists of external connection terminals such as LK and a list of node variables such as -1, 3°4, etc.

The template frame DFF MS of FIG. 6 thus materialized is assigned a serial number as an individual (instance) frame as shown in FIG. 7, and is registered as a new frame in the instance frame base 8. (124) Next, in order to expand the lower hierarchy, the expansion processing unit 4 extracts the macro stored in the connection information slot in the instantiated instance frame DFF MS 1 (FIG. 6). Start developing the description. (106, 107) In this case, the macro descriptions of the two DFFs and the inverter are developed in order, but since the function name DFF is registered in the duplicate frame name table in Figure 7, there are multiple template frames in OFF. It turns out that it exists. (
108) Therefore, the expansion processing unit 4 traces the family frames and refers to the option specification slot of the template frame "shift register" in order to request the element selection knowledge base 3 to select the most suitable FF template. (109) In this case, since nothing is stored in the value facet of the option specification slot of the template frame shift register'' in FIG. 3 (110), the 1fneeded facet (e) of the option specification slot is
The additional procedure stored in the program is activated and outputs to the user the message "Please enter parameters such as high speed, low power consumption, reduced number of elements, with reset, etc." on the terminal (111).
Prompt the user to enter a value. Here, if the user inputs [with reset], (112) the expansion processing unit selects this option specification [with reset], the template frame name DFFMS currently being expanded, and the DFF with the selected function name. data is transferred to the working storage section 6. Thereafter, the production system interpreter performs pattern matching with the element selection knowledge group expressed by the production rule as shown in FIG. 8, and executes the t h a n part of the matching rule. (113) In this case, Rule 2 of (b) is applicable, and the function name DFF in the macro description of the template frame DFF MS is
are all rewritten to DFF TYPE2 (11
4), here the template frame DFF TYPE
2 is one of a plurality of DFF template frames as shown in FIG. 9(b), and has a reset function.

Next, the expansion processing unit 4 converts the frame “D F FM
The first list of the macro description list group stored in the connection information slot in "SI" [DFF-TYPE 2.D
, 1. Q, 100. QB,] [.

CLKI, 3]. (116) Next, the value of the layer level slot of the same frame is checked (122)
, the user's desired expansion hierarchy level stored in the desired hierarchy level storage unit 9 is 2 as shown in FIG.
2'' has the value 2 in the value facet of the lv layer level 2 slot, it is determined that expansion is still necessary, and the process proceeds to step (123).

Here, similarly, the template frame "DFF TYPE2" of FIG. 9(b) is called, and the node information [D] in the upper list in the macro description is called.

1, Q, 100. QB, ] [, CLKI,
3] and the template frame “DFF” selected above.
External connection terminal of TYPE 2'' is matched with the node variable and the value of the node variable is assigned. (123) , --, By F Template frame D F F
TYPE2 is registered as an individual frame in the instance frame base 8 as a new frame with a serial number as shown in FIG. 10(a). (124) Thereafter, the expansion processing unit attempts to further expand the macro description in FIG.
Returning to step 8), the hierarchy level of the template frames corresponding to the macro description in FIG. 10(a) are all 3, so no expansion is performed after all.

The expansion processing unit 4 then expands the second macro description list roFF, D in FIG. 6, which is the next expansion target.

Zoo, Q, 2. QB, Ko [, CL
KI, 101 is expanded, and an individual frame DFF-TYPE 2 2 of DFF TYPE 2 shown in FIG. 10(b) is generated in the same manner as above and registered in the instance frame base 8. In this case as well, no further expansion of the macro description is performed.

Third macro description list [I NV, 3, 101
1, as shown in FIG. 9(c), since the value of the hierarchical level slot of the template frame INV is already 3, no further expansion is performed.

If the user's desired expansion hierarchy level extends to a lower description level such as 3rd or 4th, similar expansion processing is continued up to the template frame at the desired hierarchy level.

At this stage, among the macro descriptions of the shift register shown in FIG. 9, the first [DFF MS, D, 1°Q, 2. QB
, ] [, MCLK, the expansion of 3 pieces is completed, and then [C0
NNECTED, 2, 4], but since the corresponding template frame does not exist, it is not expanded (116, 117° 118), and then the third [C0N
NECTED.

3.6], but this is also not expanded.

(119, 116, 117, 118).

Next, the fourth [DFF MS, D, 4', Q, 5°Q
The expansion of B, ko[, MCLK, and 6 is performed by the process explained above in the same way as the expansion of the first list.

Then, such processing is continued for all macro description lists of the shift register shown in FIG. 4, and the expansion processing ends (120).

The individualized frame generated by this series of expansion processing is expressed in this structure as shown in FIG. 11.

According to this embodiment, the connection information of the shift registers expanded and generated is stored in the instance frame base 8 as a network of individualized frames, and if you want to extract only the connection information from that, you can use the connection information of all individualized frames. The connection information stored in the value facet of the slot is collected, the macro description list having the same function name as the name of the template frame belonging to the level higher than the desired expansion hierarchy level is deleted, and outputted on the terminal 10.

〔Effect of the invention〕

According to the present invention, the design of basic circuit functional blocks such as counters and shift registers can be dramatically reduced in the design work of logic circuits, which conventionally relied on acquisition, and design knowledge can be stored in the computer. This makes it easy to pass on the knowledge, and even non-veteran designers without detailed specialized knowledge can carry out highly efficient design work. especially,
By limiting the expansion to the necessary levels, the system's responsiveness increases and design thinking is less likely to be interrupted. Also, with advances in semiconductor technology,
Even if a change occurs in element technology, design knowledge is expressed hierarchically using frames, so this can be handled by simply changing the template frame at the lowest device level.

[Brief explanation of drawings]

FIG. 1 is a basic configuration diagram of an embodiment of the present invention, FIG. 2 is a processing flowchart, FIG. 3 is a diagram showing an example of hierarchical level slots of a frame, FIG. 4 is a diagram showing an example of macro instructions, and FIG. 5 shows an example of a template frame, FIGS. 6 and 7 show an example of an instance frame, FIG. 8 shows an example of a rule, and FIGS. 9(a), (b), ( c) is a diagram showing an example of a template frame; FIG. 10(a); (b) is a diagram showing an example of the hierarchical structure of the template frame, and FIG. 11 is a diagram showing an example of this structural representation. Agent Patent Attorney Katsuo Ogawa -11' Kaya 71! 1 4th concave 5th concave 7th (2I Fig. 13 Mac O Hon Otsujo Pi'$11

Claims (1)

[Claims] 1. A connection generation slot in which information describing a general generation procedure of internal connection information of functional blocks of a logic circuit in a macro is stored, and the macro description is expanded to lower level connection information. A frame consisting of a specification slot that stores specification information necessary for this, an expansion processing unit that performs this expansion processing, and a connection information slot that stores the connection information of the lower level generated by the expansion. is used as a template knowledge frame for designing the functional block, and stores the specification information necessary for materializing the functional block collected by asking questions to the user in the specification slot; generating more specific connection information by converting the macro description stored in the connection generation slot into the lower level description with reference to the connection generation slot, and storing the generated connection information in the connection information slot; Therefore, a functional block expansion method is characterized in that the functional blocks are expanded. 2. In claim 1, the function block is improved by including a pointer for referencing another template knowledge frame in the lower level description stored in the connection information slot. A function block deployment method that performs layered deployment processing. 3. In claim 2, the hierarchical expansion process is performed by specifying in advance the usable hierarchical levels of the template knowledge frame used for the expansion process or storing them in response to a question from the system. A functional block expansion method is characterized in that a design solution description level obtained by can be specified as appropriate.