JP2002056041A - Method for reflecting hardware description language hierarchy information - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make accurately and efficiently performable the preparation and change operations of the HDL(Hardware Description Language) file and to make effectively utilizable the resource of the HDL file. SOLUTION: An input-output controlling part 2 reads the external file (HDL file) 1 to be an origin to a device and expands the external file on a storing part 6, and a controlling part 4 displays the automatic generation of an upper hierarchical HDL and the port change contents of the hierarchical HDL on a displaying part 3 on the basis of port information extracted from the HDL file, reflects the automatic generation and the port change contents on a related hierarchical file and stores the related hierarchical file in a file storing part 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an HDL (Hardware)
The present invention relates to a method of reflecting hierarchical information, and more particularly to a method of reflecting HDL hierarchical information suitable for editing a file created in HDL used for designing a logic circuit of an electric circuit.

[0002]

2. Description of the Related Art In recent years, as one of efficient logic circuit design techniques, a method of describing an HDL file using HDL and performing logic verification and logic synthesis has been used. When a design method using HDL is executed, the HD
The readability of L and the processing speed at the time of performing logic synthesis on HDL greatly affect the subsequent steps.

For example, if an HDL file that has already been described is long, the internal context of the HDL file becomes complicated at the time of logic verification, and the readability of HDL deteriorates because the related description extends over a wide range. As a result, there arises a problem that the working efficiency is reduced. Also,
In the case described above, a large amount of storage area is required for the logic synthesis device that performs the logic synthesis, and as a result, the time required for the logic synthesis becomes extremely long, or the synthesis may not be completed to the end. It also creates problems.

As a countermeasure for avoiding the above-mentioned problems, a method of creating a lower layer file in which an HDL description unit is divided into a plurality of units in advance while maintaining a logically equivalent state is used. In this method, logic verification and logic synthesis are performed on the lower hierarchical file created by division, and an upper hierarchical file is created by finally managing the divided HDL files.

In the above-described method according to the prior art, in order to create an upper layer, it is necessary to manually construct a hierarchical relationship while referring to the specification of the lower layer file. When changing the port name, it is necessary to first change the port name of the lower layer file and create an upper layer.

[0006]

The above-described method of creating an upper-layer file according to the prior art requires the operator to manually create the upper-layer file while referring to the specifications of the lower-layer file. Requires, and
There is a problem that a description error may be mixed in the generated upper layer file.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art, to make it possible to accurately and efficiently create an upper-layer file, and to make effective use of HDL file assets. An object of the present invention is to provide a method for reflecting hierarchical information.

[0008]

According to the present invention, an object of the present invention is to provide a hardware description language hierarchy information reflection method for performing a logic design of a logic circuit hierarchically described using a hardware description language. This is achieved by extracting port information of logic and generating a file of upper layer logic according to a hardware description language grammar based on a description defining connection information of lower layer logic.

More specifically, the present invention reads a plurality of lower-layer files described in HDL, reads port names, input / output attributes, type attributes, Vector widths, and lower-layer names from the lower-layer files as layer port information. Is extracted, and the Po for each lower layer is extracted from the port name and the input / output attribute.
Using the rt connection relation as a connection pointer, a component statement as a lower layer component is created, components are connected by each port name and the connection pointer, and an upper layer HDL is generated according to the HDL grammar.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of an HDL editing apparatus using an HDL layer information reflecting method according to the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an HDL using one embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration of the editing apparatus, FIG. 2 is a diagram for explaining an example of a hierarchical structure of the logic circuit, FIG. 3 is a diagram showing an example of HDL description of an upper hierarchy of the logic circuit shown in FIG. 2, and FIG. FIG. 5 is a diagram illustrating an HDL description example of a lower hierarchy of the logic circuit illustrated, FIG. 5 is a diagram illustrating a table of hierarchy port information extracted from a lower hierarchy file by processing according to the embodiment of the present invention, and FIG.
FIG. 7 is a diagram illustrating a tree of each layer and a table of repeat information extracted from a lower layer file by the processing according to the embodiment of the present invention. FIG. 7 is a diagram illustrating an example of connection information description of lower layer logic defined by an operator. is there. In FIG. 1, 1 is an external file, 2 is an input / output control unit, 3 is a display unit, 4 is a control unit, 5 is a file storage unit, and 6 is a storage unit.

The HDL editing apparatus shown in FIG. 1 includes an external file 1, an input / output control unit 2, a display unit 3, a control unit 4,
It comprises a file storage unit 5 and a storage unit 6. The HDL layer information reflection method according to the embodiment of the present invention is executed by the input / output control unit 2, the display unit 3, the control unit 4, the file storage unit 5, and the storage unit 6.

The input lower layer file is stored in the external file 1 and is read from the input / output control unit 2. The contents are stored in the file storage unit 5 and are also expanded in the storage unit 6. The control unit 4 extracts hierarchical port information of the lower hierarchical file developed on the storage unit 6 and displays the extracted information on the display unit 3. The upper layer file generated based on the file is stored in the file storage unit 5. The operator can retrieve the upper layer file as an external file 1 from the file storage unit 5 through the input / output control unit 2 as necessary.

Next, an example of a hierarchical structure of a logic circuit to be handled according to the embodiment of the present invention and an example of description in HDL will be described with reference to FIGS.

The logic circuit shown in FIG. 2 is composed of two lower layers (UNDER_1, UNDER_2) and an upper layer (TOP) obtained by integrating these lower layers. Each lower layer is composed of a detailed logical structure of the circuit and input / output signals, and the upper layer is composed of blocks of lower layer names and input / output signals. When such a logic circuit of the example shown in FIG. 2 is described in HDL, the description of the upper layer is as shown in FIG. 3, and the description of the lower layer is
As shown in FIG.

In the processing to be described later of the embodiment of the present invention, layer port information, and tree and repeat information of each layer are extracted from a lower layer file described and stored in HDL as shown in FIG. . The extracted layer port information is, as shown in FIG.
port name 11 as ort information and input / output attribute 12
, A type attribute 13, a Vector width 14, and a hierarchy name 15. As shown in FIG. 6A, the tree and repeat information of each layer to be extracted include a layer name 21, an upper layer number 22, an upper layer name 23, a lower layer number 24, a lower layer number 24, and a lower layer number 24. The hierarchy name 25 and the number of repeats 26 are shown.

The connection information of the lower hierarchy logic shown in FIG. 7 is defined in advance by the operator as a port connection between the lower hierarchy and the upper hierarchy, and is referred to in the process of creating the upper hierarchy file from the lower hierarchy file. . However, if it is not defined as the connection information, the lower-level por
The t name is used as connection information in the upper hierarchy.

FIG. 8 is a flowchart for explaining a process of creating an upper layer file from a lower layer file.
Hereinafter, this will be described.

(1) First, the lower layer file described as shown in FIG. 4 is read from the external file 1 via the input / output control unit 2 and is stored in the file storage unit 5 and is stored in the storage unit 6 It is developed so that the control unit 4 can handle it freely (step S31).

(2) Next, the control unit 4 searches for a port description in the lower hierarchical file and extracts port information. The extracted layer port information is the information described with reference to FIG. 5A. In the case of the example of the lower layer file described with reference to FIG. 4, specifically, the extracted layer port information is extracted as shown in FIG. Is done. These pieces of information are registered in the port information table of the storage unit 6 (Step S32,
S33).

(3) The control unit 4 searches the hierarchical description in the lower hierarchical file and extracts the tree and repeat information as the hierarchical information described with reference to FIG. In the case of the example of the lower layer file described with reference to FIG. 4, specifically, the file is extracted as shown in FIG. 6B.
These pieces of information are registered in the tree and repeat information table of the storage unit 6 (Step S34).

(4) It is determined whether or not all lower layer files have been read and the processing up to step S34 has been completed. If lower layer files still remain, the processing from step S31 is repeated. If reading of all lower layer files has been completed, the control unit 4 proceeds to FIG.
Refer to the connection information of the lower hierarchy logic shown in FIG.
Based on the port name of the input / output attribute of the t information based on the port name of the OUT attribute, a search is performed to determine whether or not a port name having another input / output attribute of the IN attribute or the INOUT attribute is present. Register in 6. In the case of the example of the lower hierarchical file described with reference to FIG. 4, specifically, as shown in FIG. 6B, only two connection pointers 16 are registered (steps S35 and S36).

(5) A net check is performed to determine whether each connection relationship is normal, and the result is displayed on the display unit 3.
If an error has occurred in the result of the net check, the process ends without performing the subsequent processes (steps S37 and S38).

(6) If the result of the net check in step S38 is normal, the control unit 4 determines, based on the hierarchical names of the tree and the repeat information, a component statement as a lower hierarchical component as a higher hierarchical file. HDL
(Step S39).

(7) Further, the control unit 4 uses the signal name and the layer name of the layer port information and the connection pointer to execute each c.
A component description is created according to the HDL grammar, and an upper layer file is created. In the case of the example of the lower layer file described with reference to FIG. 4, specifically, an upper layer file described as shown in FIG. 3 is created, and this file is stored and saved in the file storage unit 5. (Step S40).

FIG. 9 is a flowchart for explaining a process for reflecting the change in the lower layer file when the connection description of each component of the upper layer file generated by the process described with reference to FIG. 8 is changed. Will be described.

(1) First, the control unit 4 reads the upper layer file stored in the file storage unit 5 and develops it in the storage unit 6 so that the control unit 4 can handle it freely (step S41). ).

(2) Next, the control unit 4 reads the p from the upper layer file read into the storage unit 6 to the lower layer.
The port information is retrieved by searching the ort connection description, and it is compared whether or not the extracted port information matches the port name of the hierarchical port information table created by the processing described with reference to FIG. 8 (steps S43 and S44). .

(3) As a result of the comparison in step S44, it is determined whether or not the extracted port name exists in the hierarchical port information table. If the port name does not exist, the port is regarded as a changed port and extracted. The connection information of the port and the connection pointer of the hierarchical port information table are compared to extract a matching change source port (steps S45 and S46).

(4) Then, the control unit 4 sets the extracted po
Based on the rt hierarchy name, the lower hierarchy to be changed is narrowed down by the upper hierarchy name and lower hierarchy name of the tree and repeat information, and the number of repeats, and the changed port name and the lower hierarchy to be changed are stored in the storage unit 6 (steps S47 and S48). ).

(5) If the extracted port name exists in the hierarchical port information table after the processing in step S48 or in the determination in step S45, the control unit 4
Checks whether or not extraction of all port information is completed. If there is any remaining port information, step S43 is performed.
Are repeated (step S42).

(6) In step S42, all p
When the extraction of the ort information has been completed, the lower hierarchy to be changed is read, the corresponding port location is displayed on a text editor or a schematic editor, and the operator is asked whether or not to perform the automatic change (step S4).
9).

(7) As a response from the operator in response to the inquiry in step S49, it is checked whether or not automatic change has been selected, and if automatic change has not been selected,
If the process is terminated without performing the subsequent processes and the automatic change is selected, the corresponding port name is changed and the contents of the hierarchical port information table are updated (step S).
50 to S52).

FIG. 10 is a flowchart for explaining a process of reflecting the change in the upper layer file when the port connection description of the lower layer of the upper layer file generated by the process described with reference to FIG. 8 is changed.
This will be described.

(1) First, the control unit 4 reads the lower layer file stored in the file storage unit 5 and develops it in the storage unit 6 so that the control unit 4 can handle it freely (step S61). ).

(2) Next, the control unit 4 searches for a port connection description in the hierarchy from the lower hierarchy file read into the storage unit 6, extracts port information, and extracts the extracted po.
The rt information is the hierarchy p created by the process described with reference to FIG.
It is determined whether or not the port name matches the port name in the ort information table (steps S63 and S64).

(3) As a result of the comparison in step S64, it is determined whether or not the extracted port name exists in the hierarchical port information table. If the port name does not exist, the port is regarded as the changed port and extracted. The connection information of the extracted port and the layer port information in the layer port information table are compared to extract a matching change source port (steps S65 and S66).

(4) Then, the control unit 4 sets the extracted po
Based on the rt hierarchy name, the upper hierarchy to be changed is narrowed down by the upper hierarchy name and lower hierarchy name of the tree and repeat information and the number of repeats, and the changed port name and the upper hierarchy to be changed are stored in the storage unit 6 (steps S67 and S68). ).

(5) After the processing in step S68 or in the determination in step S65, if the extracted port name exists in the hierarchical port information table, the control unit 4
Checks whether extraction of all port information has been completed, and if there is any remaining port information, determines in step S63
Are repeated (step S62).

(6) By checking in step S62, all p
If the extraction of the ort information has been completed, the upper hierarchy to be changed is read, the corresponding port location is displayed on a text editor or a schematic editor, and the operator is asked whether or not to perform the automatic change (step S6).
9).

(7) It is checked whether or not automatic change has been selected as a response from the operator in response to the inquiry in step S69, and if automatic change has not been selected,
If the process is terminated here and the automatic change is selected without performing the subsequent processes, the corresponding port name is changed and the contents of the upper layer port information are also updated (step S70).
To S72).

As described above, according to the embodiment of the present invention, the original external file (HDL file) 1 is read into the device by the input / output control unit 2, expanded on the storage unit 6, and 4 generates an upper hierarchical file and, when the port connection description of the hierarchical file is changed, displays the changed content on the display unit 3 and reflects the change to the related hierarchical file and saves it in the file storage unit 5. Therefore, the hierarchical file creation operation can be performed accurately and efficiently, and the HDL file assets can be effectively used.

[0043]

As described above, according to the present invention, an upper hierarchical file can be automatically generated from a lower hierarchical file, and a change in the connection description of the hierarchical file is automatically reflected on the associated hierarchical HDL. Therefore, the creation and modification of the HDL file can be performed accurately and efficiently, and the resources of the HDL file can be effectively used.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an HDL editing device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of a hierarchical structure of a logic circuit.

FIG. 3 is a diagram illustrating an example of an HDL description of an upper layer of the logic circuit illustrated in FIG. 2;

FIG. 4 is a diagram illustrating an example of an HDL description of a lower hierarchy of the logic circuit illustrated in FIG. 2;

FIG. 5 is a diagram illustrating a table of hierarchical port information extracted from a lower hierarchical file by a process according to the embodiment of the present invention.

FIG. 6 is a diagram illustrating a tree of each layer and a table of repeat information extracted from a lower layer file by the processing according to the embodiment of the present invention.

FIG. 7 is a diagram showing an example of connection information description of lower-level logic defined by an operator.

FIG. 8 is a flowchart illustrating a process of creating an upper layer file from a lower layer file.

FIG. 9 is a flowchart illustrating a process in which, when the connection description of each component of the upper layer file is changed, the change is reflected in the lower layer file.

FIG. 10 is a flowchart illustrating a process in which, when a port connection description of a lower layer of an upper layer file is changed, the change is reflected in the upper layer file.

[Explanation of symbols]

 Reference Signs List 1 external file 2 input / output control unit 3 display unit 4 control unit 5 file storage unit 6 storage unit

Claims (4)

[Claims] 1. A hardware description language hierarchy information reflection method for designing a logic circuit hierarchically described by using a hardware description language, the method comprising:
A hardware description language hierarchy information reflection method characterized by extracting t information and generating a file of an upper hierarchy logic according to a hardware description language grammar based on a description defining connection information of a lower hierarchy logic. 2. The hardware according to claim 1, wherein when there is no connection information in the description defining the connection information of the lower layer logic, the port name of the lower layer logic is used as the connection information of the upper layer logic. How to reflect the hardware description language hierarchy information. 3. The method according to claim 1, further comprising a step of reading a lower layer file describing the lower layer logic and extracting a tree and repeat information of each layer. 4. When the connection port information between the layers of an upper layer file describing an upper layer logic generated from a lower layer file describing the lower layer logic is changed, the extracted layer port information and 4. The hardware description language hierarchy information reflection method according to claim 3, wherein a port name between the corresponding hierarchies is extracted from the hierarchy tree and the repeat information.