JPH0442371A - Logic simulation method - Google Patents

Abstract

PURPOSE:To reduce the capacity of a file by reproducing a signal change at arbitrary time and at an arbitrary point without preserving all the signal changes. CONSTITUTION:Circuit data structure is prepared by inputting the network list of a simulation object circuit [a figure (a)] including logic elements 21-28. Since only the signal changes of signals A-C and K, for example, are outputted and stored when it is necessary to newly execute simulation, addresses to signal change data are stored only for the pointers of A-C and K in a signal change table and concerning the other signals, however, the state in NULL. Then, in a simulation step, the simulation is executed based on a partial circuit data and the signal change data and since the desired signal change data is obtained, the signal change can be referred to at arbitrary time and at the arbitrary place even without preserving all the signal change data. Thus, the capacity of the file can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to logic simulation of large-scale integrated circuits, etc., and particularly relates to a method for reducing the file capacity required during logic verification.

[Conventional technology]

A conventional logic simulation method is to "save all signal changes of signal lines that are referenced or may be referenced."

FIG. 8 is a block diagram of a conventional logic verification system, in which a logic simulator performs simulation and outputs a signal change file. Next, the waveform display program or text format signal change output program is
Based on the output signal changes, the signal changes are shown to the designer.

In a system with such a configuration, the signal line whose signal change is to be stored is specified in advance by a simulation command. Next, if a signal change occurs on the designated signal line during the simulation, this signal change is stored.

Then, based on this result, the signal change related to the signal line specified by the user is referred to in waveform display or text format.

[Problem to be solved by the invention]

In the conventional logic simulation method described above, it is difficult to predict all the referenced signals in advance during logic verification, and the file becomes huge if signal changes of all signal lines are stored. In addition, there was a problem that the simulation was slow due to the output operation.

The present invention has been made in view of these points, and its purpose is to provide a logical simulation in which signal changes at any time and place can be referenced after simulation without the signal change file becoming huge. It's about getting the environment.

[Means to solve the problem]

In order to achieve such an object, the present invention provides signal lines, flip-flops, latches, ROMs, R
A first simulating means for outputting a signal change in an output signal of an element having a memory function such as an AM, a first storing means for storing a signal identification name and signal change data as a pair, and a circuit network. a second storage means; an input means for manually inputting a signal identifier specifying desired data to be displayed; and a first search for searching for a signal from within the first storage means for the signal identifier input by the input means. and a second search means for extracting a partial circuit necessary for reproducing the signal change of the signal identification name and searching for the input signal of the partial circuit if the desired data is not found in the search by the first search means. a second simulating means for re-simulating based on the partial circuit and signal change extracted by the second retrieval means; and a second simulating means for re-simulating the signal change reproduced by the second simulating means. A registration means for registering in the first storage means is provided.

[Effect]

In the logic simulation method according to the present invention, the first
During the simulation, the signal changes of the output signals of the signal lines, flip-flops, latches, ROMs, RAMs, and other devices with storage functions specified by the user are output to a file, and this file is input after the first simulation. Accordingly, the signal change data is stored in the first storage means, in the first input step, a signal identifier for which the signal change is to be displayed is input, and in the first search step, the signal change data is specified by the input signal identifier. When the desired data is retrieved from among the data in the first storage means and the desired data is not present in the first storage means, in the second retrieval step, the partial circuit required to restore the desired data is The signal change data that is extracted and input to this partial circuit is searched, and in the simulation step, simulation is performed based on the partial circuit data and signal change data to obtain the desired signal change data, so all signal change data is extracted. You can refer to signal changes at any time and any location without having to save the data.

〔Example〕

FIGS. 1, 2, 5, and 3 are block diagrams, table diagrams, and structural diagrams for explaining one embodiment of the logic simulation method according to the present invention. Note that hereinafter, the first storage means will be referred to as a signal change table, and the second storage means will be referred to as a circuit data structure.

The signal change table shown in FIG. 2 has a signal identification name, a pointer to signal value change information, and a pointer to the corresponding signal table of the circuit data structure.

Note that for signal lines for which no signal changes are stored, the pointer to the signal table is empty (NULL).

The circuit data structure shown in FIG. 3(a) and (bl) has a table for each element and signal line, and these are connected by bidirectional pointers to reflect the circuit diagram.The signal table is It has a pointer that holds the address to the corresponding signal identifier record in the signal change table and a flag that indicates the re-simulation target partial circuit range.

In a system having such a configuration, the signal change history is displayed based on the flowcharts shown in FIGS. 4, 5, and 6. First, a netlist file is read and a circuit data structure is created (step 1). Next, if a new simulation needs to be executed, step 2 is executed. If existing simulation results are to be used, proceed to step 3. In step 2, a simulation is executed based on the simulation command, and signal changes in the signal line specified by the user and the output signal line of the element having the storage function are output to a signal change file. Then proceed to step 3. Step 3
Now, input the signal change file and create a signal change table. Then, in step 4 of FIG. 5 in step A, a signal identifier to be displayed is input, and in step 5, a search for a signal change is performed. Here, if a signal change is detected, the process proceeds to step 12 in FIG. 4; otherwise, the process proceeds to step B, step 6 in FIG. In step 6, the data structure of the logic circuit is traced and the target is shifted to the element that is outputting this signal. Next, the processing from step 7 onwards is performed on all the signals input to this element. In step 7, a search is made to see if the signal change of this signal is stored. Here, if the information is stored, the process proceeds to step 8, and if it is not stored, the process proceeds to step 9. In step 8, this signal change data is registered as an event. In step 9, a simulation target flag is set, and steps 6 to 9 are recursively performed. When all processes from step 6 to step 9 are completed, the process proceeds to step 10 in FIG. 5. 7 fb] is a circuit obtained by extracting a partial circuit necessary for restoring the signal change of the signal line J. In step 10, a simulation is performed on the partial circuit for which the simulation target flag is set. In step 11, each signal change of the simulated partial circuit is newly registered in the signal change table and used for future reference of signal values. In step 12, the desired signal change is displayed in a waveform.

FIG. 7(a) shows a part of the circuit to be simulated. In FIG. 7 (a+ and (b), 21 to 28 are logic elements.
The flowcharts shown in FIGS. 4 to 6 will be explained based on FIG. In step 1, the netlist of the target circuit (FIG. 7(a)) is input and a circuit data structure is created.

If a new simulation needs to be executed, step 2 is executed. However, in order to speed up the simulation and reduce file size, in this example, signals A, B,
Assume that a signal change is output only to C. Step 3
Now, input the simulation result file and create a signal change table (FIG. 7(C)). Here, since signal changes are stored only in signals A, B, and C1,
Only pointers A, B, C, and K in the signal change table store addresses to signal change data, but
Other signals are NULL.

Next, proceed to step 4, and input the name of the signal whose waveform you want to display. Here, the case where J is input will be explained. In step 5, the signal change table is searched for signal name J. Specifically, it looks at the J column of the signal change table and returns a pointer to the signal change table. If the value of this pointer is not NILL, the process proceeds to step 12, and if it is NULL, the process proceeds to step 6.

In step 6, attention is paid to the element outputting the signal J, that is, the element 27, as the current element.

All input signals to element 27 (F.

Steps 7 to 9 are performed for G).

The signal F will be explained. In step 7, the signal change table is searched for signal F. Since the corresponding pointer of signal F is NULL, the process moves to step 8. In step 8, the table of signal F of the circuit data structure (Fig. 3)
flag to indicate that it is a simulation area. Next, regarding the current signal F, a partial circuit extraction routine is executed. That is, the process moves to step 6. Step 6
Here, the output element 23 for the signal F is assumed to be a current element.

Then, the processes of steps 7 to 9 are performed on all input signals (AB, C) of the element 23.

Next, signal A will be explained. In step 7, the signal change table is searched for signal A. Since the corresponding pointer of signal A is not NULL, the process moves to step 9, and the signal change data to the signal is registered in the logic simulator as an event.

Next, signal B will be explained. In step 7, the signal change table is searched for signal B. Since the corresponding pointer of signal B is not NULL, the process moves to step 9, and the signal change data of signal B is registered as an event in the logic simulator.

Next, signal C will be explained. In step 7, the signal change table is searched for signal C. Since the corresponding pointer of signal C is not NULL, move to step 9.
Signal change data of signal C is registered as an event in the logic simulator.

This completes the partial circuit extraction routine with element 23 as the current element, returns to the partial circuit extraction routine with element 27 as the current element, and processes steps 7 to 9 regarding signal G in the same manner.

When the processing of the partial circuit extraction routine regarding signals F and G is completed, the process moves to step 10. FIG. 7 (The extracted partial circuit of bl is the partial circuit with the flag set.
A becomes the input of this partial circuit.

For B, C, and K, signal changes have already been registered as events in the simulator.

In step 10, a simulation is performed on this partial circuit. Obtain the signal change of signal J.

In step 11, the signal change obtained in step 10 is registered in the signal change table. That is, a non-NULL value is entered in the corresponding pointer of the signal J in the signal change table. Then, in step 12, the signal change is displayed in a waveform.

〔Effect of the invention〕

As explained above, the present invention reproduces signal changes at any time and at any point without saving all signal changes, so there is no need to store signal changes for all signals, so it is possible to save files. This has the advantage that the capacitance can be reduced, and since re-simulation is required only for related partial circuits, signal changes can be reproduced at high speed.

[Brief explanation of the drawing]

Fig. 1 is a block diagram for explaining the logic simulation method according to the present invention, Fig. 2 is a table diagram showing a signal change table, Fig. 3 is a structural diagram showing a circuit data structure, and Figs. 4 to 6 are A flowchart for explaining an embodiment of the logical simulation method according to the present invention, FIG. 7(a),
(bl and fc) are a circuit diagram and a table diagram for explaining partial circuit extraction, and FIG. 8 is a system configuration diagram for explaining a conventional method.

Claims (1)

[Claims] Signal lines, flip-flops, latches,
A first simulating means for outputting a signal change in an output signal of an element having a memory function such as a ROM or a RAM; a first storing means for storing a signal identification name and signal change data in pairs; and a circuit network. a second storage means for storing; an input means for inputting a signal identifier specifying desired data to be displayed;
a first search means for searching for a signal from within the storage means; and a partial circuit required to reproduce the signal change of the signal identification name if the desired data is not found in the search by the first search means; a second search means for extracting and searching for an input signal of the partial circuit; a second simulating means for resimulating based on the partial circuit and signal change extracted by the second search means; and registration means for registering the signal change reproduced by the second simulating means in the first storage means, and is capable of reproducing signal changes at any time and at any point without storing all signal changes. Characteristic logical simulation method.