JPH0786407A - Multilayered wiring method of integrated circuit - Google Patents
Multilayered wiring method of integrated circuitInfo
- Publication number
- JPH0786407A JPH0786407A JP22477393A JP22477393A JPH0786407A JP H0786407 A JPH0786407 A JP H0786407A JP 22477393 A JP22477393 A JP 22477393A JP 22477393 A JP22477393 A JP 22477393A JP H0786407 A JPH0786407 A JP H0786407A
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- Prior art keywords
- wiring
- integrated circuit
- layer
- layers
- multilayer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は集積回路のチップレイア
ウト方法に係り、特に、多層配線を行う集積回路におい
て、各配線層を有効に使用することにより集積回路のレ
イアウトにおける配線効率を向上させた、また配線距離
を短くし得る集積回路の多層配線方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip layout method for an integrated circuit, and more particularly, in an integrated circuit having multi-layer wiring, the wiring efficiency in the layout of the integrated circuit is improved by effectively using each wiring layer. The present invention also relates to a multilayer wiring method of an integrated circuit that can shorten the wiring distance.
【０００２】近年のＬＳＩは、高集積化に伴うチップの
大規模化により、配線層の多層化が進んでいる。そのた
め、配線層の多層化に伴う効率的な配線手法を確立させ
る必要がある。[0002] In recent LSIs, the wiring layers have become multi-layered due to the increase in the scale of chips accompanying the high integration. Therefore, it is necessary to establish an efficient wiring method with the increase in the number of wiring layers.
【０００３】[0003]
【従来の技術】従来の半導体集積回路においては、垂直
に交差する縦横の２方向をメイン配線方向としてレイア
ウトが行われている。ここで、メイン配線方向というの
は、基本的に各配線層に対して決められる配線方向のこ
とを言い、各配線層の配線方向は完全に１方向ではな
く、部分的には（配線が混雑している部分等では）異な
る方向にも配線がなされるのが一般的である。2. Description of the Related Art In a conventional semiconductor integrated circuit, layout is performed with two vertical and horizontal directions intersecting vertically as main wiring directions. Here, the main wiring direction means a wiring direction basically determined for each wiring layer, and the wiring direction of each wiring layer is not completely one direction but partially (wiring is crowded). It is general that the wiring is made in different directions (for example, in the portion where it is formed).
【０００４】例えば３層配線の場合には、図５（ａ）及
び（ｂ）に示すように、第１層目Ｌ１１と第２層目Ｌ１
２が垂直に交差するような配線方向Ｒ１１及びＲ１２を
メインの配線方向とし、更に、第２層目Ｌ１２と第３層
目Ｌ１３が垂直に交差するような配線方向Ｒ１２及びＲ
１１をメインの配線方向としていた。結果として、第１
層目Ｌ１１と第３層目Ｌ１３が同じ方向をメインの配線
方向Ｒ１１とすることとなる。このような場合に、第１
層目Ｌ１１及び第２層目Ｌ１２を基本的な配線に使用し
て、第３層目Ｌ１３を混雑している部分について補助的
に使用することが多かった。For example, in the case of a three-layer wiring, as shown in FIGS. 5A and 5B, the first layer L11 and the second layer L1
The wiring directions R11 and R12 in which 2 vertically intersects are the main wiring directions, and further, the wiring directions R12 and R12 in which the second layer L12 and the third layer L13 vertically intersect.
11 was the main wiring direction. As a result, the first
The same direction of the layer L11 and the third layer L13 is the main wiring direction R11. In such cases, the first
In many cases, the layer L11 and the second layer L12 are used for basic wiring, and the third layer L13 is used as a supplement for a congested portion.
【０００５】[0005]
【発明が解決しようとする課題】従って、従来の多層配
線を行う集積回路では、各配線層、特に第３層目以降の
配線層における配線は、該配線層を有効に使用しておら
ず、レイアウトの配線効率が悪いという問題があった。Therefore, in the conventional integrated circuit for multi-layer wiring, the wiring layers, particularly the wirings in the third and subsequent wiring layers, do not effectively use the wiring layers. There was a problem that the wiring efficiency of the layout was poor.
【０００６】本発明は、上記問題点を解決するもので、
多層配線を行う集積回路において、各配線層を有効に使
用することにより、集積回路のレイアウトにおける配線
効率を向上させ、且つ配線距離の短い集積回路の多層配
線方法を提供することを目的とする。The present invention solves the above problems.
It is an object of the present invention to provide a multilayer wiring method for an integrated circuit having a short wiring distance by improving the wiring efficiency in the layout of the integrated circuit by effectively using each wiring layer in the integrated circuit performing the multilayer wiring.
【０００７】[0007]
【課題を解決するための手段】上記課題を解決するため
に、本発明の第１の特徴の集積回路の多層配線方法は、
図１に示す如く、ｍ層（ｍは３以上の正整数）の配線層
Ｌ１，Ｌ２，及びＬ３を備える集積回路の多層配線方法
において、前記ｍ層の配線層Ｌ１，Ｌ２，及びＬ３のメ
インの配線方向は、異なるｎ種（ｎは３≦ｎ≦ｍの正整
数）の配線方向Ｒ１，Ｒ２，及びＲ３である。In order to solve the above-mentioned problems, a method of multilayer wiring of an integrated circuit according to the first feature of the present invention is
As shown in FIG. 1, in a multilayer wiring method of an integrated circuit including m layers (m is a positive integer of 3 or more) of wiring layers L1, L2, and L3, the main wiring layers of the m layers L1, L2, and L3 are The wiring directions of are different n types (n is a positive integer of 3 ≦ n ≦ m) of the wiring directions R1, R2, and R3.
【０００８】また、本発明の第２の特徴の集積回路の多
層配線方法は、請求項１に記載の集積回路の多層配線方
法において、前記ｎ種の配線方向Ｒ１，Ｒ２，及びＲ３
は、お互いに等角度で交差する。According to a second aspect of the present invention, there is provided a multilayer wiring method for an integrated circuit according to claim 1, wherein the n types of wiring directions R1, R2 and R3 are provided.
Intersect each other at an equal angle.
【０００９】また、本発明の第３の特徴の集積回路の多
層配線方法は、請求項１または２に記載の集積回路の多
層配線方法において、前記集積回路は、論理セルを備え
るゲートアレイ、スタンダードセル等の集積回路であ
る。According to a third aspect of the present invention, there is provided a multilayer wiring method of an integrated circuit according to claim 1 or 2, wherein the integrated circuit includes a gate array including logic cells and a standard. An integrated circuit such as a cell.
【００１０】更に、本発明の第４の特徴の集積回路の多
層配線方法は、請求項３に記載の集積回路の多層配線方
法において、前記集積回路の多層配線方法は、前記論理
セルまたは前記論理セルの端子をグリッドと見做し、該
グリッド間の間隔が等しいアイソメトリック・グリッド
を用いて行われる。A fourth aspect of the present invention is a multilayer wiring method for an integrated circuit according to claim 3, wherein the multilayer wiring method for the integrated circuit is the logic cell or the logic cell. The terminals of the cells are regarded as grids, and isometric grids are used in which the intervals between the grids are equal.
【００１１】[0011]
【作用】本発明の第１及び第２の特徴の集積回路の多層
配線方法では、図１に示す如く、ｍ層（ｍは３以上の正
整数であり、図１ではｍ＝３）の配線層Ｌ１，Ｌ２，及
びＬ３を備える集積回路の多層配線方法において、前記
ｍ層の配線層のメインの配線方向を、それぞれ異なるｎ
種（ｎは３≦ｎ≦ｍの正整数であり、図１ではｎ＝３）
の配線方向Ｒ１，Ｒ２，及びＲ３とし、特に、第２の特
徴の集積回路の多層配線方法では、ｎ種の配線方向Ｒ
１，Ｒ２，及びＲ３がお互いに等角度で交差するように
している。In the multilayer wiring method of the integrated circuit having the first and second characteristics of the present invention, as shown in FIG. 1, wiring of m layers (m is a positive integer of 3 or more, and m = 3 in FIG. 1). In a multilayer wiring method of an integrated circuit including layers L1, L2, and L3, the main wiring directions of the m wiring layers are different from each other by n
Species (n is a positive integer of 3 ≦ n ≦ m, and n = 3 in FIG. 1)
Wiring directions R1, R2, and R3, and in particular, in the multilayer wiring method of the integrated circuit of the second feature, n kinds of wiring directions R
1, R2, and R3 intersect each other at an equal angle.
【００１２】また、ｍ＝５，ｎ＝３とした場合には、５
層の配線層Ｌ１〜Ｌ５を備える集積回路において、前記
ｍ層の配線層のメインの配線方向を、それぞれ３種の配
線方向Ｒ１，Ｒ２，Ｒ３，Ｒ１，及びＲ２として配線さ
れることになる。When m = 5 and n = 3, 5
In the integrated circuit including the wiring layers L1 to L5, the main wiring directions of the m wiring layers are wired as three kinds of wiring directions R1, R2, R3, R1, and R2, respectively.
【００１３】即ち、図１において、ｎ種の配線方向Ｒ
１，Ｒ２，及びＲ３が均等の角度で交差するｎ層の配線
層（第１、第２、及び第３層）Ｌ１，Ｌ２，及びＬ３を
用いて配線を行うことにより、各配線層を有効に使用す
ることができ、集積回路のレイアウトにおける配線効率
を向上させることができる。また斜め配線が可能となる
ため、従来の配線に比べて配線距離の短いレイアウトを
実現できる。That is, in FIG. 1, n kinds of wiring directions R
Each wiring layer is made effective by wiring using n wiring layers (first, second, and third layers) L1, L2, and L3 in which 1, 1, R2, and R3 intersect at an equal angle. It is possible to improve the wiring efficiency in the layout of the integrated circuit. Also, since diagonal wiring is possible, a layout having a shorter wiring distance than conventional wiring can be realized.
【００１４】また、本発明の第３及び第４の特徴の集積
回路の多層配線方法では、論理セルを備えるゲートアレ
イ、スタンダードセル等の集積回路に対し、レイアウト
のＣＡＤを行うシステム上で論理セルまたは論理セルの
端子をグリッドと見做し、該グリッド間の間隔が等しい
アイソメトリック・グリッドを用いて配線決定が行われ
る。According to the third and fourth aspects of the present invention, there is provided a multilayer wiring method for an integrated circuit, wherein a logic cell is provided on a system for performing layout CAD on an integrated circuit such as a gate array or a standard cell including the logic cell. Alternatively, the terminals of the logic cells are regarded as grids, and wiring is determined by using an isometric grid in which the intervals between the grids are equal.
【００１５】これにより、レイアウト設計の自動化が図
れると共に、各配線層を有効に使用することができ、集
積回路のレイアウトにおける配線効率を向上させること
ができる。As a result, the layout design can be automated, each wiring layer can be effectively used, and the wiring efficiency in the layout of the integrated circuit can be improved.
【００１６】[0016]
【実施例】次に、本発明に係る実施例を図面に基づいて
説明する。第１実施例 図１に本発明の第１実施例に係る集積回路の多層配線方
法の概念説明図を示す。図１（ａ）は立体図、図１
（ｂ）は平面図である。本実施例の集積回路は３層の配
線層を用いて配線される。集積回路としては、論理セル
を備えるゲートアレイ、スタンダードセル等の集積回路
を想定している。Embodiments of the present invention will now be described with reference to the drawings. First Embodiment FIG. 1 is a conceptual explanatory diagram of a multilayer wiring method for an integrated circuit according to a first embodiment of the present invention. FIG. 1A is a three-dimensional view, and FIG.
(B) is a plan view. The integrated circuit of this embodiment is wired using three wiring layers. As the integrated circuit, a gate array including logic cells, a standard cell, and the like are assumed.
【００１７】同図において、Ｌ１は第１層目の配線、Ｌ
２は第２層目の配線、Ｌ３は第３層目の配線、Ｒ１は第
１層目Ｌ１のメイン配線方向、Ｒ２は第２層目Ｌ２の配
線方向、Ｒ３は第３層目Ｌ３の配線方向を、それぞれ表
す。In the figure, L1 is the wiring of the first layer, L1
2 is the wiring of the second layer, L3 is the wiring of the third layer, R1 is the main wiring direction of the first layer L1, R2 is the wiring direction of the second layer L2, and R3 is the wiring of the third layer L3. Each direction is shown.
【００１８】本実施例の集積回路の多層配線方法は、論
理セルまたは論理セルの端子をグリッドと見做し、該グ
リッド間の間隔が等しいアイソメトリック・グリッドを
用いて行われる。図２（ａ）は、本実施例におけるアイ
ソメトリック・グリッドを表す。各層の配線方向Ｒ１，
Ｒ２，及びＲ３は、お互いに等角度（６０［deg ］）で
交差している。The multilayer wiring method of the integrated circuit of this embodiment is performed by using the isometric grid in which the logic cells or the terminals of the logic cells are regarded as grids and the intervals between the grids are equal. FIG. 2A shows an isometric grid in this embodiment. Wiring direction R1 of each layer
R2 and R3 intersect each other at an equal angle (60 [deg]).
【００１９】図２（ｂ）は、ゲートアレイ、スタンダー
ドセル等の集積回路における配線例を示す。図中、Ａは
論理セルであり、１２個の論理セルから成るセル列Ｂを
５列備えた構成である。また、第１層目Ｌ１の配線方向
Ｒ１は、セル列に対して垂直方向である。FIG. 2B shows an example of wiring in an integrated circuit such as a gate array and a standard cell. In the figure, A is a logic cell, which has a configuration including five cell rows B each including 12 logic cells. Further, the wiring direction R1 of the first layer L1 is a direction perpendicular to the cell column.
【００２０】同図において、ノードＭ１及びノードＮ１
間の配線は、第１層目の配線Ｌ１〜第２層目の配線Ｌ２
〜第３層目の配線Ｌ３〜第２層目の配線Ｌ２〜第１層目
の配線Ｌ１により配線され、また、ノードＭ２及びノー
ドＮ２間の配線は、第１層目の配線Ｌ１〜第２層目の配
線Ｌ２〜第１層目の配線Ｌ１により配線されている。ま
た、ノードＮ１近傍のアイソメトリック・グリッド及び
配線を同図（ｃ）に示す。In the figure, node M1 and node N1
The wiring between them is the wiring L1 of the first layer to the wiring L2 of the second layer.
-The wiring L3 of the third layer-the wiring L2 of the second layer-the wiring L1 of the first layer, and the wiring between the node M2 and the node N2 is the wiring L1 of the first layer Wiring is performed by the wiring L2 of the first layer to the wiring L1 of the first layer. Further, the isometric grid and wiring near the node N1 are shown in FIG.
【００２１】このように、本実施例による集積回路の多
層配線方法では、各層の配線方向Ｒ１，Ｒ２，及びＲ３
が均等の角度で交差する第１、第２、及び第３層Ｌ１，
Ｌ２，及びＬ３を用いて配線し、またＣＡＤシステム上
では、論理セルまたは論理セルの端子をグリッドと見做
したアイソメトリック・グリッドの構造モデルを使用し
て、配線決定を行うことにより、各配線層を有効に使用
することができ、集積回路のレイアウトにおける配線効
率を向上させることができる。As described above, in the multilayer wiring method for the integrated circuit according to the present embodiment, the wiring directions R1, R2, and R3 of the respective layers are set.
The first, second, and third layers L1, which intersect at equal angles
Wiring is performed by using L2 and L3, and on the CAD system, the wiring model is determined by using the isometric grid structural model in which the logic cell or the terminal of the logic cell is regarded as a grid. Can be effectively used, and the wiring efficiency in the layout of the integrated circuit can be improved.
【００２２】また、本実施例では斜め配線が可能となる
ため、従来の配線に比べて配線距離の短いレイアウトを
実現できる。第２実施例 図３に本発明の第２実施例に係る集積回路の多層配線方
法の説明図を示す。本実施例においても、第１実施例と
同様の（図１に示す）３層の配線層を用いて配線され
る。Further, in this embodiment, since diagonal wiring is possible, it is possible to realize a layout having a shorter wiring distance than the conventional wiring. Second Embodiment FIG. 3 shows an explanatory view of a multilayer wiring method of an integrated circuit according to a second embodiment of the present invention. Also in this embodiment, wiring is performed using the same three wiring layers (shown in FIG. 1) as in the first embodiment.
【００２３】図３（ａ）は、本実施例におけるアイソメ
トリック・グリッドを表す。第１、第２、及び第３層Ｌ
１，Ｌ２，及びＬ３の各層の配線方向Ｒ１，Ｒ２，及び
Ｒ３は、お互いに等角度（６０［deg ］）で交差してい
る。FIG. 3A shows an isometric grid in this embodiment. First, second, and third layers L
The wiring directions R1, R2, and R3 of the layers 1, L2, and L3 intersect each other at an equal angle (60 [deg]).
【００２４】図３（ｂ）は、ゲートアレイ、スタンダー
ドセル等の集積回路における配線例を示す。第２層目Ｌ
２の配線方向Ｒ２は、セル列に対して同方向である。同
図において、ノードＭ１及びノードＮ１間の配線は、第
１層目の配線Ｌ１〜第２層目の配線Ｌ２〜第３層目の配
線Ｌ３により配線され、また、ノードＭ２及びノードＮ
２間の配線は、第１層目の配線Ｌ１〜第２層目の配線Ｌ
２〜第１層目の配線Ｌ１により配線されている。また、
ノードＮ１近傍のアイソメトリック・グリッド及び配線
を同図（ｃ）に示す。FIG. 3B shows an example of wiring in an integrated circuit such as a gate array and a standard cell. Second layer L
The wiring direction R2 of 2 is the same direction as the cell row. In the figure, the wiring between the node M1 and the node N1 is wired by the wiring L1 of the first layer to the wiring L2 of the second layer to the wiring L3 of the third layer, and also the node M2 and the node N.
The wiring between the two is the wiring L of the first layer to the wiring L of the second layer.
It is wired by the second to first layer wirings L1. Also,
The isometric grid and wiring near the node N1 is shown in FIG.
【００２５】このように、本実施例による集積回路の多
層配線方法においても第１実施例と同様に、各配線層を
有効に使用することができ、集積回路のレイアウトにお
ける配線効率を向上させることができ、また斜め配線が
可能となることから、従来の配線に比べて配線距離の短
いレイアウトを実現できる。As described above, in the multilayer wiring method for an integrated circuit according to this embodiment, each wiring layer can be effectively used as in the first embodiment, and the wiring efficiency in the layout of the integrated circuit can be improved. In addition, since diagonal wiring is possible, a layout having a shorter wiring distance than conventional wiring can be realized.
【００２６】尚、第１及び第２実施例において、第ｉ層
目Ｌｉの配線方向Ｒｉのセル列に対する方向性は、上記
内容に限定されず、どのような組み合わせであっても構
わない。第３実施例 図４に本発明の第３実施例に係る集積回路の多層配線方
法の説明図を示す。In the first and second embodiments, the directivity of the i-th layer Li in the wiring direction Ri with respect to the cell row is not limited to the above description, and any combination may be used. Third Embodiment FIG. 4 shows an explanatory view of a multilayer wiring method of an integrated circuit according to a third embodiment of the present invention.
【００２７】同図において、Ｒ１は第１層目Ｌ１のメイ
ン配線方向、Ｒ２は第２層目Ｌ２の配線方向、Ｒ３は第
３層目Ｌ３の配線方向、Ｒ４は第４層目Ｌ４の配線方向
を、それぞれ表す。In the figure, R1 is the main wiring direction of the first layer L1, R2 is the wiring direction of the second layer L2, R3 is the wiring direction of the third layer L3, and R4 is the wiring of the fourth layer L4. Each direction is shown.
【００２８】本実施例の集積回路の多層配線方法は、論
理セルまたは論理セルの端子をグリッドと見做し、従来
と同様の平方グリッドを用いて行われる。図４（ａ）
は、本実施例における平方グリッドを表す。各層の配線
方向Ｒ１，Ｒ２，Ｒ３，及びＲ４は、お互いに等角度
（４５［deg ］）で交差している。The multilayer wiring method of the integrated circuit of this embodiment is performed by using the same square grid as the conventional one, by regarding the logic cell or the terminal of the logic cell as a grid. Figure 4 (a)
Represents the square grid in this embodiment. The wiring directions R1, R2, R3, and R4 of the respective layers intersect each other at an equal angle (45 [deg]).
【００２９】図４（ｂ）は、ゲートアレイ、スタンダー
ドセル等の集積回路における配線例を示す。図中、Ａは
論理セルであり、１２個の論理セルから成るセル列Ｂを
５列備えた構成である。また、第１層目Ｌ１の配線方向
Ｒ１はセル列に対して垂直方向で、第２層目Ｌ２の配線
方向Ｒ２はセル列に対して同じ方向である。FIG. 4B shows an example of wiring in an integrated circuit such as a gate array and a standard cell. In the figure, A is a logic cell, which has a configuration including five cell rows B each including 12 logic cells. The wiring direction R1 of the first layer L1 is perpendicular to the cell column, and the wiring direction R2 of the second layer L2 is the same direction to the cell column.
【００３０】同図において、ノードＭ１及びノードＮ１
間の配線は、第１層目の配線Ｌ１〜第２層目の配線Ｌ２
〜第４層目の配線Ｌ４〜第２層目の配線Ｌ２〜第１層目
の配線Ｌ１により配線され、また、ノードＭ２及びノー
ドＮ２間の配線は、第１層目の配線Ｌ１〜第２層目の配
線Ｌ２〜第３層目Ｌ３の配線〜第２層目Ｌ２の配線〜第
１層目の配線Ｌ１により配線されている。また、ノード
Ｎ１近傍のアイソメトリック・グリッド及び配線を同図
（ｃ）に示す。In the figure, node M1 and node N1
The wiring between them is the wiring L1 of the first layer to the wiring L2 of the second layer.
-The wiring L4 of the fourth layer-the wiring L2 of the second layer-the wiring L1 of the first layer, and the wiring between the node M2 and the node N2 is the wiring L1 of the first layer Wiring is performed by the wiring L2 of the first layer, the wiring L3 of the third layer, the wiring L2 of the second layer, and the wiring L1 of the first layer. Further, the isometric grid and wiring near the node N1 are shown in FIG.
【００３１】このように、本実施例による集積回路の多
層配線方法では、各層の配線方向Ｒ１，Ｒ２，Ｒ３，及
びＲ４が均等の角度で交差する第１、第２、第３、及び
第４層Ｌ１，Ｌ２，Ｌ３，及びＬ４を用いて配線し、ま
たＣＡＤシステム上では、論理セルまたは論理セルの端
子をグリッドと見做した平方グリッドの構造モデルを使
用して、配線決定を行うことにより、各配線層を有効に
使用することができ、集積回路のレイアウトにおける配
線効率を向上させることができる。As described above, in the multilayer wiring method of the integrated circuit according to the present embodiment, the wiring directions R1, R2, R3, and R4 of the respective layers intersect at an equal angle, that is, the first, second, third, and fourth wirings. By using the layers L1, L2, L3, and L4 for wiring, and using a square grid structural model in which a logic cell or terminals of the logic cell is regarded as a grid on a CAD system, wiring is determined. The wiring layers can be effectively used, and the wiring efficiency in the layout of the integrated circuit can be improved.
【００３２】また、本実施例では斜め配線が可能となる
ため、従来の配線に比べて配線距離の短いレイアウトを
実現できる。In addition, since diagonal wiring is possible in this embodiment, a layout having a shorter wiring distance than conventional wiring can be realized.
【００３３】[0033]
【発明の効果】以上説明したように、本発明によれば、
ｎ種の配線方向が均等の角度で交差するｍ層の配線層を
用いて配線し、またＣＡＤシステム上では、論理セルま
たは論理セルの端子をグリッドと見做した平方グリッド
の構造モデルを使用して配線決定を行うこととしたの
で、各配線層を有効に使用することができ、集積回路の
レイアウトにおける配線効率を向上させることができ、
また斜め配線が可能となるため、従来の配線に比べて配
線距離の短いレイアウトを実現でき、結果として、集積
回路のレイアウトにおける配線効率を向上させ、且つ配
線距離の短い集積回路の多層配線方法を提供することが
できる。As described above, according to the present invention,
Wiring is performed using m wiring layers in which n kinds of wiring directions intersect at equal angles, and a CAD system uses a square grid structural model in which logic cells or logic cell terminals are regarded as grids. Since the wiring is decided by using each wiring layer, the wiring layers can be effectively used, and the wiring efficiency in the layout of the integrated circuit can be improved.
Further, since diagonal wiring is possible, a layout having a shorter wiring distance than that of conventional wiring can be realized, and as a result, the wiring efficiency in the layout of the integrated circuit is improved, and a multilayer wiring method for an integrated circuit having a short wiring distance is provided. Can be provided.
【図１】本発明の第１実施例に係る集積回路の多層配線
方法の概念説明図であり、図１（ａ）は立体図、図１
（ｂ）は平面図である。FIG. 1 is a conceptual explanatory diagram of a multilayer wiring method of an integrated circuit according to a first embodiment of the present invention, FIG.
(B) is a plan view.
【図２】第１実施例の集積回路の多層配線方法の説明図
であり、図２（ａ）はアイソメトリック・グリッドの説
明図、図２（ｂ）はゲートアレイ、スタンダードセル等
の集積回路における配線例、図２（ｃ）はノードＮ１近
傍のアイソメトリック・グリッド及び配線を説明図であ
る。2A and 2B are explanatory views of a multilayer wiring method of an integrated circuit of the first embodiment, FIG. 2A is an explanatory view of an isometric grid, and FIG. 2B is an integrated circuit such as a gate array and a standard cell. An example of wiring, FIG. 2C is an explanatory diagram of an isometric grid and wiring near the node N1.
【図３】本発明の第２実施例の集積回路の多層配線方法
の説明図であり、図３（ａ）はアイソメトリック・グリ
ッドの説明図、図３（ｂ）は集積回路における配線例、
図３（ｃ）はノードＮ１近傍のアイソメトリック・グリ
ッド及び配線を説明図である。3A and 3B are explanatory diagrams of a multilayer wiring method of an integrated circuit according to a second embodiment of the present invention, FIG. 3A is an explanatory diagram of an isometric grid, and FIG. 3B is a wiring example in an integrated circuit;
FIG. 3C is an explanatory diagram of the isometric grid and wiring near the node N1.
【図４】本発明の第３実施例の集積回路の多層配線方法
の説明図であり、図４（ａ）は平方グリッドの説明図、
図４（ｂ）は集積回路における配線例、図４（ｃ）はノ
ードＮ１近傍のアイソメトリック・グリッド及び配線を
説明図である。FIG. 4 is an explanatory view of a multilayer wiring method of an integrated circuit of a third embodiment of the present invention, FIG. 4 (a) is an explanatory view of a square grid,
FIG. 4B is an illustration of wiring in the integrated circuit, and FIG. 4C is an illustration of an isometric grid and wiring near the node N1.
【図５】従来の集積回路の多層配線方法の概念説明図で
あり、図５（ａ）は立体図、図５（ｂ）は平面図であ
る。5A and 5B are conceptual explanatory diagrams of a conventional multilayer wiring method for an integrated circuit, FIG. 5A is a three-dimensional view, and FIG. 5B is a plan view.
Ｌ１，Ｌ２，Ｌ３，Ｌ４…第１、第２、第３、及び第４
層（目の配線） Ｒ１，Ｒ２，Ｒ３，Ｒ４…第１、第２、第３、及び第４
層の配線方向 Ａ…論理セル Ｂ…セル列 Ｍ１，Ｍ２，Ｎ１，Ｎ２…ノードL1, L2, L3, L4 ... First, second, third, and fourth
Layer (eye wiring) R1, R2, R3, R4 ... First, second, third, and fourth
Wiring direction of layers A ... Logic cell B ... Cell column M1, M2, N1, N2 ... Node
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/822 8832−4Ｍ Ｈ０１Ｌ 27/04 Ｄ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification number Office reference number FI technical display location H01L 21/822 8832-4M H01L 27/04 D
Claims (4)
（Ｌ１，Ｌ２，及びＬ３）を備える集積回路の多層配線
方法において、 前記ｍ層の配線層（Ｌ１，Ｌ２，及びＬ３）のメインの
配線方向は、異なるｎ種（ｎは３≦ｎ≦ｍの正整数）の
配線方向（Ｒ１，Ｒ２，及びＲ３）であることを特徴と
する集積回路の多層配線方法。1. A multilayer wiring method for an integrated circuit, comprising m layers (m is a positive integer of 3 or more) of wiring layers (L1, L2, and L3), comprising: m layers of wiring layers (L1, L2, and L3). The main wiring direction of) is a wiring direction of different n types (n is a positive integer of 3 ≦ n ≦ m) (R1, R2, and R3), which is a multilayer wiring method of an integrated circuit.
Ｒ３）は、お互いに等角度で交差することを特徴とする
請求項１に記載の集積回路の多層配線方法。2. The multi-layer wiring method for an integrated circuit according to claim 1, wherein the n kinds of wiring directions (R1, R2, and R3) intersect each other at an equal angle.
トアレイ、スタンダードセル等の集積回路であることを
特徴とする請求項１または２に記載の集積回路の多層配
線方法。3. The multilayer wiring method for an integrated circuit according to claim 1, wherein the integrated circuit is an integrated circuit such as a gate array including logic cells and a standard cell.
理セルまたは前記論理セルの端子をグリッドと見做し、
該グリッド間の間隔が等しいアイソメトリック・グリッ
ドを用いて行われることを特徴とする請求項３に記載の
集積回路多層配線方法。4. The multilayer wiring method of the integrated circuit, wherein the logic cell or the terminal of the logic cell is regarded as a grid,
4. The integrated circuit multilayer wiring method according to claim 3, wherein the method is performed by using an isometric grid having an equal interval between the grids.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22477393A JPH0786407A (en) | 1993-09-09 | 1993-09-09 | Multilayered wiring method of integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22477393A JPH0786407A (en) | 1993-09-09 | 1993-09-09 | Multilayered wiring method of integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0786407A true JPH0786407A (en) | 1995-03-31 |
Family
ID=16818993
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22477393A Withdrawn JPH0786407A (en) | 1993-09-09 | 1993-09-09 | Multilayered wiring method of integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0786407A (en) |
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|---|---|---|---|---|
| US6745379B2 (en) | 2001-08-23 | 2004-06-01 | Cadence Design Systems, Inc. | Method and apparatus for identifying propagation for routes with diagonal edges |
| US6795958B2 (en) | 2001-08-23 | 2004-09-21 | Cadence Design Systems, Inc. | Method and apparatus for generating routes for groups of related node configurations |
| US6802049B2 (en) | 2000-12-06 | 2004-10-05 | Cadence Design Systems, Inc. | Method and apparatus for computing placement costs by calculating bend values of connection graphs that model interconnect line topologies |
| US6848091B2 (en) | 2000-12-06 | 2005-01-25 | Cadence Design Systems, Inc. | Partitioning placement method and apparatus |
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| US6889372B1 (en) | 2000-07-15 | 2005-05-03 | Cadence Design Systems Inc. | Method and apparatus for routing |
| US6892371B1 (en) | 2002-01-22 | 2005-05-10 | Cadence Design Systems, Inc. | Method and apparatus for performing geometric routing |
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| US6915501B2 (en) | 2001-01-19 | 2005-07-05 | Cadence Design Systems, Inc. | LP method and apparatus for identifying routes |
| US6944841B1 (en) | 2002-01-22 | 2005-09-13 | Cadence Design Systems, Inc. | Method and apparatus for proportionate costing of vias |
| US6951006B1 (en) | 2002-01-22 | 2005-09-27 | Cadence Design Systems, Inc. | Decomposing IC regions and embedding routes |
| US6951005B1 (en) | 2001-06-03 | 2005-09-27 | Cadence Design Systems, Inc. | Method and apparatus for selecting a route for a net based on the impact on other nets |
| US6976238B1 (en) | 2001-06-03 | 2005-12-13 | Cadence Design Systems, Inc. | Circular vias and interconnect-line ends |
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| US7047513B2 (en) | 2002-11-18 | 2006-05-16 | Cadence Design Systems, Inc. | Method and apparatus for searching for a three-dimensional global path |
| US7055120B2 (en) | 2000-12-06 | 2006-05-30 | Cadence Design Systems, Inc. | Method and apparatus for placing circuit modules |
| US7073150B2 (en) | 2000-12-07 | 2006-07-04 | Cadence Design Systems, Inc. | Hierarchical routing method and apparatus that use diagonal routes |
| US7080336B2 (en) | 2000-12-06 | 2006-07-18 | Cadence Design Systems, Inc. | Method and apparatus for computing placement costs |
| US7096449B1 (en) | 2002-01-22 | 2006-08-22 | Cadence Design Systems, Inc. | Layouts with routes with different widths in different directions on the same layer, and method and apparatus for generating such layouts |
| US7171635B2 (en) | 2002-11-18 | 2007-01-30 | Cadence Design Systems, Inc. | Method and apparatus for routing |
| US7310793B1 (en) | 2001-06-03 | 2007-12-18 | Cadence Design Systems, Inc. | Interconnect lines with non-rectilinear terminations |
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-
1993
- 1993-09-09 JP JP22477393A patent/JPH0786407A/en not_active Withdrawn
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| US7080336B2 (en) | 2000-12-06 | 2006-07-18 | Cadence Design Systems, Inc. | Method and apparatus for computing placement costs |
| US6802049B2 (en) | 2000-12-06 | 2004-10-05 | Cadence Design Systems, Inc. | Method and apparatus for computing placement costs by calculating bend values of connection graphs that model interconnect line topologies |
| US6826737B2 (en) | 2000-12-06 | 2004-11-30 | Cadence Design Systems, Inc. | Recursive partitioning placement method and apparatus |
| US6848091B2 (en) | 2000-12-06 | 2005-01-25 | Cadence Design Systems, Inc. | Partitioning placement method and apparatus |
| US7055120B2 (en) | 2000-12-06 | 2006-05-30 | Cadence Design Systems, Inc. | Method and apparatus for placing circuit modules |
| US7073150B2 (en) | 2000-12-07 | 2006-07-04 | Cadence Design Systems, Inc. | Hierarchical routing method and apparatus that use diagonal routes |
| US6915501B2 (en) | 2001-01-19 | 2005-07-05 | Cadence Design Systems, Inc. | LP method and apparatus for identifying routes |
| US6882055B1 (en) | 2001-06-03 | 2005-04-19 | Cadence Design Systems, Inc. | Non-rectilinear polygonal vias |
| US7310793B1 (en) | 2001-06-03 | 2007-12-18 | Cadence Design Systems, Inc. | Interconnect lines with non-rectilinear terminations |
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| US6895569B1 (en) | 2001-06-03 | 2005-05-17 | Candence Design Systems, Inc. | IC layout with non-quadrilateral Steiner points |
| US6859916B1 (en) | 2001-06-03 | 2005-02-22 | Cadence Design Systems, Inc. | Polygonal vias |
| US6745379B2 (en) | 2001-08-23 | 2004-06-01 | Cadence Design Systems, Inc. | Method and apparatus for identifying propagation for routes with diagonal edges |
| US7398498B2 (en) | 2001-08-23 | 2008-07-08 | Cadence Design Systems, Inc. | Method and apparatus for storing routes for groups of related net configurations |
| US7155697B2 (en) | 2001-08-23 | 2006-12-26 | Cadence Design Systems, Inc. | Routing method and apparatus |
| US6795958B2 (en) | 2001-08-23 | 2004-09-21 | Cadence Design Systems, Inc. | Method and apparatus for generating routes for groups of related node configurations |
| US7096449B1 (en) | 2002-01-22 | 2006-08-22 | Cadence Design Systems, Inc. | Layouts with routes with different widths in different directions on the same layer, and method and apparatus for generating such layouts |
| US6951006B1 (en) | 2002-01-22 | 2005-09-27 | Cadence Design Systems, Inc. | Decomposing IC regions and embedding routes |
| US6944841B1 (en) | 2002-01-22 | 2005-09-13 | Cadence Design Systems, Inc. | Method and apparatus for proportionate costing of vias |
| US6892371B1 (en) | 2002-01-22 | 2005-05-10 | Cadence Design Systems, Inc. | Method and apparatus for performing geometric routing |
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| US7171635B2 (en) | 2002-11-18 | 2007-01-30 | Cadence Design Systems, Inc. | Method and apparatus for routing |
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