JPS61292341A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To uniformly set a wiring density and to integrate without increasing the number of tracks by blocking cell row groups, wiring with the first and second wiring layers in the block, and wiring between the blocks with the third wiring layer. CONSTITUTION:A chip is divided into four blocks, and one is used for function blocks 5 such as ROM, RAM, PLA. The remaining three blocks are composed of cell rows 2 in which several types of standard cells 3 of NAND, NOR of the minimum units of logic functions are aligned in many rows. The length of the cell row is decided so that the number of tracks of the cell row direction required for wiring between the cells 3 in each block becomes the width between the terminals of the adjacent cell rows, i.e., the wiring region, namely, the height of the cell, as the block number 3. The cell rows are disposed and wired in each block by the first layer aluminum in the direction along the row and the second layer aluminum in the direction perpendicular thereto by a CAD. Then, the connection between the blocks in lateral direction is decided by the third aluminum wiring layer. The connection between the blocks in elevational direction uses the second layer aluminum. This is to eliminate the contact with the third layer aluminum.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a standard cell type semiconductor integrated circuit.

[Technical background of the invention and its problems]

Standard cell type semiconductor integrated circuits consist of multiple types of standard cells, such as NAND6 or NOR, which are the minimum unit of logic function, arranged in rows to form cell rows, and connections are required between these cell rows. It is used as an area for wiring between standard cells. According to this method, b
The width of the channel is variable and can be as wide as required.
As shown in the figure. In this way, in a general standard cell type semiconductor integrated circuit, a cell row 2 consisting of a row of standard cells 3, an area 4 for wiring, and a pre-designed RO
It is composed of functional blocks 5 such as M, RAM, and PLA.

Further, wiring is usually performed using two-layer metal wiring, with separate layers being assigned to horizontal (parallel to the cell columns) and vertical (perpendicular to the cell columns) interconnects.

However, in this system, as the scale increases, the length of the cell rows becomes longer, and the number of vertical and horizontal wiring lines for connecting each standard cell also increases accordingly. Further, the width of the channel, which is a region for wiring, is determined by the number of horizontal wirings, and if there is a part where there are many horizontal wirings, the width of the channel needs to be equal to the width of that part. Generally, such a region tends to occur near the center of each cell row, and therefore, there is a problem in that the left and right end portions of such a cell row remain as invalid regions that are not effectively used for wiring.

In addition, there is a strong correlation between the number of standard cells included in one cell column and the wiring area between that cell column and the opposing cell column. There is also a tendency for the number of such areas to increase. Therefore, as the length of the cell array becomes longer, the area required for wiring also increases, and the above-mentioned problem tends to be exacerbated.

[Purpose of the invention]

The present invention improves the drawbacks of the conventional method described above.
The purpose of this invention is to provide a standard cell type semiconductor integrated circuit with high integration.

[Summary of the invention]

In the present invention, by determining the length of a cell column according to the number of tracks (placement area for interconnection wiring between cells in the direction of the cell column) required for intra-block wiring, a group of logic cell columns can be divided into blocks, and the length of the cell column can be divided into blocks. are distributed by the first and second layer metal wiring.
The feature is that the blocks are interconnected using third-layer metal interconnections.

〔Effect of the invention〕

According to the present invention, uniform wiring density is achieved by forming blocks, and since inter-block wiring uses an upper layer, high integration can be achieved without increasing the number of tracks.

Further, it is more effective to increase the integration density by determining the length of the cell row so that the width of the wiring region where the track is provided is equal to the height of the standard cell, and by overlapping the cell row and the wiring region.

[Embodiments of the invention]

FIG. 1(a) is a diagram showing an embodiment of the present invention.

The chip is divided into four blocks, one of which is ROM,
It is allocated to functional block 5 such as RAM and PLA. The remaining three blocks are composed of cell rows 2 in which a large number of standard cells 3 of a plurality of types, such as NAND, NOR, etc., which are the minimum units of logic functions, are arranged in rows. Cell input/output terminals are provided at the center axis of the cell row (x mark). Then, by statistically determining the standard cell 3 in each block,
The length of the wiring between them is determined, and the number of blocks is 3 as described above.

In this embodiment, first, placement and wiring are performed in each block using CAD using the first layer M1 in the direction along the cell column and the second layer M in the direction perpendicular thereto. The 0 mark indicates a through hole.

Next, connections between blocks in the left and right direction are determined by the third layer M wiring. Connections between blocks in the vertical direction are in the second layer,
υ is used. This is done to prevent contact with the third layer M wiring. Moreover, in the layout and wiring within the block, the wiring in the direction perpendicular to the cell columns is less dense than the wiring in the direction of the cell columns, so it does not cause any interference.
Therefore, the design is easy.

FIG. 2 shows another embodiment. Here, the directions of the cell columns 2 in each block are different. However, the fact remains that the wiring within the block is composed of the first layer M1 in the direction of two cell columns and the second layer Al in the direction perpendicular thereto. The third layer AJ is used for the inter-block wiring, but it is connected to the second layer Al in the direction perpendicular to the cell rows through through holes at the block boundaries, thereby achieving layer conversion. This is the result of allocating different wiring layers in the x and y directions for inter-block wiring, and at the same time using the fact that the intra-block wiring in the direction perpendicular to the cell columns is sparse in density.

As described above, according to the present invention, blocks are formed with consideration given to the number of tracks, wiring is performed using the first and second/i metal wiring within the block, and third layer metal wiring is used between blocks, and High-density placement and wiring can be achieved.

In addition, in the above embodiment, the relationship between the first layer and the second layer M may be completely reversed. Furthermore, the present invention is not limited to the above-mentioned embodiments, and can be similarly applied to those in which wiring regions are provided between cell columns as shown in FIG.

[Brief explanation of drawings]

1 and 2 are plan views showing embodiments of the present invention;
The figure is a plan view of the conventional row. In the figure, 1... semiconductor substrate, 2... cell row, 3... standard cell, 4... wiring area, 5... functional block. Agent Patent Attorney Kensuke Chika (and 1 other person) No.
2 figure

Claims (3)

[Claims] (1) In a semiconductor integrated circuit in which a plurality of logic cell rows are formed on a semiconductor substrate and the cells are interconnected to achieve a desired circuit operation, the length of the cell rows is determined by the wiring track required for intra-block wiring. By deciding according to the number
A semiconductor integrated circuit characterized in that a group of logic cell columns is divided into blocks, the blocks are interconnected using first and second layer metal interconnections, and the blocks are interconnected using third layer metal interconnections. (2) The semiconductor according to claim 1, wherein adjacent blocks are connected by third-layer wiring in the direction of the cell columns and by second-layer wiring in the direction perpendicular to the cell columns. integrated circuit. (3) The semiconductor according to claim 1, characterized in that cell rows are arranged at right angles to each other between adjacent blocks, and inter-block interconnections are layer-converted via through holes in adjacent regions. integrated circuit.