JPH0223661A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To miniaturize a chip by reducing an electrode occupation rate by sharing a set of power supply pads VCC1 and a ground bonding pad GND 1 for a plurality of electronic circuit block power supplies not operable simultaneously, and sharing part of an electrode extending from the pad to each mat. CONSTITUTION:For example, an FM front/end block 24 is integrated on mats K-M, an FM-IF block 25 on mats E-I, and a noise canceller block 26 on mats N-P. An AM tuner block 28 is integrated on mats A-D. These blocks are crossed over through through-holes indicated by black circles and through a second layer electrode layer 79. Since the block 28 is not operable simultaneously with the external block circuits, the blocks 28 and 25 share one pad VCC1. Accordingly, the chip interior can effectually be utilized by sharing part of a power line and a ground line.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit having a pattern and layout that can be easily expanded to meet the demands of custom ICs. It is something.

Furthermore, the present invention relates to a semiconductor integrated circuit that effectively utilizes a plurality of power supply pads.

(b) Conventional technology in general is disclosed in Japanese Patent Application Laid-Open No. 59-84542 (HOI L
21776), a semiconductor integrated circuit technology in which a plurality of circuit blocks are formed on the same semiconductor substrate has the configuration shown in FIG.

FIG. 6 is a schematic plan view of the semiconductor chip (101), and a to f indicate circuit blocks. These circuit blocks handle different frequencies and signal levels, and
The functions are also different.

This circuit block is formed in an N-type region (103) on a P-type semiconductor substrate (102) as shown in FIG. 7, and each circuit block is formed in a highly doped P1-type region ( 104). Here, block b and block C are shown.

The P1 type area (104) for this partition has one end connected to P1.
It is in contact with a - type semiconductor substrate (102), and the other end is ohmically connected to a ground line (106) through an oxide film (105) on the semiconductor surface.

A ground line (106) extends from each block to one or more ground bonding pads GND at the left end, converging in the center of the integrated circuit.

Next, the power supply lines (VC-) of each block circuit are grouped around the outer periphery of the integrated circuit, as shown in Figure 6, and
Connected to one or more power supply bonding pads.

(c) Problems to be Solved by the Invention Since the ground lines and power lines are extended to each block via pads, the number of ground lines and power lines increases depending on the number of blocks, and the pads I had a growing problem.

On the other hand, if we distinguish the operations of the blocks a-f,
There are two types of blocks: blocks that operate all the time and blocks that do not operate at the same time. These blocks that do not work at the same time are each provided with the ground line and the power supply line. For example, assuming that block C and block r do not work at the same time, if block C is working, the ground line (107) and power line (108) are useless.
If block f is operating, ground line (109)
And the power line (110) is wasted. Therefore, the inside of the chip is not effectively utilized.

In addition, since the circuit blocks a to f have different functions, the number of elements in each block is different, and the block size is different. ), the sizes of each circuit block interact with each other, making it difficult to integrate them into the same chip.

Also, if you delete circuit block a and insert another circuit block a' with improved characteristics, or if you try to add circuit block g with another function to the circuit block configuration shown in Figure 6, each block Because the sizes were different, it was necessary to recreate all the patterns.

Therefore, in recent years, the lifespan of products has become extremely short, and when a user tries to incorporate a unique circuit desired by a chip into a certain chip, even though the user wants a short delivery time, the circuit The problem was that it required a very long lead time to remake the pattern.

(d) Means for Solving the Problems The present invention was made in view of the above problems, and blocks that do not work simultaneously use one power supply and ground pad, and connect the power supply line and ground line extending from this pad. The solution is to share a part, and the top surface of the semiconductor chip (1) is divided into many mats of substantially the same size at the partition line (5), and one or more electronic circuit blocks with different functions are divided into multiple mats. The conventional problem is solved by accommodating the mat in an integral number of mats.

(E) Effect According to the present invention, for example, in a structure in which each of the first and second electronic circuit blocks has a power supply pad and a ground pad, and a power supply line and a ground line extend from each pad, Considering that they do not work at the same time, pads and lines can be shared, so by using one power supply pad and ground pad and sharing at least part of the power supply line and ground line that extend from this pad, the inside of the chip can be made effective. In addition, by dividing the top surface of the semiconductor chip (1) into a large number of mats of substantially the same size at the partition line (5) and accommodating a plurality of electronic circuit blocks with different functions in an integral number of mats. , it becomes possible to design each electronic circuit block, and to divide the electronic circuit block into a fixed number of elements to design each mat. Therefore, parallel design is possible by dividing each electronic circuit block.
Design period can be significantly shortened. Furthermore, since circuit changes can be made for each electronic circuit block and for each mat, there is no need to change the design of the entire IC.

(F) Embodiment First, a first embodiment of the present invention will be described in detail with reference to FIG.

The upper surface of the semiconductor chip (1) is divided into divided regions (2) indicated by two-dot chain lines.
) is used to divide the area into first and second areas (3) and (4) with substantially the same shape, and separate each area (3) into two.
, (4> is divided into A-, T, and Ni-T mats. A power line shown by a solid line and a ground line shown by a dashed-dotted line are connected between each mat of A-J and Ni-T. The area is divided by partition lines (dan) that extend parallel to each other.

The arrangement of the power supply lines and ground lines forming the partition line (5) is such that the power supply line shown by a solid line is provided on the left side of each mat AJ and -T, and the ground line shown with a dashed line is provided on the right side. Therefore, only the partition lines (5) at both ends are formed of either the power supply line or the ground line, and the middle partition line is formed of both. Power lines and ground lines adjacent to each mat A-J, to T are integrated in each mat, and supply power to the circuit blocks.

In addition, the power line and ground line of each division line (base) are the third power line (6> and the second power line (7) shown by the three-dot chain line), the third ground line (8) and the second The third and second power supply lines (6), (7) are connected to the ground line (9) in a comb-teeth pattern, facing each other.
) and the third and second ground lines (8),
(9) is the power supply pad v0゜I*VCCt and the ground pad GN among the pads provided around the pellet.
D1. Guided by GND2.

As will become clear later, due to the circuit, ~M on the mat is
Apart from these pads, vccs l VcC4*G
ND3, GND4 are used, and each power line, ground line, and second and third power lines (7
), (6), second and third ground lines (9
).

(8) is basically realized by one layer of two-layer wiring.

Each mat A-J divided by the above-mentioned division line (5)
, to-T are formed into shapes of substantially the same size;
Specifically, the width is set so that six NPN transistors can be lined up, and the length is set to a certain number of elements that is easy to design.
For example, settings are made so that approximately 100 elements can be laid out. The size of this mat can be arbitrarily selected depending on the number of elements that can be easily designed depending on the electronic circuit block to be integrated.

The circuit elements integrated within the mat are composed of transistors, diodes, resistors, and capacitors, and are separated by normal PN isolation, and the connections of each element are connected by the first electrode layer of the two-layer wiring. Generally, there is crossover at the second layer of electrodes.

Next, with reference to FIGS. 2A and 2B, the circuit elements integrated within the mat and the partition lines (5) will be specifically described.

FIG. 2A is an enlarged top view of the vicinity of mat B.

The division line (6) indicated by the dashed line on the left is the division line (5) provided between mat A and mat B, and the division line (7) indicated by the dashed dot line on the right is the division line (5) provided between mat B and mat B. This is a partition line (5) provided between C. Between the division lines (6) and (7), there is a transistor (8), a diode (9), and a resistor (shown as dotted lines).
10) and a capacitor (11) are integrated. Although these elements are rough in the drawing,
In reality, they are highly concentrated. In addition, the wiring between elements within the mat is substantially formed by the first electrode layer (14) shown by the - dotted chain line.
The wiring between mats C and C, such as signal lines and feedback lines, is connected to the second electrode layer (15
) is formed. These first and second electrode layers (14>, (15)) are connected at contact regions indicated by X marks.

FIG. 2B is a sectional view taken along line AA' in FIG. 2A. An N-type epitaxial layer (15) is laminated on a P-type semiconductor substrate (14), and this epitaxial layer (
15) P+ reaching the semiconductor substrate (14) from the surface
A mold isolation region (16) is formed and a number of island regions are formed. In this island region (17), an NPN transistor (8), a diode (9), a resistor 10), a capacitor (11), etc. are made.
An N+ type buried region (19) is formed between the collector region (18) of the NPN transistor (8) and the semiconductor substrate (14). The epitaxial layer (1
A silicon oxide film <5> is formed on the surface of <5> by, for example, the CVD method.
20> is formed, and a first electrode layer (12) is formed on this silicon oxide film (20). In addition, for example, FIX
An insulating film 21) is formed, and a second electrode layer (13) is formed on this insulating film (21). Further, a power supply line (22) and a ground line (23) are provided on the isolation region (16), and a ground line (22) is provided on the isolation region (16).
3) is in ohmic contact with this isolation region 16> to stabilize the substrate potential.

More specifically, 10 mats A-J are formed in the first region (3), and 10 mats A-J are formed in the second region (4).
The mats are formed in substantially the same space where approximately 100 elements can be integrated, and the partition lines (
5).

The 20 mats listed above contain AM/FM as shown in Figure 4.
A 1-chip stereo tuner IC is formed. Fourth
The figure is a block diagram explaining this electronic block circuit, and includes an FM front end block (24), an FM-I F
block (25), noise canceller block (26)
), multiplex decoder block (27), A
It is composed of a total of five electronic circuit blocks including an M tuner block (28). Although each circuit block is well known, its function will be briefly explained.

First, the FM front end block (24) is a channel selection part for FM broadcasting, and receives an FM broadcast signal of several tens of MHz to several hundred MHz and converts the frequency into an intermediate frequency signal of 10.7 MHz. There are about 250 of them, so they are integrated into the -M mat. Next, FM-IF
The block (25) amplifies this intermediate frequency signal and then detects it to obtain an audio signal, and has approximately 430 elements, so it is integrated on the E-I mat. Next, the noise canceller block (26) removes pulse noise such as ignition noise, and has about 270 elements, so it is integrated into an NP mat. Further, the multiplex decoder block (27) is a block for stereo demodulating a stereo signal, and since it has about 390 elements, it is integrated into a QT mat. Finally, the AM tuner block (28) is the channel selection part for AM broadcasting, and converts the AM broadcasting signal received by the antenna to an intermediate frequency (450KHz) and detects it to obtain an audio output.
Since it has 50 elements, it is integrated in A-D mats.

Furthermore, in FIG. 5A5, FIG. 5B, and FIG. 5C, AM
A diagram in which a tuner block (2g), a front end block (24), an FM-IF block (25), and a multiplex decoder block (27) are further divided into blocks is shown.

First of all, the local oscillation circuit (OS C) (29) in the AM tuner block (28) in Fig. 5 A (7) is connected to A)
Mixing circuit (MI
RF) (32) and intermediate frequency amplification circuit (IF) (33)
) is on mat C, and the detection circuit (D E T ) (34)
is substantially integrated on the mat D, and as shown in FIG. 1, the power pad ■. The third power supply line (35), (36), (3
7), (3B) to the first power supply line (39) of mats A to D. It supplies C. In addition, the ground pad GND 1 connects to the second ground line (shown by the three-dot chain line) on the one-end divided area (2) via the three-tree electrode (40) in the shape of an octopus foot provided between the mat M and the mat N. 4
1), (42), (43), and are connected to the respective second ground lines (41), (42), (
43) is the first ground line (44) of the A-D mat.
)It is connected to the.

Next, the high frequency amplification circuit (45) and the mixing circuit (45) in Figure 5B are shown.
6) and a local oscillation circuit (47), the front end block (24), which is composed of a local oscillation circuit (47), handles signals at an extremely small level of several μV, so it
It dislikes interference from the F block (25), and the local oscillation circuit (47) in this block oscillates itself, generating unnecessary radiation. Therefore, it should be separated from the FM-IF block (25) in particular, and a separate power supply (2) should be provided since the O8C block hates interference the most. C8, VeC4+GND3, G
ND4 is used.

That is, the FM-IF block 25) is integrated on a mat of -M diagonally, and the local oscillation circuit (47) is integrated on the mat K, which is the cornermost corner, and another pad (2) is placed on both sides thereof. A first power supply line (48) and a Guérande line (49) are provided through O4 and GND4. In addition, the mat of M is connected to VCC3 and GND3.
Through these, respective first power and ground lines (50) and (51) are provided.

On the other hand, an FM-IF block (25) consisting of an intermediate frequency amplification circuit (52), a detection circuit (53), an S meter (<54), etc. is integrated on the E-I mat, and a detection circuit (<53) is on mat I, S meter (54) etc. is on mat G
Further, a limiter circuit, a mute circuit, etc. in the intermediate frequency amplification circuit (52) are substantially integrated on the E, F, and G mats.

Here, the limiter circuit with an extremely high gain of 80 to 100 dB and the detection circuit (53) with a large signal level, the limiter circuit and the S meter (54) with a large signal level generate oscillation due to feedback, and the detection circuit (53) and S meter (54
), the characteristics deteriorate due to mutual interference, so matte E,
The first power line (55) of F and G is connected to the third power line (37) shown by one three-dot chain line, and the first power line (56) of mats H and I is connected to one tree. Third power line (
36) is not connected. Further, the mat J is one in which optional circuits provided by the user are integrated, and this first power supply line (57>) is also connected to one third power supply line (35).

Also, the first ground line (58) shown by the dashed line on the E-J mat extends from the ground pad GNDI in a kite-like shape and is connected at one end to the second ground line (41), (42). , (43) are connected in the same manner as described above.

Next, the DC amplifier circuit (59) and decoder circuit (6) of the multiplex decoder block (27) in FIG.
0), the lamp driver circuit (61) is connected to mat Q and mat R, and the phase comparison circuit (62), low-pass filter circuit (63), voltage controlled oscillator (64), frequency dividing circuit (65), etc. are connected to mat S. It is substantially integrated into the mat T. Also power pad VCC! The three electrodes (66), (67), and (6B) are extended in a more octopus-like shape.
It passes between the AM tuner block (28) and the FM-IF block (25) and is connected at one end to the second power supply lines (69), (70), (71) on the divided area (2). Then, one tree goes to mats Q and R, one tree goes to mats S and T, and one tree goes to the noise canceler block (
26), which extends to the N-P mat.

On the other hand, ground pad GND2 is the third of three trees in the shape of an octopus foot.
The ground lines of (72), (73), (74
), and as before, connect the N-P mat, Q, R
It extends to the mat, S, and T mats.

Furthermore, pad V is used to prevent mutual interference between blocks.
CC1+VCCQ, pads GNDI and GND2 are each used, and pad V is used. CI+VCCQ is connected to lead (75) and pads GNDI, GND2
is connected to the lead (76). First, this prevents fluctuations in the pad VCCI from being directly transmitted to the pad VCC2, and by using two thin metal wires, the impedance of the thin metal wires is lowered. Therefore, pulse noise or the like that enters the lead is not amplified through the impedance, and voltage fluctuations can be prevented.

As explained above, the division line (5) consisting of the first power supply line and the first ground line is A-J,
, -T mats are divided. In addition, since the first power supply line and the first ground line are formed in a substantially comb-like shape, the space between the mats and the surrounding space can be effectively utilized, and the pad VC6 around the chip (1)
,, GNDI, and GND2 can be connected in the shortest distance.

Next, countermeasures against interference between the FM front end (24) and the FM-IF block (25) will be described. Previously, individual I
This was a problem with the set board because C was used for each, but this time, since it was made into one chip, this interference became an additional problem, but it was solved by the following measures.

First, as mentioned above, the FM front end block (24
) handles extremely small level signals of several μV, so
Because it dislikes interference from other circuit blocks, especially the FM-IF block (25), and because the local oscillation circuit (47) configured within this block oscillates itself and generates unnecessary radiation, it must be separated from other blocks. or provide a separate power source.

For these reasons, first, the FM front end block and the FM-IF block were provided diagonally, and the local oscillation circuits in these blocks were integrated on the mat K and separated from each other. Next, AM tuner block (28) and FM-I
F block (25), FM front end block (
24) and the noise canceller block (26),
In other words, by widening the partition line widths of mats D and E, and mats M and N, the FM front end block (24) can be separated from other blocks, especially the FM-IF block (
25). Also, between mat D and mat E, and between mat M and mat N, there is a power pad ■. An electrode (66) extending from o2 to the second region (4), (
67), (68) and an electrode (40) extending from the ground pad GNDI to the first region (3) are provided, and a second power supply line (69),
<70), (71) and the second ground line (41
), (42), and (43) are provided. Therefore, the FM front end block (24)
-IF block (25), AM tuner block (2)
8) and the noise canceller block (26), especially the power lines (66), (67), (
68) prevents unnecessary radiation, and since at least one of the ground lines (40) is in contact with the isolation region (16), the substrate current can be sucked out and interference is prevented.

Also, since the local oscillation circuit 47) in this FM front end block (24) dislikes interference, the power supply pad V
. . 4 and a ground pad GND4 are provided separately, and the external circuit is a power supply pad V. . , and are supplied by ground pad GND3.

Furthermore, the FM-IF block (25)
This circuit has a limiter circuit for removing the portion, and this circuit is integrated with mat E and mat F.

The capacitor in this limiter circuit causes leakage to the substrate, and this leakage current flows to the FM front end, causing malfunction. Therefore, the capacitors are grouped together in the mat E, and the first ground line (77) on the left side of the mat E (under the division line) is intensively sucked out. Furthermore, the first ground line (77) is connected to the FM-IF block (25) and the multiplex decoder block (25).
7〉 and the noise canceller block (26〉) are extended to the outer periphery of the area where the noise canceller block (26〉) is formed, and the leakage current generated from these is also sucked out. Similarly, the ground line (78〉 ).Also, due to wiring reasons, the third power line (35), (36
), (37), (38), second power line (69), (70), (71) on divided area (2)
) and second ground lines (41), (42)
, (43), etc., cross over through the through holes indicated by black circles and through the second electrode layer (79) indicated by dotted lines. Especially the AM tuner block (28)
The AM tuner block (28) and FM-IF block (25) do not operate simultaneously with other block circuits.
■ One pad. They share the ol, so there is a crossover. The same applies to the ground bad GNDI.

The above-mentioned configuration is shown in FIG. -The one indicated by the dotted chain line is 1
Among the electrodes formed in each layer, the one shown by a solid line is the second layer electrode. The area indicated by the X mark is the through hole. Since the two blocks do not work at the same time, they are shared, and in terms of pattern, the electrodes from the pad VCC1 and GNDI to the through hole are shared, so the area occupied by the electrodes can be reduced.

Finally, let's take a look at an example of the features of the present invention. For example, if the AM tuner block (28) is unnecessary, the four mats that will become the multiplex decoder block (27) are integrated as they are in the mats A to D, and the remaining mat Q
For example, mats I and J are integrated into mat R. Therefore, since the I, J, S, and T mats are redundant, by deleting these mats, the mats can be arranged neatly in a rectangular chip. Here, the first layer wiring within the mat can be used as is, and only the wiring between mats and the wiring between blocks need be considered.

Also, when partially improving the FM-IF block (25),
For example, it is only necessary to take out the mat F, which is the improved part, and improve it, and the other mats E, G, and H can be used as they are. Also, when adding another block that is an option for the user, all the mats can be used as is and only the required number of mats can be added to this block, and in this case mat J is used as the mat for this option.

In other words, since mats of the same size are formed in a matrix, replacement, addition, and deletion are very easy.

(G) Effects of the Invention As is clear from the above explanation, firstly, the power supplies for the plurality of electronic circuit blocks that do not work simultaneously are set in (1). c, ,
Since GNDl is shared, a part of the electrode extending from the pad to each mat can be shared.

Therefore, the electrode occupation rate of the chip (1) can be reduced, contributing to chip miniaturization.

Second, AM tuner block (28) and FM-IF
Connect the power and ground pads of block (25) to V, o
, , If GNDI is used, the electrode occupation rate can be reduced in the IC of the AM/FM stereo tuner circuit as described above, and the chip can be made smaller.

Thirdly, the pad■. CI + vcct and lead (75
) are connected with thin metal wires, the impedance of the thin metal wires decreases because they are connected in parallel.

Therefore, pulse noise and the like entering the lead (75) enters through the thin metal wire with low impedance, so that this noise is not amplified significantly. Therefore, voltage fluctuations can be prevented. Similarly pad GNDI, GND2
and the lead (76) can also prevent voltage fluctuations.

Fourth, a plurality of power lines (35), (36), (37) extend from the power supply pad VCCI to mats A-D where the AM tuner block (28) is formed.
, (38) are formed in the second layer at one end. This is to cross over the power lines (66), (67), and (6B). This makes it possible to share the AM tuner block (28) and the FM-IF block (25).

Further, the ground lines (41), (42), and (43) extending from the ground pad GNDI can also be shared in the same way.

Fifth, if the top surface of the semiconductor chip (1) is divided into a large number of mats of substantially the same size along partition lines (intersections) and a plurality of electronic circuit blocks with different functions are housed in an integral number of mats, the electronic circuit blocks Each project can be designed in parallel, significantly shortening the design period.

Furthermore, since the electronic circuit block can be divided into a fixed number of elements and designed for each mat, parallel design for each mat can be performed.

Further, since circuit changes such as deletion, addition, and modification can be designed for each electronic circuit block or each block, it is sufficient to make changes for each block or each mat, and there is no need to change the design of the entire IC.

Furthermore, mats can be made into cells as basic blocks, so
Once the design is complete, when changing the circuit afterwards, you only have to modify the mat to be changed, and the other mats can be used as they are, resulting in extremely high reliability.

Moreover, among the plurality of electronic circuit blocks, the power supplies of the electronic circuit blocks that do not operate simultaneously are shared by one power supply and the ground pad, so that a part of the electrode extending from the pad to each mat can be shared. Therefore, the electrode occupation rate of the chip can be reduced.

Sixth, in the AM/FM stereo tuner circuit IC that adopts mat division and can significantly shorten the design period,
Connect the power supply and ground pads of the AM tuner block (28) and FM-IF block (25) to the - set of VC.
Since it is shared by CI and GNDI, the area occupied by the electrode can be reduced.

Seventh, in an IC that adopts mat division, there are two power supply pads V. The thin metal wires can be connected in parallel by connecting CI + VCCI with one end of the thin metal wire and connecting the other end to one lead. Therefore, pulse noise etc. that have entered the lead will be removed due to the low impedance.
It is not amplified significantly and can prevent fluctuations in the power supply voltage. The same applies to the ground pad.

Eighth, in an IC employing mat division, a plurality of power supply lines extending from the power supply pad to the electronic circuit blocks (mats A to D) are formed at one end in the second layer. This is similar to other electronic circuit blocks (matte NP, matte Q-
This is to cross over the power supply line extending to T). Therefore, it is possible to share the electronic circuit blocks (mats A to D) and the electronic circuit blocks (mats E to J, mats J). The same applies to the ground line side.

[Brief explanation of the drawing]

FIG. 1 is a top view showing an embodiment of the semiconductor integrated circuit of the present invention, FIG. 2A is a top view showing a mat area of the semiconductor integrated circuit of the present invention, and FIG. 2B is an A-A in FIG. 2A. 3 is a top view showing the electrode pattern of the semiconductor integrated circuit of the present invention, FIG. 4 is a block diagram of an electronic circuit incorporated in the semiconductor integrated circuit of the present invention, and FIG. 5A is an AM tuner block. Figure 5B is a diagram explaining the FM front end block and FM-IF block.
FIG. C is a diagram illustrating a multiplex decoder block, FIG. 6 is a top view of a conventional semiconductor integrated circuit, and FIG. 7 is a sectional view between block b and block C in FIG. (1)...Semiconductor chip, (2)...Divided area,
(3)...first area, (4)...second area, (5)...division line, (35), (36
), (37), (3B>...Third power supply line, (41), (42), (43)...Second ground line, (69), (70),
(71)...Second power supply line, (72), (7
3), (74)...Third ground line.

Claims (8)

[Claims] (1) A semiconductor integrated circuit in which one semiconductor chip is provided with a region in which an electronic circuit consisting of a plurality of electronic circuit blocks is formed, a plurality of power supply pads, and a plurality of ground pads, the electronic circuit comprising: It has first and second electronic circuit blocks that do not work simultaneously and a third electronic circuit block that always works, and the first and second electronic circuit blocks share a first power supply pad and a first ground pad. A semiconductor integrated circuit characterized in that the third electronic circuit block supplies power using a second power supply pad and a second ground pad. (2) The electronic circuit is an AM/FM stereo tuner circuit, the first and second electronic circuit blocks are an AM tuner block and an FM-IF block, and the third electronic circuit block is an AM/FM stereo tuner circuit. The semiconductor integrated circuit according to claim 1, which is a plex decoder block. (3) The first and second power supply pads are arranged adjacently, the first and second power supply pads are connected to one power supply lead with a thin metal wire, and the first and second ground pads are connected to one power supply lead using a thin metal wire. 2. The semiconductor integrated circuit according to claim 1, wherein the first and second ground pads are arranged adjacent to each other and the first and second ground pads are connected to one ground lead by a thin metal wire. (4) A plurality of power supply lines extending from the first power supply pad to the first electronic circuit block cross over to the second layer at one end, and a plurality of power supply lines extend to the second electronic circuit block. A plurality of ground lines connected to a power supply line and extending from the first ground pad to the first electronic circuit block cross over to a second layer at one end and extend to the second electronic circuit block. 4. The semiconductor integrated circuit according to claim 3, wherein the semiconductor integrated circuit is connected to a plurality of ground lines. (5) A semiconductor chip is formed by dividing a semiconductor chip into a plurality of regions of substantially the same size by arranging a plurality of division lines in the same direction, each of which is a set of power supply lines and ground lines extending adjacent to each other. The electronic circuit includes a mat, and an electronic circuit constituted by a plurality of electronic circuit blocks having different functions that are incorporated in an integral number of the mat areas, and the electronic circuit includes first and second electronic circuit blocks that do not work simultaneously, and a second electronic circuit block that always works. 3 electronic circuit blocks, the first and second electronic circuit blocks share a first power supply pad and a first ground pad to supply power, and the third electronic circuit block has a second electronic circuit block. A semiconductor integrated circuit characterized in that power is supplied using a power supply pad and a second ground pad. (6) The electronic circuit is an AM/FM stereo tuner circuit, and the first and second electronic circuit blocks are
6. The semiconductor integrated circuit according to claim 5, wherein the third electronic circuit block is an AM tuner block and an FM-IF block, and the third electronic circuit block is a multiplex decoder block. (7) The first and second power supply pads are arranged adjacently, the first and second power supply pads are connected to one power supply lead with a thin metal wire, and the first and second ground pads are connected to one power supply lead using a thin metal wire. 6. The semiconductor integrated circuit according to claim 5, wherein the first and second ground pads are arranged adjacent to each other and the first and second ground pads are connected to one ground lead by a thin metal wire. (8) A plurality of power supply lines extending from the first power supply pad to the first electronic circuit block cross over to the second layer at one end, and a plurality of power supply lines extend to the second electronic circuit block. A plurality of ground lines connected to the ground pad and extending from the first ground pad to the first electronic circuit block cross over to the second layer at one end and extend to the second electronic circuit block. 8. The semiconductor integrated circuit according to claim 7, wherein the semiconductor integrated circuit is connected to a plurality of ground lines.