JPH0628289B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a semiconductor integrated circuit, and more particularly to a pattern layout that can be easily expanded to meet the requirements of custom ICs, and further, mutual interference. The present invention relates to a semiconductor integrated circuit having an improved pattern layout of blocks it dislikes.

(B) Conventional Technology In general, JP-A-59-84542 (H01L 21 /
As shown in 76), the semiconductor integrated circuit technology for forming a plurality of circuit blocks on the same semiconductor substrate has the configuration shown in FIG.

FIG. 6 is a schematic plan view of the semiconductor chip (1), and a to f show circuit blocks. These circuit blocks are
The frequencies and signal levels to be handled are different, and the functions are also different.

This circuit block is a P ^- type semiconductor substrate as shown in FIG.
(2) is formed in the N-type region (3) above, and each circuit block is
It is partitioned by a high-concentration P ⁺ -type region (4) adjacent to its periphery. Here, it is shown by block b and block c.

The P ⁺ type region (4) for this partition has one end in contact with the P ⁻ type semiconductor substrate (2) and the other end ohmic-connected to the ground line (6) through the oxide film (5) on the semiconductor surface. To be done.

The ground line (6) is grouped in the center of the integrated circuit from each block, and the ground bonding pad GN at the left end
Has been extended to D.

Next, the power supply line (Vcc) of each block circuit is gathered on the outer peripheral portion of the integrated circuit and individually connected to the power supply bonding pad, as shown in FIG.

On the other hand, since the circuit blocks a to f have different functions, the number of elements existing in the block is different and the block sizes are different.

On the other hand, since electronic devices such as TV tuners and FM / AM tuners take out audio signals from RF (Radio Frequency) signals, the frequency of signals handled by each circuit block divided by function is often different. For example, with only an FM tuner for Japan, the RF signal is 76-90MHz,
Intermediate frequency signal is 10.7MHz, and 20 ~ 2000
It handles 0 Hz audio signals and a wide range of signals from 20 Hz to 90 MHz.

An example of the FM / AM tuner is shown in FIG. In the figure, (11) is an FM front end that selects an FM broadcast and frequency-converts it to an intermediate frequency by mixing the reception frequency signal and the oscillation frequency signal of the local oscillation circuit (12) with a mixing circuit (13). Circuit, (14) is an intermediate frequency signal (IF signal)
An FM / IF amplifier circuit for amplifying and limiting the amplitude of the signal and detecting the signal to obtain an audio signal (AF signal), (15) is a noise canceling circuit having a function as described in Japanese Patent Publication No. 62-21461 , (16) is a multiplex circuit for demodulating into L channel and R channel signals in the case of stereo broadcasting, and (17) is an AM tuner circuit for selecting AM broadcasting and outputting an audio signal. For example, in the case of FM broadcast reception, input from the antenna (18),
RF signal amplified by high frequency in 9) and FM front end circuit
The IF signal is output from the FM front end circuit (11) by mixing the oscillation frequency signal output from the local oscillation circuit (12) of (11) with the mixing circuit (13) of the FM front end circuit (11), The IF signal is detected by the detection circuit of the FM / IF amplifier circuit (14) to output a composite signal from the FM / IF amplifier circuit (14). The multiplex circuit (16) outputs L to the output terminal (20). It is configured to output channel and R channel audio signals.

An FM tuner circuit having such a configuration is, for example,
Issued February 10, "'88 Sanyo Semiconductor Data Book Portable Audio Bipolar Integrated Circuit Edition", No. 152
Page.

By the way, in recent years, electronic devices are required to be smaller and have higher performance, and accordingly, the circuit of FIG. 4 is being integrated into one chip as much as possible. However, in the above FM tuner example, the FM front end circuit (11) has a frequency of several tens of MHz.
Since the high frequency signal of 1 is handled, interference with other circuits easily occurs due to unnecessary radiation. Further, since the weak level signal from the antenna (18) is handled, the circuit operation is apt to become unstable due to the interference with other circuit blocks, and in a remarkable case, it oscillates. Therefore, it was extremely difficult to integrate the FM front end circuit (11) into one chip.

(C) Problems to be Solved by the Invention As described above, conventionally, it is extremely difficult to integrate the FM front end circuit (11) because circuit interference easily occurs. Also, the development period of pattern design is long,
It had a drawback that it could not meet various demands immediately.

(D) Means for Solving the Problems The present invention has been made in view of such problems, and divides the upper surface of the semiconductor chip (22) into a large number of mats having substantially the same size at the partition line ( 21 ), and at the same time, The conventional problems are solved by accommodating the non-operating electronic block circuits in one or more integer number of mats and arranging the mats alternately.

(E) Operation According to the present invention, the upper surface of the semiconductor chip (22) is divided into a large number of mats of substantially the same size by the division line ( 21 ), and an electronic block circuit having a plurality of different functions is divided into an integer number of pieces. By storing the electronic block circuit in the mat, the electronic block circuit can be designed, and the electronic block circuit can be divided into a certain number of elements to be designed for each mat. Therefore, it is possible to divide each electronic block circuit for parallel design, and it is possible to significantly reduce the design period. Further, the circuit can be changed for each electronic block circuit and for each wamut, so that the design change of the entire IC is not necessary.

Further, since the first electronic block circuit and the second electronic block circuit do not operate at the same time, when the first electronic block circuit is operating, the mat in which the second electronic block circuit is integrated has high impedance, and The ground line dedicated to the second electronic block circuit arranged on the right side of the mat is a line dedicated to sucking. On the other hand, when the second electronic block circuit is operating, the mat in which the first electronic block circuit is integrated has high impedance, and the ground line dedicated to the first electronic block circuit arranged on the right side of the mat is It will be a dedicated line for blotting.

Therefore, by alternately arranging the mats in which the circuits interfering with each other in the first electronic block circuit are separately integrated and the mats in which the second electronic block circuit is integrated are alternately arranged, the mutual interference of the separately integrated mats is achieved. Can be prevented.

(F) Example First, an example of the present invention will be described in detail with reference to FIG.

The upper surface of the semiconductor chip (22) is divided into eight mats A to H. Between the mats A to H, a power supply line (23) and a ground line (24) are divided by a partition line ( 21 ) which is adjacently extended in parallel.

The arrangement of the power supply line (23) and the ground line (24) forming the division line ( 21 ) is such that the power supply line (23) shown by a solid line is provided on the left side of each mat A to H and the ground line (shown by a dashed line) on the right side. 24) is provided. Therefore, only the partition lines of the mats on both ends are the power line (23) or ground line (24).
Is formed on the one hand, and the intermediate division line is constituted by both. The power supply line (23) and the ground line (24) adjacent to each of the mats A to H are integrated in each mat and supply power to the circuit blocks.

Further, the power supply line (23) and the ground line (24) of each partition line ( 21 ) are connected in a comb-teeth shape by a line indicated by a chain double-dashed line. First supply line (25), the mat A, and C of the power supply line (23), the first supply line (26) is arranged in the mat B, the power supply line and the comb-shaped and D, the power supply pad V _cc1 More extended in parallel. First supply line (27) is mat E, G
The power supply line and the first supply line (28) are mats F and H
_Are arranged in a comb shape with the power supply line and extend in parallel from the power supply pad V _cc2 .

On the other hand, the second supply line (29) is the ground line (24) of the mats A and C, and the second supply line (30) is the mat B,
It is arranged in a comb shape with the D ground line (24) and extends in parallel from the ground pad GND1. Second supply line
(31) is arranged with the mats E and G, and the second supply line (32) is arranged with the mats F and H in a comb shape, and extends in parallel from the ground pad GND2.

The power supply line (23), ground line (24), first supply lines (25), (26), (27), (28) and second supply line
(29), (30), (31), (32) are in principle one of the two-layer wiring.
It is realized by layer wiring and partially crosses over the crossing area.

Mats A to H divided by the division line ( 21 ) described above
Are formed to have substantially the same size, and specifically, the width is set so that 6 NPN transistors are arranged, and the length is a fixed number of elements which is easy to design, for example, about 10
It is set so that 0 elements can be laid out. The size of the mat can be arbitrarily selected depending on the number of elements that can be easily designed, depending on the electronic block circuit to be integrated into an IC.

The circuit element integrated in the mat is composed of a transistor, a diode, a resistor and a capacitor and is separated by a normal PN separation, and the wiring of each element is connected by a first electrode layer of a two-layer wiring. The electrodes are crossed over at the second layer.

Next, with reference to FIGS. 2A and 2B, the circuit elements and partition lines ( 21 ) integrated in the mat will be specifically described.

FIG. 2A is an enlarged top view of the vicinity of the mat B. The partition line ( 41 ) shown by the left-hand dashed line is the partition line ( 21 ) provided between the mat A and the mat B, and the partition line ( 42 ) shown by the right-hand dashed line is the mat B and the mat. It is a division line ( 21 ) provided between C. And this division line
Between ( 41 ) and ( 42 ), the transistor (43) indicated by the dotted line,
A diode (44), a resistor (45) and a capacitor (46) are integrated. Although these elements are rough in the drawing, they are actually densely integrated. The wiring between the elements in the mat is substantially formed by the first electrode layer (47) indicated by the alternate long and short dash line.
The wiring between the mat of the mat C and the mat of the mat C, for example, the signal line and the feedback line are formed by the second electrode layer (48) shown by the solid line. The first and second electrode layers (47) and (48) are connected to each other by the contact regions indicated by the cross marks.

2B is a sectional view taken along the line AA ′ in FIG. 2A. N type epitaxial layer on P type semiconductor substrate (49)
(50) are stacked, and the P ⁺ -type isolation region (51) reaching the semiconductor substrate (49) from the surface of the epitaxial layer (50)
Are formed, and a large number of island regions are formed.
Within this island region (52) are NPN transistors (4
3), a diode (44), a resistor (45), a capacitor (46), etc. are made, and an N ⁺ type is provided between the collector region (53) of the NPN transistor (43) and the semiconductor substrate (49). Embedded regions (54) are formed. A silicon oxide film (55) is formed on the surface of the epitaxial layer (50) by, for example, a CVD method, and a first electrode layer (47) is formed on the silicon oxide film (55). . In addition, this first electrode layer
An insulating film (56) made of high heat-resistant fine polymer for semiconductors such as PIX sold as a product by Hitachi Chemical Co., Ltd. is formed so as to cover (47), and this insulating film (56)
A second electrode layer (48) is formed thereon. In addition, the power line (57) and the ground line (58) are
The ground line (58) is provided above (51) and this isolation area is
It is in ohmic contact with (51) to stabilize the substrate potential.

Next, it will be described how to integrate the mat. First, book I
The electronic circuit of C has a first electronic block circuit and a second electronic block circuit that do not operate simultaneously. The first and second electronic block circuits are divided into a plurality of pieces with a predetermined number of elements as a guide, and are integrated in each mat. For example, each of them is integrated in four mats, and as shown in FIG. 1, the first electronic block circuit is arranged in the mats A, C, E and G and the second electronic block circuit is arranged in the second mat.
The electronic block circuit of is integrated on the mats B, D, F and H,
They are arranged alternately. Further, the circuits interfering with each other in the first electronic block circuit are integrated in separate mats, and the circuits interfering with each other in the second electronic block circuit are also integrated in separate mats.

As described above, since the first and second electronic block circuits do not operate at the same time, when the first electronic block circuit is operating, the second electronic block circuit is stopped and the mats B, D, F, H has a high impedance. Therefore, the mutual interference between the mats A and C is caused by the high impedance mat B.
The mutual interference between the mats C and E can be suppressed by the high impedance mat D, and the mutual interference between the mats E and G can be suppressed by the high impedance mat F.

On the other hand, when the second electronic block circuit is operating, the first electronic block circuit is stopped and the mats A, C,
E and G have high impedance. Therefore, mutual interference between the mats B and D, the mats D and F, and the mats F and H can be suppressed by the mats C, E, and G having high impedance, respectively.

In addition, the stopped block itself becomes a huge junction-type capacitance, removing high-frequency noise. This is Fig. 2B
It is formed of an N type epitaxial layer (50) and a P ⁺ type isolation region (51), an N type epitaxial layer (50) and a P type semiconductor substrate (49) in the sectional view shown in FIG. Therefore, even if high frequency noise enters the semiconductor substrate (49) from each of the mats A and C, since the huge junction type capacitance exists in the mat B, this high frequency noise is applied to the mat B. It is sucked by the line (57) to prevent mutual interference between the mat A and the mat C. The same applies to the mats C and E and the mats E and G.

In addition, the ground line dedicated to the mat is on the right side of the mat.
Since (58) is in ohmic contact with the isolation region (51) reaching the semiconductor substrate (49), it is possible to absorb the leak current flowing out to the semiconductor substrate (49).

Further, the power supply line (23) of the mats A and C is extended in parallel with the power supply line (23) of the mats B and D from the power supply pad _Vcc1 via the first supply lines (25) and (26). Therefore, the voltage fluctuation occurring in the power line of the mat A is not directly transmitted to the power line of the mat B. The same applies to _Vcc2 , GND1 and GND2.

Next, the relationship between the electronic block circuit incorporated in this configuration and the mat will be described. As an example, FM / AM shown in FIG.
Use the tuner to explain. Here, the first electronic block circuit is an FM tuner circuit, and the FM front end block (1
1) and the FM-IF block (14) were divided into mats A and C and mats E and G, respectively. The second electronic block circuit is the AM tuner circuit (17) shown in FIG. 5, which includes the high frequency amplifier circuit RF (61), the mixing circuit MIX (62) and the local oscillator circuit OSC (63). -RF block
( 64 ), intermediate frequency amplifier circuit IF (65) and detection circuit DET (6
It is divided into an AM-IF block ( 67 ) including 6), and these two blocks ( 64 ) and ( 67 ) are respectively mats B and D and mats F and H.
Accumulated in. Since each block has a different number of elements, the number of elements integrated in the mat is also different.
D, F and H are sparser than the mats A, C, E and G.

In this IC, FM front end block (11) and FM-I
Mutual interference of the F block (14) is the most problematic, so it was divided into mats A and C and mats E and G. Therefore, for noise that enters mats E and G from mats A and C, mat B
And D become high impedance barriers, and mat D is used to prevent noise from entering mats A and C from mats E and G.
And F are high impedance barriers.

On the other hand, considering the ground line, the leak currents that enter the mats E and G from the mats A and C are absorbed by the ground lines of the mats B and D, and the matte A and C are absorbed by the mats E and G.
The leak current that enters into can be absorbed by the ground lines of the mats D and F.

FIG. 3 shows another embodiment in which the FM front end block (11) is the mats A and B, the FM-IF block (14) is the mats E and F, and the AM-RF block ( 64 ) is the mat C. D
Then, the AM-IF block ( 67 ) was integrated on the mats G and H. Also in this embodiment, two mats are alternately arranged, and the same effect as the previous embodiment is obtained.

(G) Effect of the invention As is apparent from the above description, firstly, the dividing line ( 21 )
By dividing the upper surface of the semiconductor chip (22) into a large number of mats of substantially the same size and accommodating a plurality of electronic block circuits having different functions in an integer number of mats, it is possible to design in parallel for each electronic block circuit, The design period can be greatly shortened. Further, since the electronic block circuit is divided by a fixed number of elements and the design for each mat can be performed, the parallel design for each mat can also be performed. Further, since circuit changes such as deletion, addition and correction can be designed for each electronic block circuit or each block, only the change for each block or each mat is sufficient, and the design change of the entire IC is not necessary. Furthermore, since the mat can be made into a cell as a basic block, once the design is completed, other mats can be used as they are, and the reliability can be improved very much by modifying only the mat to be changed when the circuit is changed thereafter.

Second, the first electronic block circuit and the second electronic block circuit, which do not operate simultaneously, are each divided into a plurality of pieces and integrated on a mat, and the mats integrated on the first and second electronic block circuits are alternately arranged. The circuits arranged and averse to each other in the first and second electronic block circuits are integrated into separate mats. Therefore, in one of the electronic block circuits, a mat in which the other electronic block circuit is integrated is provided between the mat and the mat which have a circuit that dislikes mutual interference, and when one of the electronic block circuits is operating. , The sandwiched mat has a high impedance because the circuit is stopped. Therefore, the mats adjacent to both sides of this high impedance mat can prevent mutual interference.

Moreover, this high-impedance mat separates the adjacent mats on both sides, so that mutual interference can be further prevented. Also, on the right side of this high impedance mat,
Since the ground line (24) in ohmic contact with the isolation region (51) is formed, it is possible to absorb the leak current flowing to the substrate (49).

Furthermore, when the second electronic block circuit is operating, the mat on which the second electronic block circuit is integrated and the ground line on the side of the mat function as a part of the circuit, and the first electronic block When the circuit is operating, the mat in which the second electronic block circuit is integrated has a high impedance, and the ground line functions as a suction line, so that two functions are performed. The same is true for the opposite case.

Second, connect the power line (23) and ground line (24) to two.
By forming on the first electrode layer (47) of the layer wiring structure, wiring with the elements to be laid out in the mat can be performed substantially on the first electrode layer (47), so that wiring between the mats , The wiring of the signal line can be integrated in the second electrode layer (48), and the design becomes very simple.

Thirdly, the circuit block is composed of at least various circuit elements having different shapes such as a transistor, a diode, a resistor, and a capacitor. However, by unifying the mat into a certain size that facilitates integration, Designing is easy because the entire layout is made useless by simply arranging the elements.

Fourthly, the power supply line (23) and the ground line (24) and the first supply lines (25), (26), (2) provided on the sides of the mat.
7), (28) and the second supply line (29), (30), (31), (3
2) and the semiconductor chip (22)
It is possible to connect the power supply pad and the ground pad provided at the shortest distance.

Fifthly, since the wiring between the elements housed in the mat is formed in the first layer in principle, the wiring between the mats and the electronic block circuits that cross the division line ( 21 ) should be in the second layer. It can be used, and the wiring between the elements in the mat and the wiring between the mats or between the electronic block circuits can be distinguished and designed, and the design becomes extremely easy.

[Brief description of drawings]

FIG. 1 is a top view of the semiconductor integrated circuit of the present invention, FIG. 2A is a top view showing a mat area of the semiconductor integrated circuit of the present invention, and FIG. 2B is a cross section taken along the line AA ′ of FIG. 2A. 3 and 4 are top views of the semiconductor integrated circuit of the present invention, and FIG. 4 is FM / A.
FIG. 5 is a block diagram showing an M tuner, FIG. 5 is a block diagram showing an AM tuner block shown in FIG. 4, FIG. 6 is a top view of a conventional semiconductor integrated circuit, and FIG. 7 is a block diagram showing a block b and a block c in FIG. FIG. ( 21 ) …… Compartment line, (22) …… Semiconductor chip, (23) ……
Power line, (24) …… Grand line, (25), (26), (2
7), (28) ... first supply line, (29), (30), (31), (3
2) …… Second supply line, (43) …… Transistor, (44)
…… Diode, (45) …… Resistance, (46) …… Capacitor,
(47) …… first layer electrode layer, (48) …… second layer electrode layer, (49) …… semiconductor substrate, (50) …… epitaxial layer,
(51) …… Separation area, (52) …… Island, (54) …… Embedded area, (55), (56) …… Insulating film.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04B 15/02 9298-5K

Claims (10)

[Claims] 1. A semiconductor chip is divided into a plurality of regions of substantially the same size by arranging a plurality of partition lines, which are adjacent to each other and extend as a set of a power supply line and a ground line, in the same direction. A formed mat and an electronic circuit configured by a plurality of electronic block circuits having different functions incorporated in the semiconductor chip, wherein the electronic circuits are a first electronic block circuit and a second electronic block circuit that do not operate simultaneously. At least, and an integer number of mats obtained by dividing the first electronic block circuit into a plurality of pieces and integrating them and n pieces of matting obtained by dividing the second electronic block circuit into a plurality of pieces and alternately arranged. A semiconductor integrated circuit characterized by. 2. The semiconductor integrated circuit according to claim 1, wherein the power supply line and the ground line are formed in the first layer of the two-layer wiring structure. 3. The semiconductor integrated circuit according to claim 1, wherein the circuit block includes at least a bipolar transistor, a diode, a resistor and a capacitor. 4. A power supply line is provided on one side of a plurality of mats, and extends in a comb shape from a first supply line provided on one side of the semiconductor chip. A plurality of ground lines are provided. Is provided on the other side of the mat
2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit extends in a comb shape from a second supply line provided on the other side of the semiconductor chip. 5. The wiring in the mat is formed substantially in the first layer, and the wiring between the mat and the mat and the electronic block circuit and the electronic block circuit is formed in the substantially second layer. 2. The semiconductor integrated circuit according to item 1. 6. A plurality of partition lines extending adjacently as a set of a power line and a ground line are arranged in the same direction to divide a semiconductor chip into a plurality of regions of substantially the same size. The formed mat and the electronic circuit configured by a plurality of electronic block circuits having different functions incorporated in the semiconductor chip are provided, and the electronic circuit has at least an AM tuner block circuit and an FM tuner block circuit that do not operate simultaneously. A semiconductor integrated circuit is characterized in that a mat in which the AM tuner block circuit is divided into a plurality of pieces and integrated, and a mat in which the FM tuner block circuit is divided into a plurality of pieces and is integrated are arranged alternately. 7. The semiconductor integrated circuit according to claim 6, wherein the power supply line and the ground line are formed on the first layer of the two-layer wiring structure. 8. The semiconductor integrated circuit according to claim 6, wherein the circuit block includes at least a bipolar transistor, a diode, a resistor and a capacitor. 9. A power supply line is provided on one side of a plurality of mats, and extends in a comb shape from a first supply line provided on one side of a semiconductor chip. A plurality of ground lines are provided. Is provided on the other side of the mat
7. The semiconductor integrated circuit according to claim 6, wherein the semiconductor integrated circuit extends in a comb shape from a second supply line provided on the other side of the semiconductor chip. 10. The wiring in the mat is formed substantially in the first layer, and the wiring between the mat and the mat and the electronic block circuit and the electronic block circuit is formed in the substantially second layer. 6. A semiconductor integrated circuit according to item 6.