JPH0251253A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To shorten the design time by dividing the upper surface of a semiconductor chip into many mats of the same size with sectioning lines, and arranging alternately one or more integral number of the mats after incorporating electronic block circuits not operating simultaneously within integral number of mats. CONSTITUTION:The upper surface of a semiconductor chip 22 is divided into many mats of the same size with sectioning lines 21 and a plurality of electronic block circuits of different functions are contained in the integral number of the mats. First and second electronic block circuits which do not operate simultaneously are divided into a plurality of pieces each and integrated in the mats, which are arranged alternately. Circuits which detest mutual interference in the first and second electronic block circuits are integrated in separate mats. When the second electronic block circuits operate, the mats in which the second electronic block circuits are integrated and the ground lines therearound are made to function as a part of the circuits. When the first electronic block circuits operate, the impedance of the mats in which the second electronic circuits are integrated becomes high and the ground lines are made to act as absorption lines. This enables shortening the design time and preventing mutual interference of the integrated mats.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to semiconductor integrated circuits, and in particular, relates to pattern layouts that allow for easy model development in order to meet the demands of custom ICs, and furthermore, to avoid mutual interference. This invention relates to a semiconductor integrated circuit with improved block pattern layout.

(b) Conventional technology in general is disclosed in Japanese Patent Application Laid-Open No. 59-84542 (HOI L
21/76), a semiconductor integrated circuit technology in which a plurality of circuit blocks are formed on the same semiconductor substrate has the configuration shown in FIG.

FIG. 6 is a schematic plan view of the semiconductor chip (1), and a
thru r indicate circuit blocks. These circuit blocks handle different frequencies and signal levels, and also have different functions.

This circuit block is formed in an N-type region (3) on a P-type semiconductor substrate (2) as shown in FIG. 7, and each circuit block is formed in a high concentration P1-type region ( 4)
It is divided into construction zones. Here, block b and block C are shown.

One end of the P+ type region (4) for this division is in contact with the P- type semiconductor substrate (2), and the other end is ohmically connected to the ground line (6) through the oxide film (5) on the semiconductor surface. Ru.

A ground line (6) is gathered from each block to the center of the integrated circuit and extends to the ground bonding pad GND at the left end.

Next, as shown in FIG. 6, the power supply lines (VCC) of each block circuit are grouped around the outer periphery of the integrated circuit and individually connected to power supply bonding pads.

On the other hand, since the circuit blocks a to f have different functions, the number of elements present in each block is different, and the block sizes are different.

On the other hand, electronic devices such as TV tuners and FM/AM tuners extract audio signals from RF (Radio Frequency) signals, so the frequency of signals handled by each circuit block divided by function is often different.
For example, an FM tuner for Japan only has an RF multiplied signal of 76 to 90 MHz and an intermediate frequency signal of 10.7 MHz.
, and an audio signal of 20-20000Hz, 2
A wide range of signals from 0Hz to 90MHz will be handled.

An example of the above FM/AM tuner is shown in FIG. In the figure, (11) is an FM front end that selects an FM broadcast and converts the frequency into an intermediate frequency by mixing the received frequency signal and the oscillation frequency signal of the local oscillation circuit (12) in the mixing circuit (13). The circuit (14) is an FM-IF amplification circuit that amplifies and limits the amplitude of an intermediate frequency signal (IF multiplied signal, and detects it to obtain an audio signal (AF multiplied signal); a noise canceling circuit having functions as described in
(16) is a multiplex circuit that demodulates L channel and R channel signals in the case of stereo broadcasting, and (17) is an AM tuner circuit that selects AM broadcasting and outputs an audio signal.0For example, in the case of FM broadcast reception, antenna(
The RF multiplied signal input from 18) and high-frequency amplified by the RF amplifier circuit (19) is mixed with the oscillation frequency signal output by the local oscillation circuit (12) of the FM front-end circuit (11). IF from the FM front end circuit (11) by mixing in the circuit (13).
The IF multiplied signal FM-IF amplification circuit (14
), the composite signal is output from the FM-IF amplifier circuit (14), and the multiplex circuit (16) outputs L channel and R channel audio signals to the output terminal (20), respectively. It is configured.

In addition, an FM tuner circuit with a refusal configuration is, for example, 1986 1.
Published on February 10th, "88 Sanyo Semiconductor Data Book Bipolar Integrated Circuits for Portable Audio Edition" No. 152
It is written on the page.

Incidentally, electronic devices in recent years are required to be more and more compact and high-performance, and accordingly, the circuit shown in FIG. 4 is being made into a single chip as much as possible. However, in the example of the FM tuner described above, since the FM front end circuit (11) handles high frequency signals of several tens of MHz, interference with other circuits is likely to occur due to unnecessary radiation.

In addition, since the weak level signal from the antenna (18) is handled, the circuit operation tends to become unstable due to interference with other circuit blocks, and in severe cases, oscillation occurs.
It was extremely difficult to incorporate the M front end circuit (11) into a single chip.

(c) Problems to be Solved by the Invention As described above, conventionally there has been a drawback that it is extremely difficult to integrate the FM front end circuit (11) because circuit interference is likely to occur. In addition, the development period for pattern design was long, and there was a drawback that it was not possible to immediately respond to various requests.

(d) Means for solving the problem The present invention has been made in view of the problem,
), the upper surface of the semiconductor chip (22) is divided into a large number of mats of substantially the same size, electronic block circuits that do not operate simultaneously are accommodated in each of one or more integral number of mats, and the mats are arranged alternately. By doing so, the conventional problems can be solved.

(E) Effect According to the present invention, semiconductor chips (2
2) By dividing the top surface into a large number of mats of substantially the same size and accommodating a plurality of electronic block circuits with different functions within an integral number of mats, it is possible to design each electronic block circuit and It becomes possible to design each mat by dividing it into a fixed number of elements. Therefore, each electronic block circuit can be divided and designed in parallel, and the design period can be significantly shortened. Furthermore, since circuit changes can be made for each electronic block circuit and for each mat, there is no need to change the design of the entire IC.

Furthermore, since the first electronic block circuit and the second electronic block circuit do not operate simultaneously, when the first electronic block circuit is in operation, the mat in which the second electronic block circuit is integrated has a high impedance, and this The ground line dedicated to the second electronic block circuit placed on the right side of the mat is a line dedicated to absorbing. On the other hand, when the second electronic block circuit is operating, the mat in which the first electronic block circuit is integrated has a high impedance, and the ground line dedicated to the first electronic block circuit placed on the right side of this mat is This is a line exclusively for blotting.

Therefore, by alternately arranging mats in which circuits that cause mutual interference in the first electronic block circuit are separately integrated and mats in which the second electronic block circuit is integrated, the mutual interference between the separately integrated mats can be avoided. can be stopped.

(f) Example First, an embodiment of the present invention will be described in detail with reference to FIG.

The upper surface of the semiconductor chip (22) is divided into eight mats A to H. There is a power line (2
3) and the ground line (24) are separated by a partition line (21) extending in parallel and adjacent to each other.

The arrangement of the power line (23) and ground line (24) forming the division line (21) is such that the power line (23) shown by a solid line is provided on the left side of each mat A-H, and the ground line (23) shown by a dashed line is provided on the right side. 24) is provided. Therefore, only the division line of the mat at both ends is the power line (23)
Alternatively, one of the ground lines (24) is formed, and the intermediate partition line is formed of both. Each mat A-H
The power line (23) and ground line (23) adjacent to
24) is integrated in each mat and supplies power to the circuit blocks.

Further, the power supply line (23) and the ground line (24) of each division line (21) are connected in a comb-teeth shape by a line shown by a two-dot chain line. The first supply line (25) is connected to the power supply line (23) of mats A and C, and the first supply line (
26) are arranged in a comb shape with the power lines of mats B and D,
It extends in parallel from the power supply pad vect. The first supply line (27) is arranged in a comb shape with the power supply line of mats E and G, and the first supply line (28> is arranged in a comb-like shape with the power supply line of mats F and H, and is connected in parallel from the power supply pad V.C1. It has been extended.

On the other hand, the second supply line (29) is arranged in a comb shape with the ground line (24) of mats A and C, and the second supply line (30) is arranged with the ground line (24) of mats B and D. and is extended in parallel from the ground pad GNDI. The second supply line (31) is connected to the mats E, G and the second supply line (31).
The supply lines (32) are arranged in a comb-teeth pattern with the mats F and H, and extend in parallel from the ground pad GND2.

The power supply line (23), the ground line (24), the first supply line (25), (26), (27)
, (28) and a second supply line (29),
(30), (31), (32) are basically 2
It is realized by one layer wiring of the layer wiring, and partially crosses over the intersecting area.

Each mat A- that can be divided by the above-mentioned division line (21)
H is formed into a shape of substantially the same size, specifically, the width is set so that NPN)-rangistaro pieces are lined up, and the length is set to a certain number of elements that is easy to design, for example, about 100. The settings are set so that the elements can be laid out.

The size of this mat can be arbitrarily selected depending on the number of elements that can be easily designed, depending on the electronic block circuit to be integrated.

The circuit elements integrated within the mat are composed of transistors, diodes, resistors, and capacitors, separated by normal PN isolation, and the connections of each element are connected by the first electrode layer of the two-layer wiring. are crossed over with the second layer of electrodes.

Next, with reference to FIGS. 2A and 2B, the circuit elements integrated within the mat and the partition lines will be specifically described.

FIG. 2A is an enlarged top view of the vicinity of mat B.

The division line (41) indicated by the dashed line on the left is mat A.
It is a division line (fu) provided between and mat B,
The division line (21) indicated by the dashed line on the right is the division line (21) provided between mat B and mat C.

Between the partition lines (41) and (42), there is a transistor (43) and a diode (4) indicated by dotted lines.
4), a resistor (45) and a capacitor (46) are integrated. Although these elements are rough in the drawing,
In reality, they are highly concentrated. Further, the wiring between elements within the mat is substantially formed by the first electrode layer (47) shown by the - dotted chain line, and the wiring between mat A, mat B, and mat B
The wiring between mats C and C, such as signal lines and feedback lines, is the second electrode layer (48
) is formed. These first and second electrode layers (47) and (48) are connected through contact regions indicated by X marks.

FIG. 2B is a sectional view taken along line AA' in FIG. 2A. An N-type epitaxial layer (50) is laminated on a P-type semiconductor substrate (49), and this epitaxial layer (
50) P'' reaching the semiconductor substrate (49) from the surface
'' type isolation region (51) is formed, and a number of island regions are formed.In this island region (52), an NPN transistor (43) and a diode (44) are formed.
), a resistor (45), a capacitor (46), etc. are made, and an N1 type buried region (54) is formed between the collector region (53) of the NPN I-transistor (43) and the semiconductor substrate (49). ) is formed. A silicon oxide film (55) is formed on the surface of the epitaxial layer (50) by, for example, the CVD method.
55>, a first electrode layer (47) is formed. Further, an insulating film (56) such as PIX is formed to cover this first n-th electrode layer (47), and a second electrode layer (48) is formed on this insulating film (56). ing. Further, a power supply line (57) and a ground line (58) are provided on the isolation region (51), and the ground line (58) is in ohmink contact with this isolation region (51), thereby stabilizing the substrate potential. is being measured.

Next, we will discuss how to accumulate on the mat.

First, the electronic circuit of this IC has a first electronic block circuit and a second electronic block circuit that do not operate simultaneously. The first and second electronic block circuits are divided into a plurality of parts using a predetermined number of elements as a guide, and are integrated into each mat.
For example, each of the first electronic block circuits is integrated into four mats, and as shown in FIG.
Second electronic block circuits are integrated on mats B, D, F, and H and arranged alternately. Furthermore, circuits that interfere with each other in the first electronic block circuit are integrated on separate mats, and circuits that interfere with each other in the second electronic block circuit are also integrated on separate mats.

As mentioned above, the first and second electronic block circuits do not operate at the same time, so when the first electronic block circuit is operating, the second electronic block circuit is in the IF state, and the mats B, D, and F , H have high impedance. Therefore, the mutual interference between mats A and C is due to the high impedance mat B.
Mutual interference between the mats C and E can be suppressed by the high-impedance mat D, and mutual interference between the mats E and G can be suppressed by the high-impedance mat F.

On the other hand, when the second electronic block circuit is operating, the first electronic block circuit is stopped and mats A, C,
E and G have high impedance. Therefore mats B and D
Mutual interference between F1 mat D and F1 mats F and H can be suppressed by high impedance mats C, E, and G, respectively.

In addition, the stopped block itself becomes a huge junction type capacitor, which removes high frequency noise. This is shown in Figure 2B.
N-type epitaxial layer (50) and P+ in the cross-sectional view shown in
type isolation region (51), N type epitaxial layer (50
) and a P-type semiconductor substrate (49). Therefore, even if high-frequency noise intrudes into the semiconductor substrate (49) from each of the mats L-A and C, this high-frequency noise will not be applied to the mat B because the huge junction type capacitance is present in the mat B. It is absorbed by the power supply line (57), which prevents mat A and mat C from interfering with each other. The same applies to mats C and E, mats E and G, etc. below.

Furthermore, on the right side of the mat, there is a ground line (58) dedicated to the mat, and a separation area (58) that reaches the semiconductor substrate (49).
Since it is in ohmic contact with the semiconductor substrate (49), leakage current flowing into the semiconductor substrate (49) can be absorbed.

Moreover, the power supply lines 23) of mats A and C are connected in parallel with the power supply lines 23) of mats B and D, and the first supply line (
25) and (26) from the power supply pad VCCI, voltage fluctuations occurring in the power supply line of mat A are not directly transmitted to the power supply line of mat B.

The same can be said of Vcc, GNDI, and GND2.

Next, the relationship between the electronic book circuit incorporated in this configuration and the mat will be described. - FM/AM as shown in Figure 4 as an example
Explain using a tuner. Here, the first electronic block circuit is an FM tuner circuit, and this FM tuner circuit is connected to the FM front end block (
11) and FM-IF block (14), and were integrated into mats A and C and mats E and G, respectively. The second electronic block circuit is an AM tuner circuit (17) shown in FIG. -RF block <64) and AM-IF block (67) including an intermediate frequency amplification circuit IF (65) and a detection circuit DET (66), and these two blocks (64).

(67) were integrated into mats B and D, and mats F and H, respectively.Since each block has a different number of elements, the number of elements integrated into each mat also differs, and here, mats B, D, F, and H are integrated into mat A , C, E, and G.

This IC uses the FM front end block (11) and the FM front end block (11).
- Since the mutual interference of the IF blocks (14) is the biggest problem, they are divided into mats A and C1 and mats E and G.

Therefore, mats B and D act as high impedance barriers for noise that enters mats E and G from mats A and C, and mat D acts as a barrier for noise that enters mats A and C from mats E and G. and F act as a high impedance barrier.

On the other hand, considering the ground line, leakage current that enters mats E and G from mats A and C is absorbed by the ground lines of mats B and D, and leakage current that enters mats A and G from mats E and G is
The leakage current that enters can be absorbed by the ground lines of mats D and F.

FIG. 3 shows another embodiment, in which the FM front end block (11) is placed on mats A and B, and the FM-IF block (
14) to mats E and F, AM-RF block (64)
were integrated into mats C and D, and AM-IF blocks (67) were integrated into mats G and H. This embodiment also has two mats arranged alternately, and has the same effect as the previous embodiment.

(G) Effects of the invention As is clear from the above explanation, the first effect is the partition line (2
In 1), if the top surface of the semiconductor chip (22) is divided into many mats of substantially the same size and electronic block circuits with different functions are housed in an integral number of mats, each electronic block circuit can be designed in parallel. This can significantly shorten the design period. In addition, the electronic block circuit is divided into a certain number of elements,
Since you can design each mat, you can also design each mat in parallel. Further, since circuit changes such as deletion, addition, and modification can be designed for each electronic block circuit or each block, it is sufficient to change each block or each mat, and there is no need to change the design of the entire IC. Furthermore, since mats can be made into cells as basic blocks, once the design is completed, when changing the circuit afterwards, only the mats to be changed need to be modified, and the other mats can be used as is, resulting in extremely high reliability.

Second, the first electronic block circuit and the second electronic block circuit, which do not operate simultaneously, are each divided into a plurality of parts and integrated into a mat, and the mats integrated into the first and second electronic block circuits are alternately arranged. Circuits that are arranged and that do not want to interfere with each other in the first and second electronic block circuits are integrated on separate mats, respectively. Therefore, in one electronic block circuit, between the mats having circuits that dislike mutual interference, there is a mat in which the other electronic block circuit is integrated, and furthermore, when one electronic block circuit is operating, Since the circuit of the sandwiched mat is stopped, the impedance becomes high. Therefore, mats adjacent on both sides of this high-impedance mat can prevent mutual interference.

Moreover, since this high impedance mat separates adjacent mats on both sides, mutual interference can be further prevented. Further, on the right side of this high-impedance mat, a gelland ink 24) is formed in ohmic contact with the separation region (51), so that leakage current flowing to the substrate (49) can be absorbed.

Furthermore, when the second electronic block circuit is operating, the mat on which the second electronic block circuit is integrated and the ground line on its side function as part of the circuit, and the first electronic block When the circuit is in operation, the mat on which the second electronic block circuit is integrated has a high impedance, and the ground line acts as a suction line, thus performing two functions. The same applies to the opposite case.

Second, the power line (23) and the ground line (2
By forming 4) on the first electrode layer (47) of the two-layer wiring structure, wiring with the elements laid out in the mat can be substantially performed using the first electrode layer (47).
The wiring between the mats and the signal line are connected to the second electrode layer (48
), making the design extremely simple.

Thirdly, a circuit block is composed of circuit elements of various shapes such as transistors, diodes, resistors, and capacitors, but by standardizing the mat to a certain size that is easy to integrate, it is possible to Design is facilitated because the overall layout is unnecessary just by arranging the elements.

Fourth, the power line (23) and ground line (24) provided on the side of the mat, and the first supply line (25)
, (26), (27), (28) and the second supply line (29), (30), (31)
, (32) in a comb-teeth shape, the power supply pad and ground pad provided on the semiconductor chip (22) can be connected by the shortest distance.

Fifth, since wiring between elements housed within a mat is, in principle, formed on the first layer, wiring between mats and between electronic block circuits beyond the partition line (21) is
Layers can be used, and wiring between elements within a mat and wiring between mats or electronic block circuits can be distinguished and designed, making the design extremely easy.

[Brief explanation of the drawing]

FIG. 1 is a top view of a semiconductor integrated circuit of the present invention, FIG. 2A is a top view showing a matte region of the semiconductor integrated circuit of the present invention, and FIG. 2B is a cross section taken along line AA' in FIG. 2A. 3 is a top view of the semiconductor integrated circuit of the present invention, and FIG. 4 is an FM/A
5 is a block diagram showing the AM tuner block of FIG. 4, FIG. 6 is a top view of a conventional semiconductor integrated circuit, and FIG. 7 is a block diagram of block b and block C in FIG. 6. FIG. (21)...Division line, 22)...Semiconductor chip, (23)...Power line, (24)...Ground line, (25), (26), (27)
, (2g)...first supply line, (29) ,
(30), (31), (,32)...Second supply line, <43)...Transistor, (44
〉...Diode, ku45〉...Resistor, (4
6)...Capacitor, (47>...First layer electrode layer, (4a)...Second layer M layer, (49)
...Semiconductor substrate, <50)...Epitaxial layer, (51)...Isolation region, (52)...Island, (54)...Buried region, (55), (56)...・Insulating film.

Claims (10)

[Claims] (1) A semiconductor chip is formed by dividing a semiconductor chip into a plurality of regions of substantially the same size by arranging a plurality of division lines in the same direction, each of which is a set of power supply lines and ground lines extending adjacent to each other. a mat, and an electronic circuit including a plurality of electronic block circuits having different functions that are incorporated into the semiconductor chip, and the electronic circuit includes at least a first electronic block circuit and a second electronic block circuit that do not operate simultaneously. The first electronic block circuit is divided into a plurality of parts and an integral number of mats are integrated, and the second electronic block circuit is divided into a plurality of parts and integrated, and an integral number of mats are arranged alternately. Semiconductor integrated circuit. (2) The semiconductor integrated circuit according to claim 1, wherein the power supply line and the ground line are formed in the first layer of a two-layer wiring structure. (3) The semiconductor integrated circuit according to claim 1, wherein the circuit block includes at least a bipolar transistor, a diode, a resistor, and a capacitor. (4) The power supply line is provided on one side of the plurality of mats and extends in a comb-like shape from the first supply line provided on one side of the semiconductor chip, and the ground line is provided on one side of the plurality of mats. provided on the other side of the
2. The semiconductor integrated circuit according to claim 1, wherein the second supply line extends in a comb-teeth shape from the second supply line provided on the other side of the semiconductor chip. (5) The wiring within the mat is substantially formed in the first layer,
2. The semiconductor integrated circuit according to claim 1, wherein the wiring between the mats and between the electronic block circuits is substantially formed in the second layer. (6) A semiconductor chip is formed by dividing a semiconductor chip into a plurality of regions of substantially the same size by arranging a plurality of division lines in the same direction, each of which is a set of power supply lines and ground lines extending adjacent to each other. a mat, and an electronic circuit configured of a plurality of electronic block circuits with different functions incorporated in the semiconductor chip, the electronic circuit having at least an AM tuner block circuit and an FM tuner block circuit that do not operate simultaneously, A semiconductor integrated circuit characterized in that a mat in which the AM tuner block circuit is divided into a plurality of parts and integrated therein, and a mat in which the FM tuner block circuit is divided into a plurality of parts and integrated therein are arranged alternately. (7) The semiconductor integrated circuit according to claim 6, wherein the power supply line and the ground line are formed in the first layer of a two-layer wiring structure. (8) The semiconductor integrated circuit according to claim 6, wherein the circuit block includes at least a bipolar transistor, a diode, a resistor, and a capacitor. (9) The power supply line is provided on one side of the plurality of mats and extends in a comb-like shape from the first supply line provided on one side of the semiconductor chip, and the ground line is provided on one side of the plurality of mats. provided on the other side of the
7. The semiconductor integrated circuit according to claim 6, wherein each of the second supply lines extends in a comb-teeth shape from the second supply line provided on the other side of the semiconductor chip. (10) The wiring within the mat is substantially formed in the first layer, and the wiring between mats and between electronic block circuits is substantially formed in the second layer. The semiconductor integrated circuit described.