JP2675338B2 - Semiconductor integrated circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having an FM front end block and an FM-IF block, and to meet the demand for custom ICs. As can be answered, the present invention relates to a semiconductor integrated circuit having a pattern layout that allows easy model development.

(B) Conventional Technology In general, a semiconductor integrated circuit technology for forming a plurality of circuit blocks on the same semiconductor substrate as shown in Japanese Patent Laid-Open No. 59-84542 (H01L 21/76) has a configuration shown in FIG. Has become.

FIG. 8 is a schematic plan view of the semiconductor chip (101), and a to f show circuit blocks. These circuit blocks have different frequencies and signal levels to be handled, and also have different functions.

This circuit block is formed in an N type region (103) on a P ⁻ type semiconductor substrate (102) as shown in FIG. 9, and each circuit block is surrounded by a high concentration P ⁺ type region. (Ten
It is divided by 4). Here, it is shown by block b and block c.

The P ⁺ type region (104) for this partition has one end in contact with the P ⁻ type semiconductor substrate (102) and the other end ohmic-connected to the ground line (106) through the oxide film (105) on the semiconductor surface. To be done.

The ground line (106) is gathered from each block at the center of the integrated circuit and extends to the ground bonding pad GND at the left end.

Next, the power supply line (V _CC ) of each block circuit is gathered on the outer peripheral portion of the integrated circuit and individually connected to the power supply bonding pad, as shown in FIG.

On the other hand, since the circuit blocks a to f have different functions,
The number of elements existing in each block is different, and the block sizes are different from each other.

(C) Problem to be Solved by the Invention In a semiconductor integrated circuit composed of a plurality of blocks described above, when the FM front end block and the FM-IF block included in the circuit for AM / FM stereo tuner are integrated,
The interference of these two blocks causes malfunction and
There was a problem that it was difficult to make chips. Further, since the circuit blocks a to f have different sizes, the size of each circuit block interacts with each other in order to efficiently accommodate all the circuit blocks in the semiconductor chip (101).
There is a problem that it is difficult to integrate them in the same chip.

Further, when the circuit block a is deleted and another circuit block a'having improved characteristics is inserted, or a circuit block g having another function is added to the circuit block configuration of FIG. It was necessary to recreate all the patterns because the size of was different.

Therefore, in recent years, when the life of the product has become extremely short, if the user wants to incorporate a unique circuit desired by a user into a certain chip, the user desires a short delivery time, but the circuit is short. It had a problem that it needed a very long delivery time to recreate the pattern.

(D) Means for Solving the Problems The present invention has been made in view of the above problems, and a suction electrode that absorbs a leak current of a semiconductor substrate is provided on the side of the FM-IF block corresponding to the FM front end block side. In addition, the upper surface of the semiconductor chip (1) is divided into a large number of mats of substantially the same size by the division line ( 5 ), and a plurality of electronic circuit blocks having different functions are divided into one or more integer numbers. By accommodating it in the mat, the conventional problems are solved.

(E) Operation According to the present invention, it is the FM front end block side
Since the side of the FM-IF block serves as a path for leakage current that enters the FM front end block, the drain electrodes (43) and (79) are provided on this side to centrally absorb the leakage current and Prevents interference with the end block. Further, by dividing the upper surface of the semiconductor chip (1) into a large number of mats having substantially the same size by the division line ( 5 ) and accommodating a plurality of electronic circuit blocks having different functions in an integer number of mats, the electronic circuit block is formed. Each mat can be designed, and the electronic circuit block can be divided into a certain number of elements to design each mat. Therefore, it is possible to divide each electronic circuit block for parallel design, and it is possible to significantly reduce the design period. Further, the circuit can be changed for each electronic circuit block and for each mat, so that it is not necessary to change the design of the entire IC.

(F) Embodiment First, the first embodiment of the present invention will be described in detail with reference to FIG. For convenience of explanation, the mat division structure, which is one of the features of the present invention, will be described here. Therefore, the mat division structure will be described first.

The first and second semiconductor chips (1) have substantially the same shape by using the divided regions (2) indicated by the chain double-dashed lines.
Area (3), (4), and each area (3),
(4) is divided into mats A to J and K to T. A
The mats J to K and T are divided by a partition line ( 5 ) in which a power line indicated by a solid line and a ground line indicated by a dot-dash line are adjacently extended in parallel.

Regarding the arrangement of the power supply line and the ground line forming the division line ( 5 ), the power supply line indicated by a solid line is provided on the left side of each of the mats A to J and K to T, and the ground line indicated by a dashed line is provided on the right side. Therefore, the division line at both ends ( 5 )
Only the power line or the ground line is formed, and the intermediate partition line is formed by both. Power supply lines and ground lines adjacent to the mats A to J and K to T are integrated in the respective mats to supply power to the circuit blocks.

The power supply line and the ground line of each partition line ( 5 ) are the third power supply line (6) and the second power supply line (7), the third ground line (8) and the second power supply line (7), which are indicated by the three-dot chain line.
Of the third and second power supply lines (6) and (7) and the third and second ground lines (8) and (9), which are connected to each other in a comb shape so as to face each other.
Are led to the power supply pads V _CC1 and V _CC2 and the ground pads GND1 and GND2 among the pads provided around the pellet.

As will become apparent later, due to the circuit, the mats K to M
Is different from these pads, V _CC3, V _CC4, GND3, using GND4, and each power supply line, ground line, and the second and third power supply line (7), (6), second And the third ground lines (9) and (8) are basically 2
It is realized by one layer wiring among the layer wirings.

Each mat A divided by the division line ( 5 ) described above
J and K to T are formed into shapes having substantially the same size,
Specifically, the width is set so that six NPN transistors can be arranged, and the length is set so that a fixed number of elements, for example, about 100 elements, can be laid out for easy design. The size of this mat can be arbitrarily selected according to the number of elements that can be easily designed by an electronic circuit block to be integrated into an IC.

The circuit elements integrated in the mat are composed of transistors, diodes, resistors and capacitors, separated by normal PN separation, and the wiring of each element is connected by the electrode layer of the first layer of the two-layer wiring. The electrodes of the second layer are crossed over.

Next, with reference to FIG. 2A and FIG. 2B, the circuit elements and the partition line ( 5 ) integrated in the mat will be specifically described.

FIG. 2A is an enlarged top view of the vicinity of the mat B. The partition line ( 6 ) shown by the dashed line on the left is the partition line ( 5 ) provided between the mat A and the mat B, and the partition line ( 7 ) shown by the dashed line on the right is the mat B and the mat. C
It is a division line ( 5 ) provided between. The transistor (10), the diode (11), the resistor (12) and the capacitor (13) shown by the dotted line are integrated between the division lines ( 6 ) and ( 7 ). Although these elements are rough in the drawing, they are actually densely integrated. The wiring between the elements in the mat is substantially formed of the first electrode layer (14) shown by the alternate long and short dash line, and the wiring between the mats A and B and between the mats B and C,
For example, the signal line and the feedback line are formed by the second electrode layer (15) shown by the solid line. The first and second electrode layers (14) and (15) are connected to each other at the contact regions indicated by the cross marks.

2B is a sectional view taken along the line AA ′ in FIG. 2A. An N type epitaxial layer (17) is laminated on a P type semiconductor substrate (16).
7) A P ⁺ -type isolation region (18) reaching the semiconductor substrate (16) from the surface is formed, and a large number of island regions are formed. The NPN transistor (10), the diode (11), the resistor (12), the capacitor (13), etc. are formed in the island region (19), and the collector region (20) of the NPN transistor (10) and the semiconductor are formed. An N ⁺ type buried region (21) is formed between the substrate (16) and the substrate. A silicon oxide film (22) is formed on the surface of the epitaxial layer (17) by, for example, a CVD method, and a first electrode layer (14) is formed on the silicon oxide film (22). . In addition, to cover the first electrode layer (14),
For example, an insulating film (23) such as PIX is formed, and this insulating film (2
3) The second electrode layer (15) is formed on the top. The power supply line (24) and the ground line (25) are provided on the separation region (18), and the ground line (25)
Is in ohmic contact with the isolation region (18) to stabilize the substrate potential.

More specifically, as shown in FIG. 1, ten mats A to J are formed in the first area (3), and ten mats K to T are formed in the second area (4). The mats are formed into substantially the same space in which about 100 elements can be integrated, and each mat is divided by a partition line ( 5 ).

In the above 20 mats, a one-chip IC for AM / FM stereo tuner shown in FIG. 3 is formed. FIG. 3 is a block diagram for explaining this electronic block circuit. The FM front end block ( 26 ), FM-IF block (27),
Noise canceller block (28), multiplex decoder block (29), AM tuner block (3
It is composed of a total of five electronic circuit blocks (0).
Although each circuit block is well known, its function will be briefly described.

First, the FM front end block (26) is a part for selecting the FM broadcast, and receives the FM broadcast signal of several tens of MHz to several hundreds of MHz,
The frequency is converted to an intermediate frequency signal of 10.7MHz,
Since it has about 250 elements, it is integrated in a mat of KM. Next, the FM-IF block (27) amplifies this intermediate frequency signal and then detects it to obtain an audio signal. Since it has about 430 elements,
~ I is integrated in the mat. The noise canceller block (28) is for removing pulse noise such as ignition noise. Since it has about 270 elements, it is integrated in the N to P mats. Further, the multiplex decoder block (29) is a block for stereo demodulating a stereo signal, and has about 390 elements and is therefore integrated in the mat of Q to T. Lastly, the AM tuner block (30) is the part for selecting the AM broadcast, converts the AM broadcast signal received by the antenna to an intermediate frequency (450KHz), and detects it to obtain an audio output.
Since it has 0 elements, the mats A to D are integrated.

Further, in FIGS. 4A, 4B and 4C, AM respectively.
The tuner block (30), the front end block (26), the FM-IF block (27), and the multiplex decoder block (29) are further divided into blocks.

First, the local oscillation circuit (OSC) (31) in the AM tuner block (30) of FIG. 4A is on the mat A and the mixing circuit (MIX).
(32) on mat B, automatic gain control circuit (AGC) (3
3), the high frequency amplification circuit (RF) (34) and the intermediate frequency amplification circuit (IF) (35) are on the mat C, and the detection circuit (DET) (3
6) is substantially integrated on the mat D, and the third power supply line (37), (38), which is shown by the three-dot chain line and extends from the power supply pad V _{CC1 as} shown in FIG. V _{CC to} the first power supply line (41) of the mats A to D via (39) and (40)
Has been supplied. Further, the ground pad GND1 has three octopus-shaped electrodes (42) provided between the mat M and the mat N.
Is connected to the second ground lines (43), (44), (45), (46) indicated by the three-dot chain line on the one-end divided region (2) through the respective second ground lines (43). , (44),
(45) and (46) are connected to the first ground line (47) of the mats A to D.

Next, the high frequency amplifier circuit (48) and the mixing circuit (4
The front end block (25) consisting of 9) and the local oscillator circuit (50) handles signals of a very small level of a few μV, so it dislikes interference from other circuit blocks, especially the FM-IF block (27). Also, the local oscillator circuit (50) in this block oscillates itself to generate unnecessary radiation. Therefore, in particular, separate it from the FM-IF block (27),
Since the OSC block (50) is most susceptible to interference, another power supply V _CC3 ,
We are using the V _CC4, GND3, GND4.

That is, K ~ which is diagonal to the FM-IF block (27)
The local oscillator circuit (50) is integrated on the mat K, which is the corner of the mat, and the other pads V are on both sides of the mat K.
_A first power supply line (51) and a ground line (52) are provided through CC4 and GND4. The other L and M mats are provided with respective first power supply lines and ground lines (53) and (54) through V _CC3 and GND ₃ .

On the other hand, an FM-IF block (27) composed of an intermediate frequency amplification circuit (55), a detection circuit (56), an S meter (57), etc.
Are integrated in the mats E to I, and the detection circuit (56) is in the mat I, the S meter (57) is in the mat G, and the limiter circuit and the mute circuit in the intermediate frequency amplifier circuit (55) are , E, F and G mats are virtually integrated.

Here, a limiter circuit having a very high gain of 80 to 100 dB and a detection circuit (56) having a large signal level, and the limiter circuit and an S meter (57) having a large signal level generate oscillation due to feedback, and the detection circuit (56) and S Since the characteristic of the meter (57) deteriorates due to mutual interference, the first power supply line (58) of the mats E, F, G is connected to the third power supply line (39) indicated by the one-dot chain line. H, I first power line (59)
Is connected to one third power supply line (38).
The mat J has an optional circuit from a user integrated therein, and the first power supply line (60) is also connected to one third power supply line (37).

The first ground line (61) indicated by the alternate long and short dash line on the mats E to J extends from the ground pad GND1 in a octopus-like shape and is connected at one end to the second ground line (4).
3), (44), (45) and (46) are connected in the same manner as described above.

Then, the DC amplifier circuit (62) and the decoder circuit (6) of the multiplex decoder block (29) of FIG. 4C.
3), the lamp driver circuit (64) is connected to the matte Q and the matte R, and the phase comparison circuit (65), the low pass filter circuit (66), the voltage controlled oscillator (67) and the frequency divider circuit (68) are connected to the matte S. Substantially integrated on the mat T. The electrode was Zaisa three extending from the power supply pad V _CC2 in octopus form (6
9), (70), (71) are AM tuner blocks (30)
And the FM-IF block (27), and the divided area (2)
One end is connected to the second power supply lines (72), (73), (74) above. And one is for mats Q and R, one is for mats S and T, and one is for noise canceller block (2
8) It extends to N to P mats.

On the other hand, the ground pad GND2 is connected to the three third ground lines (75), (76), (77) in a octopus-like shape, and in the same manner as described above, the N to P mats, the Q and R mats, Extends to S and T mats.

In addition, pads are used to prevent mutual interference between blocks.
Separately use V _CC1 , V _CC2 and pads GND1 and GND2
V _CC1 and V _CC2 are connected to leads, and pads GND1 and GND2 are connected to leads. This prevents the variation of the pad V _CC1 from being directly transmitted to the pad V _CC2 , and lowers the impedance of the metal thin wire by using two metal thin wires. Therefore, the pulse noise or the like that has entered the leads is not amplified through the impedance, and the voltage fluctuation can be prevented.

As described above, the partition line ( 5 ) composed of the first power supply line and the first ground line A to
The mats J, K to T are divided. Further, since the first power supply line and the first ground line are formed substantially in a comb shape, the space between the mats and the peripheral space can be effectively used, and the pads around the chip (1) can be effectively used.
V _CC1 , GND1, GND2 can be connected at the shortest distance.

Next, FM front end (26) and FM-IF block (27)
This section describes measures against interference. In the past, it was a problem on the set board because each individual IC was used, but this time this interference became a problem because it was one chip, but it is solved by the following measures.

First, as mentioned above, the FM front end block (26)
Since it handles a signal of a very small level of several μV, it dislikes interference from other circuit blocks, especially the FM-IF block (27), and the local oscillator circuit (50) built in this block itself oscillates. However, in order to generate unnecessary radiation,
It is necessary to separate from other blocks or provide another power source.

For these reasons, first, the FM front end block (26) and the FM-IF block (27) are provided on a diagonal line, and the local oscillator circuit (50) in this block is integrated on the mat K and separated. Next, with the AM tuner block (30)
FM-IF block (27), FM front end block (2
The FM front end block (2) is provided by widening the partition line width between the mat 6 and the noise canceller block (28), that is, the mat D and mat E and the mat M and mat N.
Keep 6) away from other blocks, especially the FM-IF block (27). Further, between the mat D and the mat E and between the mat M and the mat N, a second area (2) from the power supply pad V _CC2 is provided.
Electrodes (69), (70), (71) extending to the first electrode (42) extending from the ground pad GND1 to the first region (3).
And a second power line (72), (73), (74) and a second ground line (4) on the divided area (2).
3), (44), (45) and (46) are provided. Therefore FM
The front end block (26) is separated from the adjacent FM-IF block (27), AM tuner block (30) and noise canceller block (28), especially the power supply lines (69), (70), (71). Unnecessary radiation is prevented, and at least one of the ground lines (43), (44), (45), (46) is in contact with the isolation region (18), so the substrate current can be drawn out and interference can be prevented. doing.

Fig. 5 shows the FM front end block (2
FIG. 6 is a diagram specifically showing a state where the 6) and the FM-IF block (27) are separated. The first dashed-dotted line current is formed on the first layer
To the third power supply line and the first to third ground lines, and the electrodes shown by the solid lines are the crossover electrodes formed in the second layer.

The local oscillator circuit (50) in the FM front end block (26), since hate interference, provided separately the power pads V _CC4 and ground pad GND4, outside the circuit power supply pad
Supplied on V _CC3 and ground pad GND3.

Further, the FM-IF block (27) has a limiter circuit for removing the AM part of the FM signal, and this circuit is integrated with the mat E and the mat F. MO in this limiter circuit
Each S-type capacitor is formed in an island, and the PN junction formed by this island causes leakage to the substrate due to the capacitor, and this leakage current flows to the FM front end and causes malfunction. Therefore, a dummy island (78) shown by hatching in FIG. 6 is provided. This dummy island (78) is composed of an N-type epitaxial layer (17) surrounded by a P ⁺ -type isolation region (18) connected to the semiconductor substrate (16) supplied with the ground potential.
A barrier is formed by the junction. Therefore, the leak current can be prevented from entering the FM front end block. Further, the capacitors are put together on the mat E, and the side of the FM-IF block corresponding to the area side where the FM front end block is formed, specifically, the left side of the mat E hatched with a cross in FIG. Suction electrodes (43) and (79) are provided on the lower side and contacts of the separation region are provided to intensively suck out. Since the capacitor is actually integrated on the mat E, the suction electrode (43) extends only to the lower side of the mat E.

However, when the capacitors are dispersed in the mats E to J, they are formed like the electrodes (43) shown on the lower side of the mats E to J in FIG. 1, and the separation region ( 18) and contact may be made over substantially the entire surface. Further, the suction electrode (79) extends to the outer periphery of the region where the FM-IF block (27), the multiplex decoder block (29) and the noise canceller block (28) are formed, and leaks generated from them. It is also draining the current. Similarly, a ground line (80) is also provided around the left half of the chip (1). In addition, due to wiring, the third power line (37), (38), (39), (4
0), second power supply lines (72), (7) on the divided area (2)
3), (74) and the second ground line (43), (4
4), (45), (46), etc. are shown by dotted lines through through holes (corresponding to the X mark in FIG. 5) shown by black circles.
Crossover is performed through the electrode layer of the layer (corresponding to the solid line in FIG. 5). Especially AM tuner block (3
Since 0) does not operate simultaneously with the external block circuit, the AM tuner block (30) and the FM-IF block (27) share one pad V _CC1 and therefore cross over. The same applies to the ground pad GND1.

Next, the mat E will be described in more detail with reference to FIGS. 7A and 7B, which are enlarged views. The leakage current generated from the area where the capacitor of the mat E is formed is indicated by the dashed lines formed on both sides of the mat E (81), (82),
The ground line (81) and the suction electrode (83) arranged in the shape of a comb are sucking out. A partially enlarged view of the mat E is shown in FIG. 7A.

The thickest electrodes (81) and (82) shown by the one-dot chain line are the ground lines (7) formed on both sides of the mat E in FIG.
9) and (43). These two ground lines (8
A MOS type capacitor (84) is formed between 1) and (82), and the hatched portion corresponds to the capacitor upper layer electrode (85) and is formed on the first layer. Further, the upper layer electrode (85) makes ohmic contact with the second layer electrode (86) through the contact shown by a mark on the right side, and the electrode (86) is extended to the right side to make the electronic circuit of the present invention. It is connected to the circuit elements included in the block. The contacts (87) indicated by crosses above and below or on the left and right of the upper electrode (85) are the P-type diffusion region (88) and the capacitor formed in the lower layer of the upper electrode (85) shown in FIG. 7B. The contact portion with the electrode (89) corresponding to the lower layer electrode is shown. Here, the electrode (89) is hereinafter referred to as a lower layer electrode. This lower layer electrode (89) contacts the second layer electrode (91) through the contact (90) like the upper layer electrode (85), and the second layer electrode (91) moves to the right side. It is extended and connected to the circuit elements included in the electronic circuit block.

Finally, an example of the characteristic points of the present invention will be described. For example, if the AM tuner block (30) is not needed, four mats that will be the multiplex decoder block (29) are integrated in the mats A to D as they are, and the mats I and J, for example, are matted in the remaining mats Q and R. To be integrated. Therefore, I, J,
Since the mats for S and T are redundant, if this mat is deleted, the mats can be neatly stored in a rectangular chip. Here, the wiring of the first layer in the mat is used as it is, and only the wiring between the mats and the wiring between the blocks may be considered.

Further, when a part of the FM-IF block (27) is modified, for example, only the mat F, which is a modified part, may be taken out and modified, and the other mats E, G, H can be used as they are. When adding another block which is an option for the user, all the mats are used as they are, and the required number of mats may be added to this block. Here, the mat J is used as this option mat.

That is, since mats having the same size are formed in a matrix, replacement, addition, and deletion are very easy.

(G) Effects of the Invention As is apparent from the above description, first, the drain electrode for absorbing the leak current of the semiconductor substrate is first provided on the side of the FM-IF block, which is the side where the FM front end block is formed. By providing (79) and (43), it becomes possible to absorb the leak current generated from the region where the FM-IF block is formed. Therefore, the FM-IF block and the FM front end block can be integrated into one chip.

Second, connect the suction electrode (79) directly to the ground pad GND2.
Or connect the suction electrode (43) to the ground line (4
When connected to 2), the leak current sucked out by the suction electrodes (79), (43) can be made to flow to the outside via GND1 and GND2.

Thirdly, by contacting the drain electrodes (79) and (43) with the isolation region provided under the electrodes over substantially the entire surface, the isolation region or the drain that serves as a leak current drain port. The electrodes (79) and (43) surround the FM-IF block.

Therefore, the capacitors are not integrated on the mat E and can be effectively sucked out even if they are dispersed.

Fourthly, by providing the drain electrodes (79) and (80) around the semiconductor chip and providing the isolation region around the semiconductor chip (1), the leak current flowing out to the periphery can be drained.

Fifthly, a capacitor included in the FM-IF block is integrated in a specific region where the FM-IF block is formed, and a suction electrode is provided in this specific region, which is a source of leak current. It can be sucked out intensively from the area where the capacitor is formed.

Sixth, when the upper surface of the semiconductor chip (1) is divided into a large number of mats having substantially the same size by the division line ( 5 ) and a plurality of electronic circuit blocks having different functions are accommodated in an integer number of mats, the electronic circuit block is formed. Each design can be done in parallel and the design period can be greatly shortened. Further, since the electronic circuit block is divided into a certain number of elements and the design for each mat can be performed, the parallel design for each mat can also be performed. Further, since circuit changes such as deletion, addition and correction can be designed for each electronic circuit block or each block, only the change for each block or each mat is sufficient, and the design change of the entire IC is unnecessary. Furthermore, since the mat can be made into a cell as a basic block, once the design is completed, other mats can be used as they are, and the reliability can be improved very much by modifying only the mat to be changed when the circuit is changed thereafter.

Moreover, in the mat-divided semiconductor integrated circuit which facilitates this design, the side of the FM-IF block corresponding to the region where the FM front end block is formed, here the left side of the mat E and the mats E to J By providing the drain electrode on the lower side, the leak current flowing to the mats K to M in which the FM front end block is formed is drained. Therefore, in the IC in this mat division, FM-IF
Block and FM front end block can be integrated into one chip.

[Brief description of the drawings]

FIG. 1 is a top view showing an embodiment of a semiconductor integrated circuit of the present invention, FIG. 2A is a top view showing a mat area of the semiconductor integrated circuit of the present invention, and FIG. 2B is A-A in FIG. 2A. A sectional view taken along the line ', FIG. 3 is a block diagram of an electronic circuit incorporated in the semiconductor integrated circuit of the present invention, FIG. 4A is a diagram for explaining an AM tuner block, and FIG. 4B is an FM front end block and FM-IF. FIG. 4C is a diagram illustrating a block, FIG. 4C is a diagram illustrating a multiplex decoder block, and FIG.
FIG. 6 is an electrode pattern diagram of FIG. 6, FIG. 6 is a dummy island pattern diagram of FIG. 1, FIG. 7A is a top view when capacitors are integrated on the mat E, and FIG. 7B is AA ′ in FIG. 7A.
FIG. 8 is a cross-sectional view of the line, and FIG. 8 is a top view of a conventional semiconductor integrated circuit.
FIG. 9 is a sectional view between block b and block c in FIG. (1) …… Semiconductor chip, (2) …… Divided area, (3)
...... First area, (4) ...... Second area, ( 5 ) ...... Partition line, (37), (38), (39), (40) ...... Third power supply line, (43 ), (44), (45), (46) …… Second
Ground line, (72), (73), (74) ... second power line, (75), (76), (77) ... third ground line.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP 62-12147 (JP, A) JP 62-293660 (JP, A) JP 61-292341 (JP, A) Actual development 57- 138351 (JP, U)

Claims (3)

(57) [Claims] 1. A semiconductor network of a semiconductor chip is divided into a plurality of arrangement regions having substantially the same size and shape, and a circuit network including a plurality of circuit blocks including at least NPN transistors and having different numbers of elements and functions, Each of the circuit blocks is housed in one or more of the layout areas, and wiring for power supply is extended along the side of the layout area to prevent leakage current from the stored elements in the layout area. Provided on the side edge is a contact hole through which the high concentration isolation area is exposed together with the high concentration isolation area, and a ground (GND) line that is a part of the power supply wiring formed on the side edge of the arrangement area, Alternatively, a ground (GND) line drawn independently from an external connection pad is connected to the high-concentration isolation region through the contact hole to serve as the leak current drain electrode. Semiconductor integrated circuit as a characteristic. 2. A dummy region is formed in the center of the semiconductor layer of the semiconductor chip, the divided region dividing the semiconductor chip into a first region and a second region, and the divided region is surrounded by a high concentration isolation region. The first region and the second region are divided into a plurality of arrangement regions having substantially the same size and shape, and the plurality of circuit blocks including at least NPN transistors and having different numbers of elements and different functions are provided. Each of the circuit blocks is housed in one or a plurality of the layout areas, and wiring for power supply is extended along a side edge of the layout area. A contact hole that exposes the high concentration isolation region is provided on the high concentration isolation region surrounding the island, and a ground (GND) line that is a part of the power supply wiring is extended or The semiconductor integrated circuit, characterized in that ground (GND) line routed separately from the connection pads, and a suction electrode of leakage current through the contact hole connected to the high-concentration isolation regions. 3. The semiconductor integrated circuit according to claim 2, wherein an FM front end block is formed in one of the first area and the second area, and an FM-IF block is formed in the other area.