JPH0628288B2 - Linear semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a semiconductor integrated circuit, and more particularly to a pattern layout that can be easily developed in a model so as to meet the demand of a custom IC.

(B) Conventional Technology In recent years, semiconductor integrated circuits have become more multifunctional, highly integrated, and diversified, and the FM / AM tuner circuit shown in FIG. 5 is also being integrated into one chip.

In the figure, (1) is a circuit for selecting an FM broadcast and mixing the received frequency signal with the oscillation frequency signal of the local oscillation circuit (2).
An FM front end circuit that converts the frequency to an intermediate frequency by mixing in (3), and (4) is an intermediate frequency signal (IF
FM / IF amplifier circuit which obtains an audio signal (AF signal) by amplifying / amplifying signal) and detecting it, and (5) is a noise canceling circuit having a function as described in Japanese Patent Publication No. 62-21461. , (6) is a multiplex circuit for demodulating into L channel and R channel signals in the case of stereo broadcasting, and (7) is an AM tuner circuit for selecting AM broadcasting and outputting an audio signal. (8) is an antenna, (9) is an RF amplifier circuit, and (10) is an output terminal.

Generally, JP-A-59-84542 (H01L 21 /
As shown in 76), the semiconductor integrated circuit technology for forming a plurality of circuit blocks on the same semiconductor substrate like the FM / AM tuner circuit has the configuration shown in FIG.

FIG. 6 is a schematic plan view of the semiconductor chip (101).
Reference characters f to f denote circuit blocks. These circuit blocks have different frequencies and signal levels to be handled, and also have different functions.

This circuit block is a P ^- type semiconductor substrate as shown in FIG.
The circuit block is formed in the N-type region (103) on the (102), and each circuit block is partitioned by the high-concentration P ⁺ -type region (104) adjacent to the periphery thereof. Here, the blocks b and c are shown.

One end of the P ⁺ type region (104) for partitioning is in contact with the P ⁻ semiconductor substrate (102) and the other end is ohmic-connected to the ground line (106) through the oxide film (105) on the semiconductor surface. It

The ground line (106) extends from each block in the central portion of the integrated circuit to the ground bonding pad GND at the left end.

Next, the power supply line (V _cc ) of each block circuit is gathered on the outer peripheral portion of the integrated circuit and individually connected to the power supply bonding pad, as shown in FIG.

On the other hand, since the circuit blocks a to f have different functions, the number of elements existing in the block is different and the block sizes are different.

(C) Problems to be Solved by the Invention As described above, since the circuit blocks a to f have different sizes, all of these circuit blocks can be efficiently used in the semiconductor chip (1
In order to fit in 01), there is a problem that the size of each circuit block interacts with each other, making integration on the same chip difficult. Therefore, the FM / AM tuner circuit shown in FIG. 5 has a drawback that the design period becomes extremely long.

If the circuit block a is deleted and another circuit block a'having improved characteristics is inserted, or a circuit block g having another function is added to the circuit block configuration of FIG. It was necessary to recreate all the patterns because the size of was different.

Therefore, in recent years, when the life of the product has become extremely short, if the user wants to incorporate a unique circuit desired by a user into a certain chip, the user desires a short delivery time, but the circuit is short. It had the drawback of requiring a very long delivery time to recreate the pattern.

(D) Means for Solving the Problems The present invention has been made in view of the above problems, and divides the upper surface of the semiconductor chip (11) into a large number of mats of substantially the same size by the dividing line ( 17 ), By storing electronic circuit blocks with different functions in one or more integer mats,
It is intended to provide a semiconductor integrated circuit which solves the conventional problem and which can easily design a pattern by surrounding a local oscillation circuit (24) of an AM tuner circuit (7) with a dummy island (33).

(E) Operation According to the present invention, the upper surface of the semiconductor chip (11) is divided into a large number of mats having substantially the same size by the division line ( 17 ), and an electronic circuit block having a plurality of different functions is divided into an integer number. By accommodating in the mat, it is possible to design for each electronic circuit block and divide the electronic circuit block by a fixed number of elements to design for each mat. Therefore, it is possible to divide each electronic circuit block for parallel design, and it is possible to significantly reduce the design period. Further, the circuit can be changed for each electronic circuit block and for each mat, so that it is not necessary to change the design of the entire IC.

The local oscillator circuit (24) of the AM tuner circuit (7) is surrounded by a dummy island (33) to prevent interference, so that the local oscillator circuit (33) can be laid out at any position on the mat (18). , The mat (18) does not impair the ease of design.

(F) Example Hereinafter, the present invention will be described in detail with reference to the drawings.

A mat which facilitates pattern design will be described with reference to FIG. 2 on the left. In the figure, the semiconductor chip (1
A divided region (12) is formed in the center of (1) so as to cross it in a substantially straight line, and the element forming region of the semiconductor chip (11) is divided into two regions of substantially the same size vertically. The divided region (12) is a necessary unavoidable region for extending the ground line (13) and the power supply line (14) as described later, and is a region in which no circuit element is formed, and the divided region (12) is formed. By doing so, the divided two areas are respectively divided into a first area and a second area ( 1
5 ) ( 16 ) The ground line in a direction perpendicular to the divided area (12) (13) and the power supply line (14) and were adjacent compartments lines extend (17) provided as a pair, the compartment lines (17) A semiconductor chip (11)
The surface of the mat is divided into a number of mats (18) of substantially the same size. The size of the mat (18) is set to an occupied area in which an arbitrary number of elements can be laid out, and the width thereof is empirically set so that 5 to 6 NPN transistors can be arranged in one row.

On both sides of the mat (18), the ground line (13) and the power supply line (14) forming the division line ( 17 ) are extended in pairs, so that they are regularly arranged, for example, facing each other in a comb shape. Circuit formed on the mat (18) by extending so that the ground line (13) contacts one side of the mat (18) and the power supply line (14) contacts the other side of the mat (18). Supply operating power to the device.

The ground line (13) and the power supply line (14) extending the division line ( 17 ) are grouped according to each circuit block and whether or not they have a common impedance,
The divided regions (12) are extended to be individually connected to the corresponding ground electrode pad (19) and power electrode pad (20). As a result, a plurality of ground lines (13) and power supply lines (14) extend over the divided area (12), and each one is formed relatively wide to reduce the wiring impedance. (12) naturally requires a relatively large occupied area.

Ground line (13) and power supply line (14) that extend the partition line ( 17 ), ground line (13) and power supply line (14) that extend over the divided area (12), and in each mat (18) The connection wiring between the circuit elements in is basically performed by the first wiring layer by using a comb-shaped layout. From the second layer onwards, the mats are cut across the division line ( 17 ) and the divided area (12).
Mainly used to form signal transmission wiring between (18) and the shield electrode (21).

Incidentally, the divided area (12) sometimes extends in parallel with each division line ( 17 ). This is the power electrode pad (20) and ground electrode pad (19) for the package pin and array requirements.
It is provided between the mats (18) when there is a positional restriction or when there is a relationship in which the mats (18) or the circuit functional blocks are desired to be separated from each other. In FIG. 2, the area between the mats D and E is the former reason, and the area between the mats M and N is the latter reason. Then, the power supply line (14) and the ground line (13) are respectively drawn from the power supply electrode pad (20) and the ground electrode pad (19) provided near the ends of the divided regions (12a) extending in parallel, Then, the semiconductor chip (11) is routed over the divided region (12) which crosses the center of the semiconductor chip (11) and connected to the circuit elements in each mat (18).

When the function-specific circuit block is stored in the semiconductor chip (11) in which the element formation region is divided into a number of mats (18) in this way,
Each circuit block is stored as follows.

First, since the mat 18 is designed to have a size capable of accommodating an arbitrary fixed number of elements, the circuit block is divided into the fixed number of elements. For example, the size of the mat (18) is 10
If 0 elements are to be stored and the circuit block has about 270 elements, three mats (18) are prepared and 100 elements each are divided. Of course, take into consideration capacitors that occupy a large area. Then, according to the above classification, each mat (1
8) Each circuit element is stored, and the NPN stored in the mat (18)
The connection wiring between circuit elements such as PNP transistors, diodes, resistors, capacitors, etc. is completed in the first wiring layer. After repeating the pattern design of all the mats (18) by repeating this, the three mats (18) are arranged adjacent to each other, and the electrical connection between the mats (18) is made by the wiring of the second and subsequent layers. By making the connections, functional circuit blocks are constructed. Then, after storing all the circuit blocks in the mat (18), all the mats (18) are combined, and electrical connection between the circuit blocks is made by the wiring layers of the second and subsequent layers to complete the whole IC. design.

According to such a configuration, by storing a plurality of circuit blocks having different functions in an integer number of mats (18), it is possible to design each circuit block and divide the circuit blocks into certain elements to create a mat. (18) Each design can be done. Therefore, parallel design for each circuit block or mat (18) is possible, and the design period can be greatly shortened. Also, the circuit can be changed for each circuit block and for each mat (18),
It is not necessary to change the design of the entire IC, and it is possible to use it while maintaining the reliability of the previous model except for the changed portion.

Next, the AM tuner circuit (7) will be described. In FIG. 3, (22) is an RF amplifier circuit for high-frequency amplification of the RF signal tuned by the antenna, (23) is the RF signal and the local oscillation circuit (24).
Mixing circuit for frequency conversion to IF intermediate frequency (450KHz) by mixing with the frequency signal that oscillates, (25)
Is an IF amplifier circuit that amplifies the IF signal, (26) is an automatic gain control circuit that adjusts the gain according to the strength of the radio wave, and (27) is a detection circuit that detects the IF signal and demodulates it into an audio signal. . In addition to these main circuits, station detectors (S
D) circuit, S meter circuit, and associated circuits such as whistle noise prevention circuit (Tweet REG) for preventing noise are incorporated. The RF amplifier circuit (22) can be omitted.

Since the AM tuner circuit (7) has about 350 circuit elements in total, four mats (18), that is, mats A to D, are prepared, and all circuit elements are matted (mats) in accordance with the above procedure. Store in 18). An FM / IF amplifier circuit (4) is provided on the mats E to I and an FM front end circuit (1) is provided on the mats K to M.
However, the noise cancel circuit (5) is stored in the mats N to P, the multiplex circuit (6) is stored in the mats Q to T, and the other (optional) circuit is stored in the mat I.

FIG. 1 shows a pattern in which the AM tuner circuit (7) is housed in the mats A to D. In the figure, I is attached to the mat A
The F amplifier circuit (25) and the mixing circuit (23), the local oscillation circuit (24) and the whistle sound prevention circuit (28) on the mat B, and the RF signal on the mat C.
AGC circuit (29), S meter circuit (30) and SD circuit (31)
However, in the mat D, the RF / AGC circuit (29), the IF / AGC circuit (32) and the detection circuit (27) are housed, respectively, and the power line (14) and the ground line (13) on the partition line ( 17 ) are stored. ) Is
In view of the mutual relation of each circuit, the circuit is divided / integrated depending on whether common impedance is allowed or not, and individually extended to be connected to the power electrode pad (20) and the ground electrode pad (19). In particular, the local oscillation circuit (24) and the mixing circuit (23) are provided with their own dedicated ground lines (13a) and ground electrode pads (1
Connect to 9).

And handle the highest frequency signal and configure the input stage,
A dummy circuit (23) is provided for each of the mixing circuit (23) which is likely to be saturated depending on the level of the input signal (RF signal) and the local oscillation circuit (24) which is required to accurately perform an unstable operation called an oscillation operation. By completely enclosing them with, the circuit interference due to the inflow and outflow of leak current is prevented.

Fig. 4 shows the cross-sectional structure of the mixing circuit (23), where (41) is P
Type semiconductor substrate, (42) N type epitaxial layer, (43) N type
⁺ Type buried layer, (44) is from the surface of the epitaxial layer (42) to the substrate
P ⁺ type separation region reaching (41), (45) separation region (44)
Islands for element formation formed by the epitaxial layer (42) surrounded by (33) is a dummy island not forming a circuit element, (46) and (47) are P and N type impurity diffusion regions, and (47) is An oxide film covering the epitaxial layer (42), (48) inter-element connection wiring by the first wiring layer, (13) and (14) similarly ground lines and power lines by the first wiring layer, (4)
9) is the interlayer insulating film, and (50) is the second crossing the partition line ( 17 ).
It is the connection wiring by the second wiring layer. Dummy Island (3
3) is formed by using the occupied area of the partition line ( 17 ) and is set to a floating state where no potential is applied, or a power supply line ( 17 ) which forms the partition line ( 17 ) through the N ⁺ type diffusion region (47a). The power supply potential _Vcc is given by 14). Further, the ground line (13b) forming the section line ( 17 ) is brought into ohmic contact with the surface of the underlying isolation region (44) to form a drain electrode for draining a leak current.

According to such a configuration, since the resistance component due to the N-type high-low high-layer of the dummy island (33) is present, the dummy island (3
3) Coupling of the regions on both sides can be roughened. Further, the potential barrier due to the PN junction between the dummy island (33) and the isolation region (44) increases the resistance component. Therefore, the dummy island (33) serves as an element for passing leakage current, and suppresses mutual interference between the mixing circuit (23) and other circuits due to the leakage current. Also,
It is also effective to provide a suction electrode on the side of the dummy island (33). Therefore, the mixing circuit (23) and the pole oscillation circuit (24)
Can basically be placed at any position on the mat (18).

Since the mixing circuit (23) constitutes the input stage, the semiconductor chip (1
The wiring from the input electrode pad can be shortened and the interference can be prevented if it is located on the outer periphery of 1).

By the way, since the detection circuit (27) handles a signal of a large amplitude level after being amplified with a high gain, it leaks a leak current to cause mutual interference with the mixing circuit (23) and the local oscillation circuit (24) and oscillate. It is easy to cause malfunctions such as Therefore, by arranging the mixing circuit (23) or the local oscillation circuit (24) and the detection circuit (27) at the corners on the diagonal line of the AM tuner (7) storage area, respectively, the two are maximally separated from each other. Interference can be minimized.
Further, since the detection circuit (27) is the output stage, the AM
If the tuner circuit (7) is placed in the corner of the storage area, each circuit can be placed according to the flow of the signal line, so the mat (18)
There is also an advantage that connection wiring between them becomes easy.

In addition, the division line ( 1
If the ground line (13a) forming the element ( 7 ) is used as a suction electrode, the leak current from the detection circuit (27) can be immediately sucked, which further prevents interference.

(G) Effect of the Invention As described above, according to the present invention, since each circuit block is housed in the mat (18) based on the integer number of areas of the mat (18), pattern design can be performed for each mat (18). By combining the mats (18) whose design has been completed, there is an advantage that the layout of the entire IC can be arbitrarily realized. Also, the mat (1
8) There is also an advantage that parallel design can be performed for each. Therefore, the design period of the entire IC can be shortened, and when designing models with different circuit functions, only the changed mat (18) needs to be designed, and the remaining mat (18) has the reliability of the previous model. Since it can be reused while maintaining the above, there is an advantage that the design period required for model development can be greatly shortened.

Since the signal interference can be prevented by surrounding the mixing circuit (23) of the AM tuner circuit (7) and the local oscillation circuit (24) with a dummy island (33), basically, it can be placed at any position of the mat (18). AM tuner circuit (7)
This has the advantage that the degree of freedom in design is not impaired at the time of integrating the components with the mat (18).

In addition, the two circuits are separated from each other on the diagonal corners, and the leak current is sucked by the suction electrode, so that the circuit operation can be further stabilized. Further, since the dummy island (33) uses the occupied area of the division line ( 17 ), it has an advantage that the occupied area can be efficiently used.

[Brief description of drawings]

FIG. 1 is a plan view showing a pattern of an AM tuner circuit according to the present invention, FIG. 2 is a plan view for explaining the present invention, and FIG.
FIG. 4 is a circuit diagram showing an AM tuner circuit, FIG. 4 is a sectional view for explaining the present invention, FIG. 5 is a circuit diagram for explaining an FM / AM tuner circuit, and FIGS. 6 and 7 are respectively It is a top view and a circuit diagram for explaining a conventional example. (13) is a ground line, (14) is a power line, ( 17 ) is a partition line, (18) is a matte, (23) is a mixed circuit, (24) is a pole oscillator circuit, (27) is a detection circuit, (33) is a dummy island.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location H04B 1/08 E 7240-5K 7210-4M H01L 27/06 101 B

Claims (2)

[Claims] 1. Positioned on a semiconductor layer of a semiconductor chip,
A semiconductor element arrangement region (mat) formed in the semiconductor layer, which has a plurality of shapes of substantially the same size, and a plurality of electronic circuit blocks whose functions are substantially different in circuit size. In the linear semiconductor integrated circuit, the semiconductor element of the linear electronic circuit is formed in the arrangement area (mat), and the electronic circuit block divided by the function is a local oscillation output by a reception frequency signal and a local oscillation circuit. An AM tuner circuit block for outputting an audio signal by converting the frequency signal into an intermediate frequency by mixing the frequency signal with a mixing circuit, and demodulating the intermediate frequency into a detection circuit; and all semiconductors of the electronic circuit block. A plurality of elements are obtained by dividing the total number of semiconductor elements in this electronic circuit block using the arrangement area (mat) as a unit. At least one of the local oscillation circuit and the mixing circuit of the AM tuner circuit block, which is substantially formed in the placement area (mat), is surrounded by a separation area connected to the semiconductor substrate which is one configuration of the semiconductor chip. A linear semiconductor integrated circuit characterized by being completely surrounded by islands. 2. The local oscillating circuit or the mixing circuit is provided in a corner portion of a plurality of arrangement areas (mats) for accommodating semiconductor elements of the AM tuner circuit block, and the local oscillation circuit or the mixing circuit is provided in a corner portion of the entire area. The linear semiconductor integrated circuit according to claim 1, wherein the detection circuit is provided at a corner portion in a diagonal direction.