JPH0316163A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To eliminate a bad influence on other electronic circuit blocks by a method wherein capacitors in circuit blocks are integrated substantially in one region and a leakage current generated by the capacitors is sucked out in a concentrated manner. CONSTITUTION:The surface of a semiconductor chip 1 is divided into, e.g. 10 mats A to J; the individual mats A to J are partitioned by partition lines 4 where power-supply lines 2 and ground lines 3 are extended in parallel so as to be adjacent. Circuit elements which are integrated in the mats A to J contain transistors, diodes, resistances and capacitors 7; the capacitors 7 contained in an electronic circuit block of, e.g. the mat E are integrated in the mat E. When the capacitors 7 are integrated in one region in this manner, a leakage current can be sucked out in a concentrated manner at a circumference of this region. Thereby, it is possible to eliminate the leakage current which influences other electronic circuit blocks.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to semiconductor integrated circuits, and particularly to a capacitor leakage current absorption structure. (B) Conventional technology in general is disclosed in Japanese Patent Application Laid-Open No. 59-84542 (HOI L
21/76), a semiconductor integrated circuit technology in which a plurality of circuit blocks are formed on the same semiconductor substrate has the configuration shown in FIG. FIG. 8 is a schematic plan view of the semiconductor chip (101), and a to f indicate circuit blocks. These circuit blocks handle different frequencies and signal levels, and
The functions are also different.

This circuit block is formed in an N-type region <103) on a P-type semiconductor substrate (102) as shown in FIG. (104). Here, block b and block C are shown.

One end of the P4'' type region (104) for this division is in contact with the P1 type semiconductor substrate (102), and the other end is connected to the ground line (106) through the oxide film (105) on the semiconductor surface. Mink connected.

A ground line (106) is gathered from each block to the center of the integrated circuit and extends to the ground bonding pad GND at the left end.

Next, as shown in FIG. 8, the power supply lines (VCE) of each block circuit are grouped around the outer periphery of the integrated circuit and individually connected to power supply bonding pads. On the other hand, since the circuit blocks a to r have different functions, the number of elements present in each block is different, and the block sizes are different. (8) Problem to be Solved by the Invention The MOS type capacitor of the circuit block is generally P
Since it is formed within an N type island region surrounded by a type isolation region and an N+ type buried region, a PN junction capacitance is generated. This PN junction capacitance is determined by the junction between the N-type island region and the P0-type divided region, the N-type island region, or the N"-type buried region and the P0-type divided region.
This occurs when the mold is bonded to the semiconductor substrate. On the other hand, since this MOS type capacitor has a very large area, the PN junction area naturally increases, and the capacitance value becomes very large.

Therefore, there has been a problem in that leakage current from this capacitor flows into the semiconductor substrate, adversely affecting other electronic circuit blocks.

(2) Means for Solving the Problems The present invention has been made in view of the above problems, and solves the problems by integrating the capacitors (7) included in the circuit block in one area.

(*) Effect According to the present invention, since the capacitors are integrated in one area, leakage current can be sucked out in a concentrated manner around this one area. Therefore, leakage current that affects other electronic circuit blocks can be eliminated.

(f) Embodiment First, a first embodiment of the present invention will be described in detail with reference to FIG. The upper surface of the semiconductor chip (1) is divided into 10 mats A to J. There is a power line (2
> and the ground line (3) are separated by a division line (4) extending in parallel and adjacent to each other.

The arrangement of the power supply line (2) and ground line (3) forming the division line (4) is such that the t-source line (2) shown by a solid line is provided on the left side of each mat A-J, and the ground line shown by a dashed-dotted line is provided on the right side. (3) is provided.

Therefore, only the division lines of mat A and mat J at both ends are formed by either the power supply line (2> or the ground line {3}, and the intermediate division line is composed of both. Adjacent power supply lines (2) and ground lines (3>) are integrated in each mat and supply power to the circuit blocks.

In addition, the power line (2) and ground line (3) of each division line (4) are connected to the first line formed above and below the mat.
The first and second supply lines (5), . (6) is the power supply pad v0 in the pad provided around the pellet. and is led to the ground pad GND.

As will become clear later, each power line <2), the ground line (3), and the first and second supply lines (5)
, (6) is basically realized with 1 lm wiring of two-layer wiring.

Each mat A-J divided by the above-mentioned division line (4)
are formed into a shape of substantially the same size, specifically, the width is set so that six NPN transistors can be arranged in a row, and the length is set to a certain number of elements that is easy to design, for example, about 1.
The settings are such that 00 elements can be laid out. The size of this mat can be arbitrarily selected depending on the number of elements that can be easily designed depending on the electronic circuit block to be integrated.

The circuit elements integrated within the mat are composed of transistors, diodes, resistors, and capacitors, and are separated by normal PN isolation, and each element is connected by the first electrode layer of the two-layer wiring. Exceptionally, there is crossover at the second layer of electrodes. Also, as will become clear later, the main capacitors (7) included in the electronic circuit blocks of Mat E to Mat J are represented by the rectangles with broken lines on Mat E.
It is concentrated in Next, with reference to FIGS. 3A and 3B, the circuit elements integrated within the mat and the partition lines (4>) will be specifically explained.

FIG. 3A is an enlarged top view of the vicinity of mat B.

The division line (8) shown by the dashed line on the left is the division line (2) provided between mat A and mat B in FIG. The division line (4) provided between mat B and mat C in Figure 1
> is. And this division line (8). Between (9), a transistor (10), a die (11), a resistor (12), and a capacitor (13) are integrated, which are indicated by dotted lines.In the drawing, these elements are shown roughly. However, in reality, they are integrated at a high density.Also, the wiring between elements within the mat is connected to the first electrode layer <1
4), and wiring between mats A and B and between mats B and C, such as signal lines and feedback lines, is formed by the second electrode layer (15) shown by solid lines. ing. These first and second electrode layers (14) and (15) are connected through contact regions indicated by x marks. FIG. 3B is a sectional view taken along line AA' in FIG. 3A. An N-type epitaxial layer (17) is laminated on a P-type semiconductor substrate (16).
17) P0 reaching the semiconductor substrate (16) from the surface
A mold isolation region (18) is formed and a number of island regions are formed. Inside this island region (19), there is an NPN transistor (1o), a die (11),
A resistor <12>, a capacitor <13>, etc. are made, and the collector region <20> of the NPN} transistor (1o) is made.
) and the semiconductor substrate (16) or between the island and the substrate (19) is an N1 type buried region (21).
) is formed. A silicon oxide film (22) is formed on the surface of the epitaxial layer (17) by, for example, the CVD method.
is formed on this silicon oxide film (22).
The third electrode layer <14> is formed. Also this first
Layered electrode J'! (14), for example, PIX
An insulating film (23) such as The ground line (3) is provided on the isolation region (18) and is in direct mink contact with the isolation region (18) to stabilize the substrate potential.

Next, the relationship between the electronic circuit block incorporated in this configuration and the mat will be described. Here, two electronic circuit blocks shown in FIG. 6 are used, for example, a multiplex decoder block (24) that demodulates a stereo signal, and an FM-IF block that amplifies an intermediate frequency signal and then detects it to obtain a digital signal. Block (25) is installed.

The number of elements in this multiplex decoder block (24) is approximately 390, and the number of elements in the FM-IF block (24) is approximately 390.
5) is approximately 430 pieces. Therefore, the former is divided into four parts with 100 elements or less as a guide, and each part is integrated into mats A to D, and the function between each mat is determined by the second electrode layer (l5) as described above. The latter is also divided into five parts with 100 elements or less as a guide, and each part is integrated into mats E to ■, and the functions between each mat are as follows. As mentioned above, the second electrode layer (15) is provided to realize an electronic circuit block.Mat J is also intended to integrate circuits submitted by users, and for example, to further improve the performance of this IC. The circuit to improve the performance is integrated.

1-i, FM-The capacitor (7) incorporated in the IF block (25) is integrated in the mat E.

In Figure 1, there are 11 capacitors shown by broken lines. The leakage current generated from the area of mat E where the capacitor is formed is represented by ground lines (26) and (27) indicated by dashed lines on both sides of mat E.
The air is sucked out using the ground line <26> and the suction electrode (28) arranged in a comb-like shape. A partially enlarged view of this mat E is shown in FIG. 2A.

The thickest electrode (29), (30) indicated by the dashed-dotted line
are the ground lines (26), <27) formed on both sides of mat E in FIG. A MOS type capacitor (7) is formed between these two ground lines (29) and (30), and the hatched part corresponds to the upper layer electrode (31) of the capacitor, and the first layer This upper layer electrode (31) is in direct contact with the second layer electrode (33) via the contact (32) indicated by the cross on the right side, and this electrode (33)
) extends to the right and is connected to the circuit elements included in this electronic circuit block. Further, the upper layer electrode (31)
The contacts (34) indicated by cross marks on the upper and lower sides or left and right correspond to the P-type diffusion region <35> formed in the lower layer of this upper layer electrode (31) shown in Fig. 2B and the lower layer electrode of the capacitor. The contact portion with the electrode (36> is shown. Here, the electrode {36} is hereinafter referred to as the lower layer electrode. This lower layer electrode (36), like the upper layer electrode (31>), is connected via the contact (37). The second layer electrode <38> is in contact with the second layer electrode <38>, which extends to the right and is connected to a circuit element included in the present electronic circuit block.

Here, the contact (32) of the upper layer electrode (31) is provided near the left side of the ground line (30) to prevent the second layer electrode (33) extending from there in the direction of the mat F from crossing. It is provided in a straight line for this purpose.

Furthermore, since the signal flow in the circuit is from the top to the bottom of the mat F, the capacitors are also provided substantially in the order of the circuit from top to bottom.

Next, a cross-sectional view of this IC will be explained. Cross-sectional views taken along lines AA' and BB' in FIG. 2A are illustrated in FIGS. 2B and 2C.

First, there is a P-type semiconductor substrate (16), and an N-type epitaxial layer (17) is laminated on this semiconductor substrate (16). ) reaching the P-type separation region (18)
Each capacitor (7) is formed in an island surrounded by this isolation region (18). There is an N'' type buried layer (40) in the main region of this island (39), a P4 type diffusion region (41) is formed in the upper layer of this buried layer (40), and this diffusion region (41 ) is formed, and a P-type diffusion region <35> is formed which overlaps with the epitaxial layer (17>).
．． There is a film (22), and on this Sin film (22),
An upper layer electrode (31), a lower layer electrode (36), ground lines (29), (30), and a suction electrode (28) are formed. This grand line (29). (3
0) and the suction electrode (28) are in contact with each other over substantially the entire surface, as shown in the hatched contact area in FIG. 2A. And the second layer of insulation film,
For example, PIX (23) is coated and electrodes (33) and (38) extending to the mat F are shaped.

Therefore, a junction capacitor formed around or below this MOS type capacitor (7), such as an island (39
) and the isolation region (18), and the leakage current of the junction capacitor formed when the PN junction consisting of the island (39), the semiconductor base Fi (16) and the buried layer (40) is reverse biased, Via the Grand Line (29)
．． (30) or suction electrode (28).

Next, a second embodiment of the present invention will be described in detail with reference to FIG. In this embodiment, the semiconductor chip (42) has substantially the same shape using a divided region (43) whose upper surface is indicated by a two-dot chain line.
It is characterized in that it is equally divided into first and second regions (44) and (45), and a large number of mats are provided in each region (44) and (45). As a result, since the number of mats is large, the layout of the semiconductor chip (42) is easier than in the first embodiment.

Specifically, 10 mats A-J are formed in the first area (44), and 10 mats K-T are formed in the second area (45).
The structure of each mat is the same as in the first embodiment, with substantially the same space capable of integrating about 100 elements, and each mat is divided by {± partition line (4). .

However, the capacitor included in this electronic circuit block is integrated in the mat E in order to intensively absorb leakage current to the substrate.

The 20 mats listed above contain AM/FM as shown in Figure 6.
A 1-chip stereo tuner IC is formed. 6th
The figure is a block diagram explaining this electronic block circuit, including the FM front end block (46), FM-I
F block (25), noise canceler block (4)
7), multiplex decoder block (24),
It is composed of a total of five electronic circuit blocks: AM tuner block <48>. Although each circuit block is well known, its function will be briefly explained.

First, the FM front end block (46) is the FM broadcast channel selection part, which receives the FM broadcast signal of several tens of MHz to several hundred MHz and converts it into a 10.7 MHz intermediate frequency signal, and the number of elements is There are about 250 pieces of FM-I, so they are integrated on the K-M mat.Next, FM-I
The F block <25> amplifies this intermediate frequency signal and then detects it to obtain a single frequency signal, and has about 430 elements, so it is integrated on the E-1 mat. Next is Noise Canceller Block 47>
The device removes pulse noise such as ignition noise, and has approximately 270 elements, which are integrated into an NP mat. Further, the multiplex decoder block (24) is a block for stereo demodulating stereo signals, and since it has approximately 390 elements, it is integrated into a Q-T mat. Finally, the AM tuner block (48) is a channel selection part for AM broadcasting, and converts the AM broadcast signal received by the antenna to an intermediate frequency (450 KHz>) and detects it to obtain a high-speed output. Since it has about 350 elements, it is integrated in A-D mats.

Furthermore, in FIG. 7 A1, FIG. 7 B, and FIG. 7 C,
? A diagram in which the Euner block (48), the front end block (46), the FM-IF block (25), and the multiplex decoder block (24) are further divided into blocks is shown.

First, the local oscillation circuit (OSC) (49) in the AM tuner block (48) in FIG. 7A is connected to mat A, and the mixing circuit (MIX'') (50) is connected to mat B.
, an automatic gain control circuit (AGC) (51), a radio frequency amplification circuit (RF) (52), and an intermediate frequency amplification circuit (IF).
(53) is substantially integrated in the mat C, and the detection circuit (DET) (54) is substantially integrated in the mat D, and as shown in FIG. Third 't source line (55), (56), (5
7), (V. One end is connected to second ground lines (61), (62), and (63) shown by three-dot chain lines on the divided region (43) through three octopus-shaped electrodes (60), respectively. The second ground line (61), (62),
<63) is the first ground line (
64>.

Next, the high frequency amplification circuit (65) and the mixing circuit (65) in Fig. 7B are shown.
The front end block (46), which is composed of a local oscillation circuit 6) and a local oscillator circuit 67), handles signals at an extremely small level of several microvolts, so it
It dislikes interference from the F block (25), and the local oscillator circuit (67) in this block oscillates by itself.
Generates unnecessary radiation. Therefore, the FM-IF block (25〉) is particularly spaced apart, and since the OSC block hates interference the most, a separate power supply V.cl+Vq.., GND3,
GND4 is used.

That is, the local oscillation circuit (67) is integrated on the mat K-M diagonally with the FM-IF block (25), and the local oscillation circuit (67) is integrated on the mat K that is the most corner, and on both sides there are other pads VCC4 and A first t source line (68> and a ground line (69) are provided through GND4. Also, the other LM mats are connected to Vc (3 and GND).
3, respective first power supply lines and ground lines <70), (71) are provided.

On the other hand, the FM-IF block (25), which is composed of an intermediate frequency amplification circuit (72), a detection circuit (73), an S meter <74>, etc., is integrated on the E~! mat, and a detection circuit (73) is integrated into the mat I, the S meter (74〉, etc.) is integrated into the mat G, and furthermore, the limiter circuit, mute circuit, etc. in the intermediate frequency amplification circuit (72) are substantially integrated into the mats E, F, and G. .

Here, as explained in the first embodiment, the capacitor included in the limiter circuit is integrated in the mat E. This mat E is shown in Fig. 2 A1 Fig. 2 B and Fig.
Although it is substantially the same as Figure C, the ground lines (75) and (76) formed around the mat E are different. Ground line (75) Tsuji, semiconductor chip (4
2>, connects to GND2, contacts the isolation region below, and absorbs the nok current around the capacitor of mat E and the chip. In addition, the ground line (76) shares GND with a limiter circuit other than the capacitor included in the mat F, and allows leakage current from the mat E in the direction of the mat F to flow through the electrode (60) to GNDI. .

Further, the electrode (77) on the left periphery of the chip (42>) also sucks out leakage current.

Here, the limiter circuit with an extremely high gain of 80 to 100 dB, the detection circuit with a large signal level (73), the limiter circuit and the S meter 74) with a large signal level generate oscillation due to feedback, and the detection circuit (73) and the S meter (74
), the characteristics deteriorate due to mutual interference, so matte F,
The first power line (78) 41 of mats H and I is connected to the third power line (57) indicated by a single three-dot chain line.
The power supply line (79) is connected to one third power supply line (5
6). Further, the mat J is one in which an optional circuit provided by the user is integrated, and this power supply line (80) is also connected to a single third power supply line (55>).

Also, the first ground line shown by the dashed line on the E-J mat is the second ground line (61) which extends from the ground pad GNDI in a kite-like shape and is connected at one end.
, (62), and (63) are connected in the same way as above. Next, the DC amplifier circuit (81) and the decoder circuit (81) of the multiplex decoder block (24) shown in FIG.
2), the lamp driver circuit (83) is connected to mat Q and mat R, and the phase comparison circuit (84), low-pass filter circuit (85), voltage controlled oscillator (86), frequency dividing circuit (87), etc. are connected to mat S. The electrodes (88), (89), and (90) extend from the power supply pad VCC* in an octopus-like shape.
It passes between the AM tuner block (48) and the FM-IF block (25) and connects to the second section on the divided area (43).
One end is connected to the power supply lines (91), (92), and (93) of the above. One wire extends to the mats Q and R, one wire extends to the mats S and T, and one wire extends to the N-P mat that serves as the noise canceller block (47).

On the other hand, the ground bad GND24t has three third ground lines (94) shaped like an octopus. (95) , (9
6), and as before, the N-P mat, Q,
It extends to the R mat, S, and T mats. As explained above, similarly to the first embodiment, the A-J and K-T mats are divided by the dividing line (4>) composed of the first power supply line and the first ground line. In addition, since the first M. source line and the first ground line are substantially comb-shaped, the space between the mats and the surrounding space can be used effectively, and the area around the tip (42) can be effectively used. Pads Vccr, GNDI, and GND2 can be connected at the shortest distance.

Next, countermeasures against interference between the FM front end (46) and the FM-IF block (25) will be described. Previously, individual I
This was a problem with the set board because C was used for each, but this time, since it was made into one chip, this interference became an additional problem, but it was resolved by the following measures. First, as mentioned above, the FM front end block (46
) handles extremely small level signals of several μV, so
Other circuit blocks especially FM-IF block (25)
Since the local oscillation circuit (67) configured within this block oscillates itself and generates unnecessary radiation, it is necessary to separate it from other blocks or provide a separate power supply. .

For these reasons, first, the FM front end block and the FM-IF block were provided diagonally, and the local oscillation circuits in these blocks were integrated on the mat K and separated from each other. Next, the AM tuner block (48) and the FM-
Between the IF block (25), the FM front end block (46) and the noise canceller block (47), that is, mat D and mat E1 mat M and mat N
By widening the partition line width, the FM front end block (46) is kept away from other blocks, especially the FM-IF block (25).Also, between mat D and mat E, and between mat M and mat N, , power pad VC
C! an electrode (88) extending further to the second region (45);
, (89), (90) and ground pad GND
An electrode (60) extending from the I to the first region (44) is provided, and a second i source line <
91), (92). (93) and second ground lines (61), (62), and (63). Therefore, the FM front end block (46) is
Adjacent FM-IF block (25), AM tuner block (48) and noise xenseller block (
47〉, especially 1! Source line <88) , (
89) and (90) prevent unnecessary radiation, and since the ground line (60) is in contact with the isolation region, it can suck out the substrate current and prevent interference.

Also, since the local oscillation circuit (67) in this FM front end block (25) dislikes interference, the power supply bad v
cea and a ground pad GND4 are provided separately, and external circuits are supplied by a power supply pad VCCs and a ground pad GND3.

Further, the FM-IF block (25>) has a limiter circuit for removing the AM part of the FM signal, and this circuit is integrated with mat E and mat F.

The capacitor in this limiter circuit causes leakage to the substrate as described above, and this leakage current flows to the FM front end, causing malfunction. Therefore, the capacitors are grouped together in the mat E, and the first ground line (75) of the division lines (4) on both sides of the mat E is placed. <76) is sucking out intensively. Furthermore, this first ground line (75〉
is extended around the outside of the FM-IF block (25), multiplex decoder block <24) and noise canceller block <47>, and also sucks out the leakage current generated from these.

Also, due to wiring reasons, a third power supply line (55), (5
6), (57), (58), divided area (43)
Upper second power line (91), (92), (
93) and the second ground line (61). (6
2), (63), etc. cross over via the through holes shown by black circles and the second electrode layer shown by dotted lines. In particular, since the AM tuner block (48) does not operate simultaneously with other block circuits, the AM tuner block (48) and FM-IF block (25)
) share one pad VCCI, which results in a cross-band. The same goes for the ground bad GNDI. As mentioned above, FIG. 5 shows the FM front end block (46) and the FM-IF block (2).
5) In order to explain the separation and crossover, the configuration of the electrodes is specifically shown. The cross points are indicated by cross marks, and the through holes are indicated by black circles.

Finally, let's take a look at an example of the features of the present invention. For example, if the AM tuner block (48>) is not needed, the four mats that will become the multiplex decoder block (24) are directly integrated into the mats A to D, and the remaining mat Q
For example, mats I and J are integrated into mat R. Therefore, since the mats I, J, S, and T are redundant, by deleting these mats, the mats can be arranged neatly in a rectangular chip. Here, the first layer wiring within the mat can be used as is, and only the wiring between mats and the wiring between blocks can be considered.

Furthermore, when partially improving the FM-IF block (25), it is only necessary to take out and improve only the mat F, which is the improved part, and the other mats E, G, and H can be used as they are. Also, when adding another block that is an option for the user, you can use all the mats as is and add as many mats as you need for this block. Also, in this case, mat J is used as the mat for this gift. .

In other words, mats of the same size are formed in a matrix, making replacement, addition, and deletion very easy. (G) Effects of the Invention As is clear from the above explanation, by substantially integrating the capacitors in a circuit block in one area, leakage from the capacitors occurs! You can suck out the flow in a concentrated manner.

In particular, since the capacitors are installed in a group in one area, if a leak t-flow suction electrode is provided to surround this area, the leak can be concentrated and the effect on the circuit block can be eliminated. .

Therefore, in a semiconductor integrated circuit in which many functions are integrated into one chip, these functions can be operated without malfunction.

[Brief Description of the Drawings] Fig. 1 is a top view showing a first embodiment of the semiconductor integrated circuit of the present invention, and Fig. 2A is a top view showing a specific mat in which capacitors are integrated in Fig. 1. Figure 2B is Figure 2A
A cross-sectional view taken along line A-A' in Figure 2C is BB-B in Figure 2A.
3A is a top view showing a normal mat, FIG. 3B is a sectional view taken along line AA' in FIG. 3A, and FIG. 4 is a semiconductor integrated circuit according to the present invention. 5 is a top view showing the actual electrode pattern of FIG. 4; FIG. 6 is a block diagram of an electronic circuit incorporated in the semiconductor integrated circuit of the present invention; FIG. Figure A is a diagram for explaining the AM tuner block, Figure 7B is a diagram for explaining the FM front end block and FM-IF block, Figure 7C is a diagram for explaining the multiplex decoder block, and Figure 8 is a diagram for explaining the multiplex decoder block.
The figure is a top view of a conventional semiconductor integrated circuit, and FIG. 9 is a sectional view between block b and block C in FIG.

Claims (3)

[Claims] (1) In a semiconductor integrated circuit in which a plurality of circuit blocks are formed on the same semiconductor substrate, the capacitors in the circuit blocks are substantially integrated in one area, and the leakage current generated from the capacitors is concentratedly sucked out. A semiconductor integrated circuit characterized by: (2) Claim 1, wherein the capacitor is a MOS type capacitor surrounded by a separation region, and leakage current is intensively sucked out by an electrode electrically connected to the separation region. The semiconductor integrated circuit described. (3) A region for forming semiconductor elements substantially arranged in a matrix on a semiconductor substrate, and a plurality of circuit blocks configured using at least one of the regions, and a MOS in the circuit block. 1. A semiconductor integrated circuit comprising: a type capacitor integrated in at least one region, surrounded by a separation region, and leakage current generated from the capacitor being intensively sucked out by an electrode connected to the separation region.