JPH0666414B2 - Semiconductor integrated circuit - Google Patents

Description

The present invention relates to a semiconductor integrated circuit in which circuit blocks having different signal frequencies and signal levels such as FM / AM tuners are formed on the same semiconductor substrate.

(B) Conventional technology Electronic equipment such as TV tuners and FM / AM tuners are
Because the audio signal is extracted from the signal, the frequency of the signal handled by each circuit block divided by function is often different. For example, with an FM tuner only for Japan, the RF signal is 76 to 90 MHz, the intermediate frequency signal is 10.7 MHz,
Then, it handles audio signals of 20 to 20000 Hz and a wide range of signals of 20 Hz to 90 MHz.

An example of the FM / AM tuner is shown in FIG. In the figure, (1) is an FM front end that selects an FM broadcast and frequency-converts it to an intermediate frequency by mixing the received frequency signal and the oscillation frequency signal of the local oscillation circuit (2) in the mixing circuit (3). A circuit, (4) is an FM / IF amplifier circuit that amplifies and limits the amplitude of an intermediate frequency signal (IF signal) and detects it to obtain an audio signal (AF signal), and (5) is, for example, Japanese Patent Publication No. 62-21461. The noise cancellation circuit having the function as described in (6) is L in the case of stereo broadcasting.
A multiplex circuit for demodulating channel and R channel signals, and (7) is an AM tuner circuit for selecting an AM broadcast and outputting an audio signal. For example, in the case of FM broadcast reception,
The FM front end circuit (1) receives the RF signal input from the antenna (8) and high frequency amplified by the RF amplification circuit (9) and the oscillation frequency signal output by the local oscillation circuit (2) of the FM front end circuit (1). The IF signal is output from the FM front end circuit (1) by mixing in the mixing circuit (3) of
The composite signal is output from the FM / IF amplifier circuit (4) by detecting the IF signal in the detector circuit of the FM / IF amplifier circuit (4), and the L channel is output to the output terminal (10) by the multiplex circuit (6). , R channel audio signals are output. An FM tuner circuit having such a structure is described, for example, on page 152 of "'88 Sanyo Semiconductor Data Book Portable Audio Bipolar Integrated Circuit Edition" issued December 10, 1987.

By the way, in recent years, electronic devices have been required to be smaller and have higher performance, and accordingly, the circuit of FIG. 7 is being integrated into one chip as much as possible. However, in the example of the FM tuner, since the FM front end circuit (1) handles a high frequency signal of several tens of MHz, interference with other circuits due to unnecessary radiation is likely to occur. Further, since the weak level signal from the antenna (8) is handled, the circuit operation is likely to become unstable due to the interference with other circuit blocks, and in a remarkable case, it oscillates. Therefore, it was extremely difficult to integrate the FM front end circuit (1) into one chip.

Further, in recent years, electronic devices have become more and more diversified and diversified, and it is desired to shorten the pattern design time. Further, there are various demands for deleting, replacing, and adding a specific circuit block to a semiconductor integrated circuit whose design has been completed. However, since the specific circuit blocks are not always accommodated in the same occupied area, they have to be redesigned for each requirement, and there is a drawback that the requirements cannot be met immediately.

(C) Problem to be Solved by the Invention As described above, conventionally, it is extremely difficult to integrate the FM front end circuit (1) because circuit interference easily occurs. Also, the development period of pattern design is long,
It had a drawback that it could not meet various demands immediately.

(D) Means for Solving the Problems The present invention has been made in view of the above drawbacks, and prevents interference with other circuits by surrounding the FM front end circuit (1) with a dummy island (23). It is a thing. Also,
The surface of the semiconductor chip (11) is divided into mats (18) of substantially the same size, and each circuit block is individually matted (18).
In addition to storing it in the area for an integer number, when mounting the FM front end circuit (1), surround this area with a dummy island (23).
By surrounding with (), circuit interference is prevented and pattern design by the combination of the mat (18) is facilitated.

(E) Operation According to the present invention, since the resistance component due to the N-type high resistance layer of the dummy island (23) is present, and due to the N-type layer of the dummy island (23) and the high concentration separation region (30). Since the PN junction barrier increases the resistance component, it is possible to roughen the coupling between the two divided by the dummy island (23). Also,
Since the circuit interference can be prevented by the dummy island (23), it becomes possible to incorporate the FM front end circuit (1) into the IC formed into the mat (18) without impairing the effect of the mat (18).

(F) Example Hereinafter, the present invention will be described in detail with reference to the drawings.

The mat that makes pattern design easier first
It will be described with reference to the drawings. In the figure, the semiconductor chip (1
In the center of 1), a divided region (12) is formed so as to cross the straight line, and the element forming region of the semiconductor chip (11) is divided into two regions of substantially the same size in the vertical direction. Divided area (1
2) is a necessary unavoidable region for extending the ground line (13) and the power supply line (14) as will be described later, and is a region where no circuit element is formed. , Each of the divided two areas is the first
And the second area ( 15 ) ( 16 ). Further, a partition line (17) is provided, which is formed by adjoining and extending a pair of the ground line (13) and the power supply line (14) in a direction orthogonal to the divided area (12), and the partition line (17). By arranging a plurality of them in parallel, the surface of the semiconductor chip (11) is divided into a large number of mats (18) of substantially the same size. The size of the mat (18) is set to an occupied area in which an arbitrary number of elements can be laid out, and its width is empirically set so that 5 to 6 NPN transistors can be arranged in one row.

On both sides of the mat (18), the ground line (13) and the power supply line (14) forming the partition line (17) extend in pairs, so that they are regularly arranged, for example, facing each other in a comb shape. By extending the mat line, the ground line (13) is on one side of the mat (18) and the power line (1) is on the other side.
4) are extended so that they are in contact with each other, and operating power is supplied to the circuit elements formed on the mat (18).

The ground line (13) and the power supply line (14) extending the partition line (17) are grouped according to each circuit block and whether or not they have a common impedance, and are arranged on the divided area (12). And are individually connected to the corresponding ground electrode pad (19) and power supply electrode pad (20). As a result, a plurality of ground lines (13) and power supply lines (14) extend over the divided region (12), and each one is formed relatively wide to reduce wiring impedance. (12) naturally requires a relatively large occupied area.

In the ground line (13) and the power supply line (14) that extend the partition line (17), the ground (13) and the power supply line (14) that extend above the division area (12), and in each mat (18) The connection wiring between the circuit elements is basically performed by the first wiring layer by utilizing a comb-tooth layout.
The second and subsequent layers are mainly used to form the signal transmission wiring between the mats (18) and the shield electrode (21) across the partition line (17) and the divided region (12).

Incidentally, the divided area (12) sometimes extends in parallel with each division line (17). This is due to the positional constraints of the V _CC electrode pad (20) and the ground electrode pad (19) to the package pinout requirements, and any particular distance between adjacent mats (18) or functional blocks of the circuit. Provided between the mats (18). In FIG. 3, between the mats D and E is the former reason, and between the mats M and N is the latter reason. The V _CC line (14) and the ground line (13) are routed from the V _CC electrode pad (20) and the ground pad (19) provided near the ends of the divided regions (12a) extending in parallel. , Then the semiconductor chip (1
It is connected to the circuit elements in each mat (18) by drawing on the divided area (12) which crosses the center of 1).

When the functional circuit blocks are housed in the semiconductor chip (11) in which the element formation region is divided into a large number of mats (18) in this way, the circuit blocks are housed as follows.

First, since the mat (18) is designed to have a size that can accommodate an arbitrary fixed number of elements, the circuit block is divided into the fixed number of elements. For example, the size of the mat (18) is 10
If the circuit block is about 270 elements for storing 0 elements, prepare three mats (18) and divide each 100 elements as a guide. Of course, take into consideration capacitors that occupy a large area. Then, according to the above classification, each mat (1
8) Each circuit element is stored in the mat (18) NPN
-The connection wiring between circuit elements such as PNP transistors, diodes, resistors, and capacitors should be completed in the first wiring layer. After repeating the pattern design of all the mats (18) by repeating this, the three mats (18) are arranged adjacent to each other, and the electrical connection between the mats (18) is made by the wiring of the second and subsequent layers. By making the connections, functional circuit blocks are constructed. Then, after all the circuit blocks are stored in the mat (18), all the mats (18) are combined and the circuit layers are electrically connected to each other by the second and subsequent wiring layers to complete the whole IC. design.

According to such a configuration, by storing a plurality of circuit blocks having different functions in an integer number of mats (18), it is possible to design each circuit block and divide the circuit block into a certain number of elements. You will be able to design each mat (18). Therefore, parallel design is possible for each circuit block or mat (18), and the design period can be greatly shortened. In addition, since the circuit can be changed for each circuit block and for each mat (18), it is not necessary to change the design of the entire IC, and the parts other than the changed parts can be used while maintaining the reliability of all models.

Next, a semiconductor integrated circuit in which the FM / AM tuner circuit as shown in FIG. 7 is housed in the mat (18) will be described with reference to FIGS.

First, based on Fig. 3, the FM front end circuit (1) has about 25
As it is composed of 0 elements, 3 mats (1
8) is prepared and the whole FM front end circuit (1) is divided into 80 to 100 elements, and the mat K,
The functional configuration of the FM front-end circuit (1) is realized by housing the circuit element in each of L and M and processing the connection wiring in the mat (18) and the connection wiring between the mat (18) and the mat (18). . Similarly, the other circuit blocks are also stored in the mat (18), and the AM tuner circuit (7) is stored in the mat A to mat D and the FM.
The IF amplifier circuit (4) is used for mat E to mat I, the noise canceling circuit (5) is used for mat N to mat P, the multiplex decoder circuit (6) is used for mat Q to mat T, and other (optional) The circuits are housed in mats J, respectively, and the whole is arranged so as to fit within the rectangular shape of the semiconductor chip (11). The functional configuration of the entire IC is realized by processing the connection wiring between each circuit block.

By the way, the FM front-end circuit (1) is tuned by an antenna (8) and a tuning circuit to be described later.
The function of inputting the F signal and performing frequency conversion to an intermediate frequency (IF) signal of 10.7 MHz by mixing the RF signal and the local oscillation frequency signal output by the local oscillation circuit (2) in the mixing circuit (3) Have. In addition to the main components of the local oscillator circuit (2) and the mixing circuit (3), an amplification circuit for amplifying the IF output signal of the mixing circuit (3) and outputting it to the FM / IF amplification circuit (4) ( In many cases, other circuits associated with the main circuit such as IF / Amp) and an automatic gain control circuit (AGC) for automatically controlling the received signal level are incorporated. Since these circuits must handle high frequency signals of several tens of MHz and accurately process signals from a very small level of a few microvolts (μV) to a relatively large amplitude level, they will not interfere with other circuit blocks. The circuit I hate. Among them, the local oscillator circuit (2) is the circuit that requires the utmost attention, because the local oscillator circuit (2) must accurately perform extremely unstable operation of high frequency oscillation. On the other hand, among the other circuit blocks, the FM / IF amplifier circuit (4) that amplifies and limits the amplitude of the IF signal handles the signal of a large amplitude level, which is relatively close to 10.7MHz and handles the FM front end circuit ( This is the circuit block for which the relationship with 1) is the most important.

In order to prevent the interference between the above circuit blocks, the FM front end circuit (1) takes various measures against interference.

The first is a shield electrode (21) which covers the area where the FM front end circuit (1) is formed. The shield electrode (21) is formed of a wiring layer after the second wiring layer and is applied with a power supply potential V _CC or a ground potential GND which is AC grounded. By providing the shield electrode (21), the shield electrode (21) is fixed to a potential that is grounded in terms of AC. Therefore, the FM front-end circuit (1), in particular, the local oscillation circuit with oscillation operation ( 2) The unwanted radiation from 2) is shielded, and the interference to other circuits and the interference signal from other circuits are shielded.

At this time, if the ground line (13) and the power supply line (14) are to be formed in the first wiring layer and the shield electrode (21) is formed in the second wiring layer, there is a partition line (17). FM
The degree of freedom in designing the connection wiring between the mats (18) in the front end circuit (1) is severe. Therefore, the FM front-end circuit (1) has a two-layer wiring structure by removing the partition line (17). As described above, the FM front-end circuit (1) is housed in an area for an integral number of mats (18) regardless of whether or not the matte (18) is formed, so that a large number of mats (18) are included in the semiconductor chip (11). ) It is easy to combine them in correspondence with the square shape, and the ease of moving, replacing, deleting, etc. of the FM front end circuit (1) block is not impaired.

The pattern of the FM front end circuit (1) is shown in Fig. 4. The second measure against interference is that the local oscillation circuit (2) is provided with a shield electrode (21a) independently,
By preventing 1) from having a common impedance, the shield electrode (21) is firmly fixed to an AC ground potential to stabilize the circuit operation. This is due to interference in the FM front end circuit (1) via the shield electrode (21) and interference current from other circuits reaching the local oscillator circuit (2) via the shield electrode (21). It also prevents interference. If the shield electrode (21b) that covers the mixing circuit (3) and the shield electrode (21c) that covers the other circuits associated therewith are also divided, the circuit operation can be further stabilized.

The third countermeasure against interference is to provide a ground electrode pad (19a) dedicated to the local oscillation circuit (2) and to connect the ground line (13a).
Is also provided separately from the others to prevent interference caused by any of the ground potential GND wirings having a common impedance. The ground lines (13b) and (13c) for the mixing circuit (3) and the other circuits associated therewith are also individually extended and connected to the ground electrode pad (19). At that time, the ground line (13a) (13b) (13c) and the shield electrode (2
Connections with 1a, 21b, and 21c are made as close as possible to the ground electrode pad (19), thereby minimizing unnecessary potential rise due to wiring impedance of the ground line (13). A lead terminal for external connection is also provided exclusively for the local oscillator circuit (2). With this structure, the ground potential applied to the local oscillator circuit (2)
Stabilize circuit operation by firmly fixing GND and avoiding interference from others.

The fourth countermeasure against interference is to arrange the local oscillator circuit (2) at the most corner of the FM front-end circuit (1) so that the local oscillator circuit (2) can be moved from the FM / IF amplifier circuit (4) to the maximum. Place at a limited distance. With this configuration, the local oscillator circuit (2) is separated from the distance, and the periphery of the local oscillator circuit (2) is mixed with the mixing circuit (3) and the shield electrodes (21b) (21c) for the other circuits. Is surrounded by FM,
Signal interference from the IF amplifier circuit (4) can be minimized. Separation to the corner also makes it possible to minimize the length of extension of the ground line (13a) from the ground electrode pad (19a) to the local oscillation circuit (2), thus ensuring stable operation of the local oscillation circuit (2). Will also contribute.

The fifth countermeasure against interference is to provide a suction electrode (22) in ohmic contact with the semiconductor substrate in the FM front end circuit (1) region. The suction electrode (22) is connected to the ground line (13c) extending between the local oscillation circuit (2) and the mixing circuit (3) and the other circuits associated therewith to prevent leak current flowing between them. In addition to sucking out, NPN / PNP transistors that perform saturation operation in circuit elements,
The leak current is absorbed by being provided in the immediate vicinity of a circuit element such as a capacitor and a resistor which is expected to leak the leak current. Is the leaked current leaked out as it is to the ground electrode pad ((19b) via the ground line (13c)?
Or the shield electrode (21a) (21b) (21
Ground line (13b) (13c) (13d) that is sucked into c) and contacts the shield electrodes (21a) (21b) (21c)
Is connected to the ground electrode pads (19a) and (19b) via. Only for the local oscillator circuit (2), a ground line (13d) that applies the ground potential GND to the suction electrode (13d) and the shield electrode (21a) and a ground line that applies the ground potential GND to the circuit elements that make up the local oscillator circuit (2). By providing (13a) separately, ground potential GN due to leaked leakage current
D Avoid the effects of rising. With such a structure, mutual interference due to a leak current through the substrate surface is prevented.

The sixth countermeasure against interference is to surround the FM front end circuit (1) housing area with a dummy island (23) as a feature of the present invention.

In FIG. 1, (24) is a storage area for the local oscillator circuit (2), (25) is a storage area for the mixing circuit (3), and (26) is a storage area for the other circuits attached thereto. The entire front end circuit (1) block is completely surrounded by the dummy island (23), and only the storage area (24) of the local oscillation circuit (2) is further partitioned by the dummy island (23a). Ground potential GND for the circuit element of the local oscillator circuit (2)
A region for forming a dedicated ground electrode pad (19a) for supplying the electric field is also housed in the dummy island (23a) surrounding the local oscillation circuit (2), and the ground potential is applied to the substrate through the isolation region. The dummy island (23) is a region surrounded by a high-concentration isolation region connected to the substrate and electrically insulated from the others, so the dummy island (23) is in a floating state where no power supply potential V _CC or any potential is applied. Put in a state.

The FM front end circuit (1) that has processed the shield electrode (21), the suction electrode (22) and the dummy island (23).
The sectional structure of the part is as shown in FIG.

In FIG. 5, (27) is a P-type semiconductor substrate, and (28) is N.
Type epitaxial layer, (29) N ⁺ other buried region, (30) P ⁺ type isolation region connected to the substrate (21), (31) island for element formation, (23) (23a) dummy Island,
(32) and (33) are P or N type diffusion regions for forming circuit elements, (34) is an oxide film covering the epitaxial layer (28),
(35) is an inter-element connection wiring by the first wiring layer, (13
b) (13c) is the ground line, (22) is the suction electrode,
(36) is an interlayer insulating film, and (21a) and (21b) are shield electrodes by the second layer wiring. As is clear from the figure, the dummy islands (23) (23a) are epitaxial layers (28).
A P ⁺ type isolation region (30) reaching from the surface to the surface of the substrate (27) to which the ground potential GND is applied is formed by partitioning the epitaxial layer (28). According to such a configuration, the resistance component is inserted between the regions on both sides of the dummy island (23) by the N-type high resistance layer of the dummy island (23), and therefore flows in the horizontal direction with the substrate (27). It is possible to prevent the leakage current from passing therethrough and prevent circuit interference due to the leakage currents of both. Further, since the resistance component of the potential barrier of the PN junction formed by the dummy island (23) and the isolation region (30) substantially increases, the coupling between the circuits can be further roughened. The dummy island (23) (23
If it is used as an extension area of the ground lines (13b) (13c) or the power supply line (14) on a), the occupied area can be effectively used.

In addition to the interference measures in the FM front end circuit block (1) part described above, it is possible to further prevent the interference by using the divided area (12). That is, as described above, since the divided area (12) requires a relatively large occupied area,
The FM front end circuit (1) is arranged at the corner of the semiconductor chip (11) by utilizing the matte K to matte M or the corresponding region, and the FM / IF amplifier circuit (4) is formed by the matte E to matte I. By using, both are arranged with the divided area (12) sandwiched therebetween. With such a configuration, both can be separated by the amount of the divided area (12), and thus mutual interference can be minimized.

In addition, as shown in FIG. 2, the area occupied by the divided region (12) is used to make a dummy island (23) as shown in FIG. 5 in this region.
By providing a large number of elements, it is possible to further prevent mutual interference due to leak currents.

Fig. 6 also incorporates the above FM front end circuit (1).
It is an FM / AM receiver configured using an IC. In the figure, ( 40 ) is the RF signal tuned by selecting the receiving frequency.
FM front-end circuit (1) mixed circuit (3) or AM
A tuning circuit for outputting to the mixing circuit of the tuner circuit (7),
( 41 ) and ( 42 ) are composed of a surface acoustic wave filter (43) and extract only the FM / IF signal from the output signal of the mixing circuit (3).
1, 2nd filter circuit, ( 44 ) is FM / local oscillation circuit (2)
The passive circuit element of the local oscillation circuit (2) that determines the oscillation frequency of ( 45 ) is the crystal oscillator that determines the oscillation frequency of the voltage controlled oscillation circuit (VCO) of the multiplex decoder circuit (6), and ( 46 ) is A filter circuit for passing only the AM / IF signal, ( 47 ) is a passive circuit element of the local oscillation circuit of the AM tuner circuit (7), and ( 48 ) is an output terminal of the L and R channels. In addition, the entire circuit is realized by externally attaching capacitors and resistors having a value that is difficult to integrate in terms of element constants.

According to the above configuration, basically, it is possible to externally attach a passive circuit element such as a large-capacity capacitor, resistor, or varistor, which is difficult to integrate, and an FM / AM tuner by only externally attaching a tuning circuit ( 40 ). Since it can be realized, an inexpensive tuner can be constructed by reducing the number of parts.

(G) Effect of the Invention As described above, according to the present invention, the FM front end circuit (1) is surrounded by the dummy islands (23) to prevent interference, and the FM front end circuit (1) also includes one chip. It has the advantage of realizing a simplified IC.

Also, since the entire IC is laid out by using the mat (18) as a base and combining the mat (18), it is possible to design in parallel for each circuit block or each mat (18), greatly reducing the pattern design period. Can be achieved. Also, the circuit can be changed for each circuit block or for each mat (18),
There is no need to change the design of the entire IC, and it has the advantage that it can be used while maintaining the reliability of the previous model except for the changed portion.

Since the FM front-end circuit (1) can be stored in the area for the integer number of mats (18) and interference can be prevented by the dummy island (23), the FM front-end circuit (1)
The block can be treated like other circuits, and there is an advantage that the ease of pattern design by combining the mat (18) is not impaired.

Since the semiconductor integrated circuit can also be integrated into the FM front-end circuit (1) on a single chip, a circuit forming a tuning circuit ( 40 ) with a passive circuit element such as a capacitor, resistor, or varistor that is difficult to integrate in value. By adding an element,
It has the advantage that an inexpensive and high-performance FM / AM tuner can be constructed.

[Brief description of drawings]

1 is an enlarged plan view of an essential part for explaining the present invention, FIGS. 2 and 3 are plan views for explaining the present invention, and FIG. 4 is an FM.
5 is an enlarged plan view showing the front end circuit (1) part, FIG.
4 is a cross-sectional view of the main part of FIG. 4, FIG. 6 is a circuit diagram for explaining the radio receiver of the present invention, and FIG. 7 is a circuit diagram showing an FM / AM tuner circuit. (11) is a semiconductor chip, (12) is a divided area, (13) is a ground line, (14) is a power line, (17) is a partition line, (18) is a mat, (19) is a ground electrode pad,
(21) is a shield electrode, (23) is a dummy island,
(30) is a separation area, and ( 40 ) is a tuning circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 27/06 H04B 1/08 E 7240-5K

Claims (4)

[Claims] 1. At least a local oscillation circuit and a mixing circuit are included.
A front end circuit block that frequency-converts an RF (Radio Frequency) signal into an IF (intermediate frequency) signal and an IF amplifier circuit block that amplifies and limits the amplitude of the IF signal are stacked on a semiconductor substrate of one conductivity type. It is integrated into an epitaxial layer of conductivity type, and is completely formed by an island region composed of the epitaxial layer surrounded by a high-concentration isolation region of the same conductivity type that connects the periphery of the front-end circuit block to the semiconductor substrate fixed to the ground potential. A semiconductor integrated circuit characterized in that the local oscillation circuit is completely surrounded by the island region so as to completely separate the local oscillation circuit from the other front end circuit block. 2. Located on a semiconductor layer of a semiconductor chip,
A semiconductor element arrangement region (mat) formed in the semiconductor layer, which has a plurality of shapes of substantially the same size, and a plurality of electronic circuit blocks whose functions are substantially different in circuit size. A linear semiconductor integrated circuit in which the semiconductor element of the linear electronic circuit is formed in the arrangement area (mat), and the electronic circuit block divided by the function is a front end circuit block including at least a local oscillation circuit. All the semiconductor elements of the electronic circuit block are substantially divided into a plurality of placement areas (mats) obtained by dividing the total number of semiconductor elements of the electronic circuit block in units of the placement area (mat). Formed of a semiconductor layer, and the front-end circuit block is surrounded by a high-concentration isolation region fixed to a ground potential. Linear-type semiconductor integrated circuit, characterized in that it completely surrounds the area. 3. A division region for substantially dividing the semiconductor chip into a first region and a second region, and a division region positioned in the first region and the second region in the center of the semiconductor layer of the semiconductor chip, A semiconductor element arrangement region (mat) formed in the semiconductor layer, which has a plurality of shapes of substantially the same size, and a plurality of electronic circuit blocks whose functions are substantially different in circuit size. In the linear semiconductor integrated circuit, in which the semiconductor element of the linear electronic circuit is formed in the arrangement area (mat), the electronic circuit block divided by the function includes a front end circuit block including at least a local oscillation circuit. However, all the semiconductor elements of the electronic circuit block are obtained by dividing the total number of semiconductor elements of the electronic circuit block in units of the arrangement area (mat). The front end circuit block is substantially formed in a plurality of arrangement regions (mats), and the periphery of the front end circuit block is completely surrounded by an island region formed of the semiconductor layer surrounded by a high concentration isolation region fixed to a ground potential. A linear semiconductor integrated circuit characterized by: 4. The local oscillation circuit is completely surrounded by the island region so as to completely separate the local oscillation circuit and the other front end circuit blocks from each other. Linear semiconductor integrated circuit.