JPH0251250A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable concurrent designing, and remarkably shorten the design time by dividing the upper surface of a semiconductor chip into many mats of substantially the same size with sectioning lines and incorporating a plurality of electronic circuit blocks of different functions in the integral number of the mats. CONSTITUTION:The upper surface of a semiconductor chip 10 is divided into first and second areas 12 and 13 of substantially the same shape with a division area 11 indicated with a two-dot chain line. The areas 12 and 13 are divided into mats A-J and K-T respectively. Sectioning lines 14 including electric source lines and adjacent ground lines stretched in parallel are placed between the mats to section each mat. The electric source lines are installed on the left side of each mat A-J and K-T and the ground lines on the right side. Therefore, only the sectioning lines 14 on both the ends comprise one of the electric source and the ground lines and intermediate sectioning lines comprise both the electric source and the ground lines. The electric source and the ground lines adjacent to each mat A-J and K-T are integrated in each mat and supply a current to a circuit block.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to semiconductor integrated circuits, and particularly to semiconductor integrated circuits having a back-to-back layout that allows for easy model development in order to meet the demands of custom ICs. The present invention further relates to a semiconductor integrated circuit that prevents interference.

(b) Conventional technology in general is disclosed in Japanese Unexamined Patent Publication No. 59-84542 (HOIL
21/76), multiple circuit blocks are
-1'': The semiconductor integrated circuit technology formed on the conductive substrate has the configuration shown in FIG.

FIG. 11 is a schematic plan view of the semiconductor chip (1),
a to r indicate circuit blocks. These circuit blocks handle different frequencies and signal levels, and have different functions.

This circuit block is formed in an N-type region (3) on a P- type semiconductor substrate (2) as shown in FIG. 4
). Here, they are shown as block b and block C. be.

The P″″-shaped area (4) for this partition has one end connected to P-
The other end is connected to the ground line (6) through the oxide film (5) on the semiconductor surface.

A ground line (6) is gathered from each block to the center of the integrated circuit and extends to the ground bonding pad GND at the left end.

Next, the power supply line (Vcc) of each block circuit is connected to the 11th
As shown in the figure, they are grouped around the outer periphery of the integrated circuit and each is individually connected to a t-source bonding pad.

On the other hand, since the circuit blocks a to f have different functions, the number of elements present in each block is different, and the block sizes are different from each other.

(c) Problems to be Solved by the Invention As mentioned above, since the circuit blocks a to r have different sizes, all of these circuit blocks can be efficiently integrated into a semiconductor chip (
1) In order to fit within the same chip, the sizes of each circuit block interact with each other, making it difficult to integrate them into the same chip.

Also, if you delete circuit block a and insert another circuit block a with improved characteristics, or if you try to add circuit block g with another function to the circuit block configuration shown in Figure 11, each block Because the sizes were different, it was necessary to recreate all the patterns.

Therefore, in recent years, the lifespan of products has become extremely short, and when a user tries to incorporate a unique circuit desired by a chip into a certain chip, even though the user wants a short delivery time, the circuit The problem was that it required a very long lead time to remake the pattern.

Further, wiring such as signal wiring and feedback lines between circuit blocks has the problem of interference caused by unnecessary radiation from high frequency circuit blocks.

(d) Means for Solving the Problems The present invention has been made in view of the above problems, and consists of dividing the semiconductor chip into first and second regions in the center of the semiconductor chip, and dividing the semiconductor chip into first and second regions. The area is divided into a large number of mats of substantially the same size by dividing lines, a plurality of electronic block circuits with different functions are integrated into an integral number of mats, and a second ground line and a second ground line are formed in the divided area. In addition to the power supply line, provide a wiring area and use this wiring as a signal line or feedback line between electronic circuit blocks.
This problem can be solved by providing a shield metal over this wiring.

Further, the problem is solved by providing second and third divided regions in the first and second regions, respectively, and providing shielded wiring similarly to the divided regions.

(*) Effect According to the present invention, the upper surface of a semiconductor chip is divided into a large number of mats of substantially the same size along a partition line, and a plurality of electronic circuit blocks with different functions are housed in an integral number of mats. , it becomes possible to design each electronic circuit block, and to divide the electronic circuit block into a fixed number of elements to design each mat. Therefore, parallel design can be performed by dividing each electronic circuit block, and the design period can be significantly shortened.

Furthermore, since circuit changes can be made for each electronic circuit block and for each mat, there is no need to change the design of the entire IC.

On the other hand, the dividing area divides the semiconductor chip into first and second areas and extends from the left side to the right side of the semiconductor chip, and by effectively using this area, wiring can be prevented from crossing other electrodes. provided.

In other words, in FIG. 1, the divided area between mat E and mat J or between mat K and mat M is not provided with the first and second extension electrodes in the vertical direction, so the wiring is routed within this area. Can be set arbitrarily. Also the second and third
The divided areas are similarly provided in the vertical direction.

Furthermore, by providing a shield electrode on this wiring, unnecessary radiation from the area adjacent to this wiring is not received, and interference can be prevented.

(f) Embodiment First, an embodiment of the present invention will be described in detail with reference to FIG. Here, for convenience of explanation, the structure of mat division, which is one of the features of the present invention, will be described.

The upper surface of the semiconductor chip (10) is divided into divided regions (
11), the first and second
It is divided into two areas (12) and (13), and each area (12) and (13) is divided into A-J and -T mats. The mats A-J and A-T are separated by partition lines (14) in which a power supply line and a ground line extend adjacently and in parallel.

The arrangement of the power supply lines and ground lines forming the partition lines (14) is such that the power supply lines are provided on the left side of each mat A-J and -T, and the ground lines are provided on the right side.

Therefore, only the partition lines (b) at both ends are formed of either the power supply line or the ground line, and the middle partition line is formed of both. The power supply line and ground line adjacent to each mat A-J, -T are integrated in each mat, and supply power to the circuit blocks.

The first area (12) is the third area (15), which is matte A to matte D1, and the fourth area (16), which is matte E to
Pine l-J is divided by a second division area (17). Further, the second area (13) is connected to the fifth area (18).
) is divided into mats N and T, which are the sixth region (19) and mat M1, by the third divided region (2o).

The first power supply line (21) of mat A to mat D is connected to the third power line (21) formed at the upper end of the mat. source line (22) and extends to t*bad v cct. In addition, the first power line (23) of mat E to mat J is
A second layer electrode (25) connected to the third power line (24) formed on the upper edge of the mat and hatched with a dot.
and the third region (15)
The power line (22) is disconnected.

On the other hand, the first ground line (2
6) is connected to a second ground line (27) formed at the lower end of the mat, and extended to the ground pad GNDI via a second extension electrode (28). Also, the first ground line (29) of mat E to mat J is the second ground line (30) formed at the bottom end of the mat.
The second layer electrode 〈31
) and is connected to the second ground line (27) of the third region (15).

Also, between matte and matte, which will become clear later, Vc
c+, Vcc*, GND1, GND
2 uses a separate power supply and ground pad.

Also, the first power line (32) of Mat N-Mat T is connected to the second power line (33) formed at the upper end of the mat.
and is extended to the power supply pad VCC□ by the first extension electrode 〈34). The first of the mats N-T
The ground line (35) is connected to a third ground line (36) formed at the lower end of the mat, and extends to the ground pad GND2. Also, clockwise from the left side of mat E, there is a ground line (3
7) is extended and connected to the ground pad GND2.

Each mat A- divided by the above-mentioned division line (14)
J, ni-T are formed into shapes of substantially the same size, specifically, the width is set so that six NPN transistors are lined up, and the length is set to a certain number of elements that is easy to design. , for example, so that about 100 elements can be laid out. The size of this mat can be arbitrarily selected depending on the number of elements that can be easily designed depending on the electronic circuit block to be integrated.

The circuit elements integrated within the mat are composed of transistors, diodes, resistors, and capacitors, and are separated by normal PN isolation, and the connections of each element are connected by the first electrode layer of the two-way wiring. Basically, it is crossed over at the second layer TSI.

Next, with reference to FIGS. 8A and 8B, the circuit elements integrated within the mat and the partition lines (14) will be specifically described.

FIG. 8A is an enlarged top view of the vicinity of mat B.

The division line (40) indicated by the dashed line on the left is mat A.
The partition line (14) shown by the dashed line on the right is the partition line (14) provided between the mat B and the mat C. A transistor (42), a diode (43), a resistor (44), and a capacitor (45) shown by dotted lines are integrated between the partition lines (40) and (41). Although these elements are shown sparsely in the drawing, they are actually densely integrated. In addition, the wiring between elements within the mat is connected to the first electrode layer (46
), and wiring between mats A and B and between mats B and C, such as signal lines and feedback lines, is shown by solid lines in the second electrode layer (
47). These first and second electrode layers (46) and (47) are connected at a contact area indicated by an X mark.

FIG. 8B is a sectional view taken along line AA' in FIG. 8A. An N-type epitaxial layer (49) is laminated on a P-type semiconductor substrate (48), and this epitaxial layer (
49) P“ reaching the semiconductor substrate (48) from the surface
A mold separation region (50) has been formed, and a number of island regions have been formed.゛In this island region (51) there are an NPN transistor (42) and a diode (43).
), a resistor (44), a capacitor (45), etc. are made, and the left field (42) of the NPN transistor (42) is
An N'' type buried region (53) is formed between the semiconductor substrate (48) and the epitaxial layer (49).A silicon oxide film (54) is formed on the surface of the epitaxial layer (49) by, for example, the CVD method. This silicon oxide film (54
>A third electrode layer (46) is formed on the top. Further, an insulating film (55) such as PIX is formed to cover this first electrode layer (46), and a second electrode layer (47) is formed on this insulating film (55). Also, the tl [line (56) and the ground line (
57) is provided on the isolation region (50), and the ground line (57) is in ohmic contact with this isolation region (50) to stabilize the substrate potential.

More specifically, as shown in FIG. 1, ten mats A to J are formed in the first area (12), and in the second area (13).
Form 10 mats of Ni-T, and divide the mats into approx.
The mats have substantially the same space in which 0 elements can be integrated, and the mats are separated by partition lines (14).

The 20 mats listed above contain AM/FM as shown in Figure 9.
A 1-chip stereo tuner IC is formed. 9th
The figure is a block diagram explaining this electronic block circuit, and includes a 1M front end block (60), FM-IF
block (61), noise canceller block (62)
), multiplex decoder block (63), A
It is composed of a total of five electronic circuit blocks including an M tuner block (64). Although each circuit block is well known, its function will be briefly explained.

First, the 1M front end block (60) is the FM broadcast channel selection part, which receives the FM broadcast signal of several tens of MHz to several hundred MHz and converts the frequency into an intermediate frequency signal of 10.7 MHz. There are about 250 of them, so they are integrated into the -M mat. Next, FM-I
The F block (61) amplifies this intermediate frequency signal and then detects it to obtain an audio signal, and has approximately 430 elements, so it is integrated on the mats E to E. Next is the noise canceller block (62)
The device removes pulse noise such as ignition noise, and has approximately 270 elements, which are integrated into an NP mat. Further, the multiplex decoder block (63) is a block for stereo demodulating a stereo signal, and since it has about 390 elements, it is integrated into a QT mat. Finally, the AM tuner block (64) is the AM broadcast tuning part, which converts the AM broadcast signal received by the antenna to an intermediate frequency (450 KHz>) and detects it to obtain an audio output. Since it has 100 elements, it is integrated in A-D mats.

Furthermore, an AM tuner block (64), a front end block (60), an FM-IF block (61), and a multiplex decoder block (63) are further added to FIG. 10A1, FIG. 10B, and FIG. 10C, respectively. A block diagram is shown.

First, the local oscillation circuit (OS C) (65) in the AM tuner block (64) in Fig. 10A is connected to Matsu l-A.
A mixing circuit (MI
RF) <68) and intermediate frequency amplification circuit (IF) (
69) is substantially integrated in the mat C, the detection circuit (DET) (70) is substantially integrated in the mat D, and the third '1l is extended in four octopus-like shapes from the power supply pad Vcc+ as in the first U9J.
Vcc is supplied to the first power supply line (21) of the A-D mats via the JX line (22). Further, the ground pad GND 1 is connected to the second electrode on one end of the first divided area (11) via four second extension electrodes (28) in the shape of a kite foot provided between the mat M and the pine (pine)-N. are connected to the ground line (27) of the respective second ground lines (
27) is the first ground line (26
)It is connected to the.

Next, the high frequency amplification circuit (71) and the mixing circuit (
72) and a local oscillation circuit (73), the front end block (60), which is composed of a local oscillation circuit (73), handles signals at an extremely small level of several μV, so it
It dislikes interference from the F block (61), and the local oscillation circuit (73) in this block oscillates by itself.
Generates unnecessary radiation. Therefore, especially FM-IF
<61) and the OSC block (73)
Since interference is the least desirable, separate power supply V CC3 * Vcc4.
GND3 and GND4 are used.

That is, the FM-IF block (61) is integrated on a mat of -M diagonally, a local oscillation circuit (73) is integrated on the mat K which is the most corner, and other pads V are placed on both sides thereof. A first power supply line and a ground line are provided through C4 and GND4. Also other glue, M
The mat is connected through V c c s and GND3,
Respective first power lines and ground lines are provided.

On the other hand, the FM-IF block (61), which is composed of an intermediate frequency amplification circuit (74), a detection circuit (75), an S meter (76), etc., is integrated on a mat from E to E, and the detection circuit (75) is matte, and S meter (76) etc. is matte G.
Furthermore, a limiter circuit, a mute circuit, etc. in the intermediate frequency amplification circuit (74) are substantially integrated on the E, F, and G mats.

Here, the limiter circuit with an extremely high gain of 80 to 100 dB, the detection circuit (75) with a large signal level, the limiter circuit and the S meter (76) with a large signal level generate oscillation due to feedback, and the detection circuit (75) and the S meter (76) have a high signal level. Meter (76
), the characteristics deteriorate due to mutual interference, so matte E,
The first power line (23) of F and G is connected to the third power line (24) of one tree, and the first power line (23) of mat H2■ is connected to one third power line (24). 24). Mat J also integrates optional circuits provided by the user, and this first power supply line (23
) is also connected to one third 'rIt source line).

Also, the first ground line (29
) is connected from the ground pad GNDI to the second extension electrode (2
8) is extended and connected to the second ground line (27), which is connected at one end, in the same manner as described above.

Next, the DC amplifier circuit (77) and decoder circuit (77) of the multiplex decoder block (63) in FIG.
78), the lamp driver circuit (79) is connected to the mat Q and the mat R, and the phase comparator circuit (80), the low-pass filter circuit (81), the voltage controlled oscillator (82), the frequency dividing circuit (83), etc. are connected to the mat S. It is substantially integrated into the mat T. Also power supply pad VcC! The first extension electrodes (34), which have been extended into three octopus-like shapes, pass between the AM tuner block (64) and the FM-IF block (61), and are connected to the first divided area (11). One end is connected to the upper second power supply line (33). And one is matte Q and R
One tree extends to mats S and T, and one tree extends to mats N to P, which serve as noise canceller blocks (62).

On the other hand, the ground bad GND2 has two thirds like an octopus.
connected to the ground line (36) of the
NP mat, Q, R mat, S.

It extends to the T mat.

Furthermore, pad V is used to prevent mutual interference between blocks.
CCr + V CCI, pad GNDI, GND2
Use Pad V for a minute each. CI + VCCI is 1
The pads GNDI and GND2 are connected to the leads of the tree. This is pad Vcct
The variation of pad V directly. Prevent telling the CI! To,
Furthermore, by using two thin metal wires, the impedance of the thin metal wires is lowered. Therefore, pulse noise or the like that enters the lead is not amplified through the impedance, and voltage fluctuations can be prevented.

The above is an explanation of mat division, and let us take an example of this characteristic point. For example, if the AM tuner block (64) is not needed, the four mats that will become the multiplex decoder block (63) can be integrated into the A-D mats, and the remaining mats Q and R can be used as mats I and J.
Integrate. Therefore, since the I, J, S, and T mats are redundant, by deleting these mats, the mats can be arranged neatly in a rectangular chip. Here, the first layer wiring within the mat can be used as is, and only the wiring between mats and the wiring between blocks need be considered.

Also, when partially improving the FM-IF block (61),
For example, it is only necessary to take out the mat F, which is the improved part, and improve it, and the other mats E, G, and H can be used as they are. Also, when adding another block that is an option for the user, all the mats can be used as is and only the required number of mats can be added to this block, and in this case mat J is used as the mat for this option.

In other words, since mats of the same size are formed in a matrix, replacement, addition, and deletion are very easy.

Next, I will explain about the shield electrode. The hatched area in FIG. 1 is a shield electrode, and the structure of this shield electrode is shown in FIGS. 3 to 7. Also, thick solid lines indicate wiring.

As mentioned above, in the first divided region (11), the second power supply line (33) and the second ground line (30) are provided in parallel from the left side to the right side in the first layer. Second
In the divided region (17) and the third divided region (20), a first extension electrode (34> and a second extension electrode (28) are provided in the first layer. If the width of region (11) is widened, for example, the second ground line connected to the first ground line of mat F and mat G <30
), it is possible to widen the distance between the first ground line of the mat H and the mat E and the second ground line (30) that is read directly.

Therefore, wiring can be provided from mat H to point r. Furthermore, if the distance between the second ground line (30) of mat J and the second X* line (33) of mat S and mat T is widened, wiring can be provided from below mat E to below mat J. Can be done.

In this way, the first extension electrode (34) and the second extension electrode (
28) is concentrated in the first divided region (
11) can be used as a wiring area. The second and third divided areas (17) and (20) can be utilized in the same way, and an example is shown with wiring connecting mat M to mat E through points a, b, and c.

To describe the wiring in more detail, the wiring extending from the mat H extends horizontally to point f, and extends vertically from point f to point e, and is formed in the first layer. Points e to d are formed in the second layer to cross over with the second its line (33). Further, the wiring extending from the mat M is horizontally extended from point a until it reaches the point, and is formed in the second layer in order to cross over the second extension 721 (28). The electrodes up to point C are formed in the first layer in order to avoid the electrodes in the second layer hatched with dots. The area from the point C to the remat E is formed in the second layer in order to cross over the first extension electrode (34). In the above configuration, substantially all of the wiring portions formed in the first layer are provided with shield electrodes in the second layer. An example of this is shown in the hatched area. The relationship among the shield electrode, wiring, and semiconductor substrate is shown in FIGS. 3 to 7 as cross-sectional views taken along line AA' in the figures.

In addition, FIG. 2 shows the first to third divided areas (11).
, (17), and (20), this dummy island (90) is
As shown in the figure, there are four layers, but this number is not limited to this. As can be seen from FIG. 3, this dummy island (90) is a semiconductor substrate (91) to which a ground potential is applied.
), the barrier is formed by this PN junction, making it possible to prevent leakage current.

Next, the cross-sectional views shown in FIGS. 3 to 7 will be explained. First, in FIG. 3, there are two N-type dummy islands (90) surrounded by a P-type isolation region (92), and through the first layer of insulating film on these dummy islands (90), Wiring <
93〉 or provision. A first shield electrode <94) is provided on both sides of this wiring (93), and this wiring (93)
A second layer of insulating film is formed to cover the first shield electrode (94), and further makes ohmic contact with the first shield electrode (94) via this second layer of insulating film. , first shield electrode (94) and arrangement (93)
A second shield electrode (95) is formed to cover the. Here, VCC or GND may be applied to the second shield electrode (95).

Next, FIG. 4 is almost the same as FIG. 3, but 1) the first shield electrode (94) of II is in ohmic contact with the N-type island region (90). Here the second
The shield electrode (95) may be applied to Vcc.

Next, in FIG. 5, a first shield '1IJi (94) is in ohmic contact with a P-type isolation region (92), and wiring is provided in a dummy island region (90). Therefore, the second shield electrode (95) is applied to GND.

Next, FIG. 6 shows a three-layer structure unlike the above-mentioned example. The first shield electrode (
94) is in ohmic contact with the isolation region (92). A wiring (93) is formed in the second layer, and second shield electrodes (95) are formed on both sides of this wiring (93) in ohmic contact with the first shield electrode (94), and A third shield electrode (96) of a third layer is formed to cover the second shield electrode (95) and the wiring (93).

Here, the first shield electrode (94) of the first JI may be, for example, the same as the polysilicon resistor formed in the mat, and the above-mentioned configuration is similar to the single-core shield wire used conventionally. produces a similar effect.

Furthermore, FIG. 7 shows a wiring (93) on the P-type isolation region (92).
) and a shield electrode are provided, and here the first
Although the shield electrode (94) is in ohmic contact with the isolation region (92), this is not the case.

Alternatively, a three-layer structure as shown in FIG. 6 may be used. Above wiring (93)
The above description has been made in the case where the first divided area (11) is provided, but the second and third divided areas (17) are provided on the first divided area (11).

Similarly, for (20), the configurations shown in FIGS. 3 to 7 can be implemented.

(g) Effects of the invention As is clear from the above explanation, firstly, the upper surface of the semiconductor chip (10) is divided into a large number of mats of substantially the same size along the partition line (b), and a plurality of mats with different functions are divided into mats. When circuit blocks are housed in an integral number of mats, each electronic circuit block can be designed in parallel, and the design period can be significantly shortened. Furthermore, since the electronic circuit block can be divided into a fixed number of elements and designed for each mat, parallel design for each mat can be performed.

Further, since circuit changes such as deletion, addition, and modification can be designed for each electronic circuit block or each block, it is sufficient to make changes for each block or each mat, and there is no need to change the design of the entire IC. Furthermore, since mats can be made into cells as basic blocks, once the design is completed, when changing the circuit afterwards, only the mats to be changed need to be modified, and the other mats can be used as is, resulting in extremely high reliability.

Furthermore, by widening the widths of the divided regions (11), (17), and (20), the wiring (93) can be provided in these divided regions. Moreover, by changing the positions of the second ground line (30) and the second t-source lining (33), the first division excluding the first and second extension electrodes (34) and (28) can be achieved. Wiring can be horizontally provided in the region (11) with any length.

On the other hand, by changing the positions of the first and second extension electrodes, the second and third divided regions (17)
, (20) are also provided with wiring.

Second, divided areas (11), (17), (20
) and dummy islands (92) and dummy islands (
90), it can be effectively shielded. In other words, as shown in FIG. 3, the first and second shield electrodes (94
), (95) can prevent unnecessary radiation from above and from the sides. Also, Fig. 4 shows the N-type island region (90), Fig. 5 shows the P-type isolation region (92) and the semiconductor substrate (91), and Fig. 6 shows the first shield electrode (94).
), FIG. 7 shows that the lower layer of the wiring can also be shielded by the P-type isolation region (92), and can be used like a single-core shielded wire used conventionally. Therefore, interference can be prevented without receiving unnecessary radiation from the electronic circuit block.

[Brief explanation of the drawing]

1 is a plan view showing a semiconductor device of the present invention, FIG. 2 is a diagram showing a dummy island formed in FIG. 1, FIG. 3 is a diagram showing an example of the shield electrode used in FIG. 4 shows an example of the shield electrode used in FIG. 1, FIG. 5 shows an example of the shield electrode used in FIG. 1, and FIG. 6 shows an example of the shield electrode used in FIG. 1. FIG. 7 is a diagram showing an example of the shield electrode shown in FIG. 1, FIG. 8A is a partially enlarged view of mat B, and FIG. 8B is A-
9 is an AM/FM stereo tuner block circuit diagram, FIG. 10A is an AM tuner block diagram, and FIG. 10B is a diagram explaining the FM front end block and FM-IF' lock. , FIG. 10C is a block diagram of a multiplex decoder, and FIG. 11 is an iPPN2 of a conventional semiconductor integrated circuit. FIG. 12 is a sectional view between block b and block C in FIG. <10)...Semiconductor chip, (11)...Divided area, (12)...First area, (13)...Second area, (14)...Partition line, ( 15)...
Third area, (16)...Fourth area, (17)
...second divided area, (18)...fifth area,
(19)...Sixth region, <20)...Third divided region, (27), (30)...Second ground line, (33)...Second power supply line , (9
0)...Dummy island, (93)...Wiring,
(94)...first shield electrode, (95>...
- Second shield electrode, (96)...Third shield electrode.

Claims (14)

[Claims] (1) Place this semiconductor chip in the center of the first
and a divided area that is substantially divided into a second area, and a plurality of identical dividing lines that are orthogonal to the divided area and extend adjacent to each other as a set of a first power supply line and a first ground line on both sides thereof. the first and second
a mat formed by dividing a region into a plurality of regions of substantially the same size; a plurality of electronic circuit blocks having different functions that are incorporated into the semiconductor chip and formed in an integral number of the mats, respectively; a second ground line and a second power supply line formed on the divided region and connected to the first ground line of the first region and the first power supply line of the second region, respectively; A semiconductor integrated circuit comprising: a wiring connecting mats formed substantially parallel to a second power supply line and a second ground line; and a shield electrode shielding the wiring. (2) The semiconductor integrated circuit according to claim 1, wherein the divided region is provided with one or more dummy islands surrounded by isolation regions. (3) The shield electrode has a two-layer structure, in which the first shield electrode formed in the first layer is provided on both sides of the wiring, and the second shield electrode formed in the second layer is provided on both sides of the wiring. 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit covers the first shield electrode and wiring and makes ohmic contact with the first shield electrode over substantially the entire surface. (4) The shield electrode has a two-layer structure, and the first shield electrode formed in the first layer is provided on both sides of the wiring, and the dummy island covers substantially the entire surface of the first shield electrode. 2. A second shield electrode formed in a second layer, which is in ohmic contact, covers the first shield electrode and the wiring, and is in ohmic contact with the first shield electrode over substantially the entire surface. The semiconductor integrated circuit described. (5) The shield electrode has a two-layer structure, and the first shield electrode formed in the first layer is provided on both sides of the wiring, and covers substantially the entire surface of the first shield electrode, and has a dummy island. make ohmic contact with the surrounding isolation area,
The second shield electrode formed in the second layer is the second shield electrode formed in the second layer.
3. The semiconductor integrated circuit according to claim 2, wherein said semiconductor integrated circuit covers said first shield electrode and wiring and makes ohmic contact with said first shield electrode over substantially the entire surface. (6) The shield electrode has a three-layer structure, and the first shield electrode formed in the first layer is provided on the dummy island and isolation region corresponding to the region where the wiring is provided, and the first shield electrode is provided on the isolation region and and the first shield electrode are in ohmic contact, and the second shield electrode formed in the second layer is provided on both sides of the wiring formed in the same layer, and is substantially in contact with the second shield electrode. The entire surface is in ohmic contact with the first shield electrode, and the third shield electrode is in ohmic contact with the first shield electrode.
3. The semiconductor integrated circuit according to claim 2, wherein the third shield electrode formed in a layer covers the second shield electrode and the wiring and makes ohmic contact with the second shield electrode over substantially the entire surface. . (7) The shield electrode has a two-layer structure, and the first shield electrode formed in the first layer is provided on both sides of the wiring formed on the isolation region surrounding the dummy island,
A second shield electrode formed in the second layer is in ohmic contact with the separation region over substantially the entire surface of the first shield electrode.
3. The semiconductor integrated circuit according to claim 2, wherein the shield electrode covers the first shield electrode and the wiring and is in ohmic contact with the first shield electrode over substantially the entire surface. (8) Place this semiconductor chip in the center of the first
and a first divided region that substantially divides the first region into a third and fourth region; and a second divided region that substantially divides the first region into a third and fourth region; a third divided region that is substantially divided into a fifth and a sixth region; and a third divided region that is orthogonal to the first divided region and has a first power supply line and a first ground line that are adjacent to each other as a set and extend on both sides thereof. a mat formed by arranging a plurality of existing partition lines in the same direction and dividing the third to sixth regions into a plurality of regions of substantially the same size; and the third to sixth regions. a plurality of electronic circuit blocks having different functions, each of which is incorporated in an integer number of the mats; and a first ground line of the first region and a second ground line formed on the first divided region; a second ground line and a second power supply line connected to the first ground line of the second region, respectively; a second ground line and a second power supply line connected to the first ground line of the second region; a second extension electrode formed on the third divided region and connected to the first ground line of the first region; and at least one of the second and third divided regions. A semiconductor integrated circuit comprising: a wiring connecting between mats formed in parallel with the first and second extension electrodes; and a shield electrode shielding the wiring. (9) The semiconductor integrated circuit according to claim 8, wherein one or more dummy islands are provided in the first to third divided regions. (10) The shield electrode has a two-layer structure, the first shield electrode formed in the first layer is provided on both sides of the wiring, and the second shield electrode formed in the second layer is provided on both sides of the wiring. 9. The semiconductor integrated circuit according to claim 8, wherein the semiconductor integrated circuit covers the first shield electrode and the wiring and makes ohmic contact with the first shield electrode over substantially the entire surface. (11) The shield electrode has a two-layer structure, and the first shield electrode formed in the first layer is provided on both sides of the wiring, and the dummy island covers substantially the entire surface of the first shield electrode. Claim 9, wherein the second shield electrode formed in the second layer is in ohmic contact and covers the first shield electrode and the wiring, and is in ohmic contact with the first shield electrode over substantially the entire surface. The semiconductor integrated circuit described. (12) The shield electrode has a two-layer structure, and the first shield electrode formed in the first layer is provided on both sides of the wiring, and covers substantially the entire surface of the first shield electrode, and has a dummy island. A second shield electrode formed in a second layer is in ohmic contact with the surrounding isolation region, covers the first shield electrode and the wiring, and is in ohmic contact with the first shield electrode over substantially the entire surface. The semiconductor integrated circuit according to claim 9. (13) The shield electrode has a three-layer structure, and the first shield electrode formed in the first layer is provided on the dummy island and isolation region corresponding to the region where the wiring is provided, and the first shield electrode is provided on the isolation region and and the first shield electrode are in ohmic contact, and the second shield electrode formed in the second layer is in ohmic contact with the first shield electrode.
The shield electrodes are provided on both sides of the wiring formed in the same layer, and substantially cover the entire surface of the second shield electrode,
A third shield electrode formed in a third layer is in ohmic contact with the first shield electrode, covers the second shield electrode and the wiring, and is in contact with the second shield electrode over substantially the entire surface. 10. The semiconductor integrated circuit according to claim 9, wherein the semiconductor integrated circuit has ohmic contact. (14) The shield electrode has a two-layer structure, and the first shield electrode formed in the first layer is provided on both sides of the wiring formed on the isolation region surrounding the dummy island, and is substantially the first shield electrode formed in the first layer. A second shield electrode formed in a second layer, which is in ohmic contact with the separation region over the entire surface of the first shield electrode, covers the first shield electrode and the wiring, and is substantially in contact with the first shield electrode. 10. The semiconductor integrated circuit according to claim 9, wherein the semiconductor integrated circuit has ohmic contact over the entire surface.