JP2011171415A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To lower the resistance value of a power-supply wiring connecting a pad for a power supply for a semiconductor integrated circuit and a power supply line of a logic-circuit block and/or a ground wiring connecting the pad for a ground for the semiconductor integrated circuit and a ground line for the logic-circuit block in the semiconductor integrated circuit including at least the logic-circuit block. <P>SOLUTION: The semiconductor integrated circuit includes: a semiconductor substrate; and a plurality of wiring layers being formed on the semiconductor substrate through each interlayer insulating film and being connected to a plurality of transistors formed to the semiconductor substrate and configuring at least the logic-circuit block together with a plurality of the transistors. The semiconductor integrated circuit further includes the wiring layer as an uppermost layer being formed on the semiconductor substrate forming a plurality of the wiring layers through the interlayer insulting films and having a film thickness at five to twenty times as large as a maximum film thickness in a plurality of the wiring layers. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit including at least a logic circuit block including a plurality of transistors formed on a semiconductor substrate and a plurality of wiring layers formed on the semiconductor substrate via respective interlayer insulating films. .

  In a semiconductor integrated circuit, the thickness of a wiring layer used for a logic circuit block is usually about 400 nm even if it is thick, and the resistance value of the wiring cannot be ignored. Among such wirings, in power supply wiring and ground wiring, currents flowing through a large number of logic circuits are superimposed and various noises are generated, so noise interference between multiple circuits or multiple circuit blocks is a problem. It becomes. In particular, in a semiconductor integrated circuit in which a logic circuit and an analog circuit are mixedly mounted, wraparound of digital noise generated in the logic circuit into the analog circuit becomes a big problem.

  As related technologies, Patent Document 1 and Patent Document 2 disclose a functional standard including a bypass capacitor that has a small residual inductance, does not increase the area, and provides a sufficient capacity in order to eliminate power supply noise of a high frequency component. A cell and a semiconductor integrated circuit having the same are disclosed.

  The standard cell disclosed in Patent Document 1 is for wiring a semiconductor substrate on which at least one functional circuit element including input and output signal terminals is formed, and an input and output signal terminal formed above the semiconductor substrate. And a three-terminal capacitor formed above the signal wiring layer. The three-terminal capacitor includes a power supply wiring layer and a first and a second power supply layer sandwiching the power supply wiring layer via an insulating layer. The functional circuit element is supplied with power from the power wiring layer and the first ground wiring layer.

  The semiconductor integrated circuit disclosed in Patent Document 2 is a semiconductor integrated circuit including at least one standard cell or macrocell having a multilayer wiring layer, and is a signal composed of at least one layer formed above a semiconductor substrate. A wiring layer; and a three-terminal capacitor formed above the signal wiring layer. The three-terminal capacitor includes a power wiring layer and first and second ground wiring layers sandwiching the power wiring layer through an insulating layer. The functional circuit element is supplied with power from the power supply wiring layer and the first ground wiring layer.

  According to Patent Document 1 and Patent Document 2, by providing first and second ground wiring layers (electrodes) on both upper and lower sides of a power supply wiring layer (electrode) of the bypass capacitor via insulating layers, the capacitance of the bypass capacitor Can be increased. However, Patent Document 1 and Patent Document 2 do not specifically disclose the reduction of the resistance value of the power supply wiring or the ground wiring.

Japanese Patent Laying-Open No. 2003-224195 (first page, FIG. 3) Japanese Patent Laying-Open No. 2007-165922 (first page, FIG. 3)

  Therefore, in view of the above points, according to some aspects of the present invention, in a semiconductor integrated circuit including at least a logic circuit block, a power supply wiring for connecting a power supply pad of the semiconductor integrated circuit and a power supply line of the logic circuit block And / or the resistance value of the ground wiring connecting the ground pad of the semiconductor integrated circuit and the ground line of the logic circuit block can be lowered.

  In order to solve the above problems, a semiconductor integrated circuit according to one aspect of the present invention includes a semiconductor substrate and a plurality of transistors formed over the semiconductor substrate through respective interlayer insulating films. A plurality of wiring layers that are connected to form at least a logic circuit block together with a plurality of transistors, and are formed on a semiconductor substrate on which the plurality of wiring layers are formed via an interlayer insulating film. And an uppermost wiring layer having a film thickness of 5 to 20 times.

  Here, the uppermost wiring layer directly connects the power supply pad of the semiconductor integrated circuit and the power supply line of the logic circuit block, and / or connects the ground pad of the semiconductor integrated circuit and the ground line of the logic circuit block. It may be used for direct connection.

  Further, the uppermost wiring layer includes a first wiring that directly connects a power supply pad of the semiconductor integrated circuit and a power supply line of the logic circuit block, and a ground pad of the semiconductor integrated circuit and a ground line of the logic circuit block. The first wiring and the second wiring may include a comb-teeth shape that alternately enters the second wiring.

  In the above, a high-frequency circuit block may be further configured by a plurality of circuit elements formed on the semiconductor substrate, a plurality of wiring layers, and the uppermost wiring layer. In that case, an inductor may be formed in the uppermost wiring layer in the high-frequency circuit block.

  According to one aspect of the present invention, in a semiconductor integrated circuit including at least a logic circuit block composed of a plurality of transistors and a plurality of wiring layers, a film having a film thickness of 5 to 20 times the maximum film thickness of the plurality of wiring layers. Since the uppermost wiring layer having a thickness is provided, the power supply pad of the semiconductor integrated circuit and the power supply line of the logic circuit block are directly connected and / or the ground pad of the semiconductor integrated circuit and the ground of the logic circuit block By using the uppermost wiring layer to directly connect the line, the resistance value of the power supply wiring and / or the ground wiring can be lowered.

1 is a block diagram illustrating a configuration example of a semiconductor integrated circuit according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing a configuration example of a low noise amplifier shown in FIG. 1. FIG. 2 is a circuit diagram showing a configuration example of the VCO shown in FIG. 1. 1 is a plan view showing a layout of a semiconductor integrated circuit according to an embodiment of the present invention. 1 is a cross-sectional view illustrating a structure of a semiconductor integrated circuit according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same referential mark is attached | subjected to the same component and description is abbreviate | omitted.
FIG. 1 is a block diagram showing a configuration example of a semiconductor integrated circuit according to an embodiment of the present invention. This semiconductor integrated circuit (IC) is used for wireless communication in a device such as a wireless mouse that performs wireless communication.

  The semiconductor integrated circuit shown in FIG. 1 includes a high frequency (RF) circuit block 10, a low frequency (LF) circuit block 40, and a logic circuit block 50. The high frequency circuit block 10 includes a low noise amplifier (LNA) 11, a mixer 12, a modulation circuit 21, a power amplifier (PA) 22, an oscillation circuit 31, a control voltage generation circuit 32, and a voltage controlled oscillator (VCO) 33. And 34, variable frequency dividing circuits 35 and 36, and a selector (selection circuit) 37. The low frequency circuit block 40 includes a filter unit 41 and a digital / analog converter (DAC) 42. The logic circuit block 50 includes a digital demodulation circuit 51, a digital modulation circuit 52, and a control circuit 61.

  The antenna ANT may be realized as an external component of a semiconductor integrated circuit, or may be formed on-chip using W-CSP (Waferlevel Chip Size Package) technology or the like. The low noise amplifier 11 amplifies a high frequency received signal supplied from an antenna ANT that has received radio waves from outside with low noise. The mixer 12 down-converts the reception signal by multiplying the reception signal amplified by the low noise amplifier 11 and the signal (local oscillation signal) RX generated by the VCO 33.

  The filter unit 41 extracts a baseband signal while performing image removal by performing bandpass filter processing realized by a complex filter or the like on the reception signal down-converted by the mixer 12. The digital demodulation circuit 51 obtains reception data by performing digital demodulation processing on the baseband signal, and outputs the obtained reception data to the control circuit 61. For example, when FSK (frequency shift keying) is used as a digital modulation method on the transmission side, the digital demodulation circuit 51 performs FSK demodulation processing on the baseband signal.

  On the other hand, the digital modulation circuit 52 generates a modulation signal used for digitally modulating the carrier wave based on the transmission data supplied from the control circuit 61. For example, when FSK is used as the digital modulation method, the digital modulation circuit 52 generates a modulation signal for frequency-modulating the carrier wave based on the transmission data. The DAC 42 converts the digital modulation signal into an analog modulation signal.

  The modulation circuit 21 modulates the transmission carrier frequency signal (carrier wave) TX generated by the VCO 34 based on the analog modulation signal supplied from the DAC 42. Note that the modulation circuit 21 and the VCO 34 may be configured integrally. The power amplifier 22 amplifies the carrier wave modulated by the modulation circuit 21 and supplies it to the antenna ANT, whereby radio waves are transmitted from the antenna ANT to the outside.

  The oscillation circuit 31 generates a reference signal having a predetermined frequency by performing an oscillation operation using a vibrator such as a crystal vibrator. However, the crystal resonator connected to the oscillation circuit 31 is provided outside the semiconductor integrated circuit. Alternatively, the oscillation circuit 31 may be omitted and the reference signal may be supplied from the outside of the semiconductor integrated circuit.

  The control voltage generation circuit 32 includes a phase comparison circuit, a charge pump, and a loop filter, and compares the phase of the divided signal selected by the selector 37 with the phase of the reference signal supplied from the oscillation circuit 31. Then, a control voltage for controlling the oscillation frequency of the VCOs 33 and 34 is generated.

  In the reception mode, the VCO 33 generates a signal (local oscillation signal) RX used for down-converting the reception signal by performing an oscillation operation at a frequency according to the control voltage supplied from the control voltage generation circuit 32. The variable frequency dividing circuit 35 divides the signal RX generated by the VCO 33 by the frequency dividing ratio set by the control circuit 61.

  In the transmission mode, the VCO 34 generates a signal (carrier wave) TX of a carrier frequency for transmission by performing an oscillation operation at a frequency according to the control voltage supplied from the control voltage generation circuit 32. The variable frequency dividing circuit 36 divides the signal TX generated by the VCO 34 by the frequency dividing ratio set by the control circuit 61.

  Under the control of the control circuit 61, the selector 37 selects the frequency-divided signal output from the variable frequency dividing circuit 35 in the reception mode, and the frequency-divided signal output from the variable frequency dividing circuit 36 in the transmission mode. select. Thereby, in the reception mode, the VCO 33 and the variable frequency dividing circuit 35 constitute a PLL circuit together with the control voltage generating circuit 32, and in the transmission mode, the VCO 34 and the variable frequency dividing circuit 36 together with the control voltage generating circuit 32 are PLLs. Configure the circuit. The reception system circuit and the transmission system circuit may always operate, but one operation may be stopped when not necessary.

Here, the variable frequency dividing circuit 35 divides the signal RX by 1 / N _R by setting the frequency dividing ratio in the variable frequency dividing circuit 35 of the receiving system to N _R : 1. signal frequency of the signal obtained by multiplying the N _R times RX is obtained. In addition, since the variable frequency dividing circuit 36 divides the signal TX by 1 / N _T by setting the frequency dividing ratio in the variable frequency dividing circuit 36 of the transmission system to N _T : 1, in the transmission mode, the reference signal The signal TX is obtained by multiplying the frequency of N by _NT times.

  The control circuit 61 sets the frequencies of the signals TX and RX by setting the frequency dividing ratios of the variable frequency dividing circuits 35 and 36 according to the selected wireless communication channel in the transmission mode and the reception mode, respectively. The control circuit 61 performs control of the entire semiconductor integrated circuit, digital processing of received data and transmitted data, and the like. The control circuit 61 includes a link layer circuit 62, a host interface (I / F) 63, and the like, executes link layer protocol processing, and transfers data to and from an external host computer.

FIG. 2 is a circuit diagram showing a configuration example of the low noise amplifier shown in FIG. The low-noise amplifier (LNA) includes N-channel MOS transistors Q11 and Q12 that differentially amplify reception signals supplied to the antenna connection pads PANT1 and PANT2, the sources of the transistors Q11 and Q12, and a power supply potential V _SS (FIG. 2). Is connected to the ground potential), N-channel MOS transistors Q13 and Q14 cascode-connected to the drains of the transistors Q11 and Q12, respectively, the drain of the transistor Q13, and the power supply potential V an inductor L11 and capacitor C11 connected between the _DD, and the inductor L12 and capacitor C12 connected between the drain and source potential _{V DD} of the transistor Q14, a capacitor C13 and C14 for DC cut, transistor Resistors R11 and R12 for applying a bias voltage VBS to the gates of the transistors Q11 and Q12.

  The inductor L11 and the capacitor C11 that are the load of the transistor Q13 constitute a resonance circuit, and the inductor L12 and the capacitor C12 that are the load of the transistor Q14 also constitute a resonance circuit. The resonance frequency of these resonance circuits is set near the carrier frequency of the received signal. For example, when the carrier frequency of the received signal is 2.4 GHz, the resonance frequency is also set around 2.4 GHz. By providing a load by such a resonance circuit, a high-frequency received signal can be amplified with low noise. In the example shown in FIG. 2, a differential amplification type low noise amplifier is used, but a single type low noise amplifier may be used.

FIG. 3 is a circuit diagram showing a configuration example of the VCO shown in FIG. This VCO is a constant current connected between N-channel MOS transistors Q21 and Q22 constituting a differential pair, and sources of the transistors Q21 and Q22 and a power supply potential V _SS (referred to as a ground potential in FIG. 3). A source CS21, inductors L21 and L22 connected between the drains of the transistors Q21 and Q22 and the power supply potential _VDD , respectively, and varicaps connected between the control voltage input terminal and the drains of the transistors Q21 and Q22, respectively. (Varactor diode) VC21 and VC22 are included.

  The drain of the transistor Q21 is connected to the output terminal A and the gate of the transistor Q22, and the drain of the transistor Q22 is connected to the output terminal B and the gate of the transistor Q21. The VCO shown in FIG. 3 oscillates at a higher frequency as the voltage applied to the control voltage input terminal is higher, and oscillates at a lower frequency as the voltage applied to the control voltage input terminal is lower. In the example shown in FIG. 3, a differential amplification type VCO is used, but a single type VCO may be used.

Next, a layout of the semiconductor integrated circuit according to one embodiment of the present invention will be described.
FIG. 4 is a plan view showing the layout of the semiconductor integrated circuit according to the embodiment of the present invention compared with the layout of the conventional semiconductor integrated circuit. FIG. 4A shows a layout of a semiconductor integrated circuit according to an embodiment of the present invention, and FIG. 4B shows a layout of a conventional semiconductor integrated circuit. 4, in the RF (high frequency) region, the high frequency circuit block 10 shown in FIG. 1 is arranged, and in the LF (low frequency) region, the low frequency circuit block 40 shown in FIG. 1 is arranged, and the GA (gate array). ) Area, a gate array constituting the logic circuit block 50 shown in FIG. 1 is arranged.

  As shown in FIGS. 2 and 3, an inductor is used in a low noise amplifier (LNA) or a VCO of a high frequency circuit block. Therefore, as shown in FIG. 4, an inductor in the RF region (a set of inductors in FIG. 4). LA and LB are formed). In order to form an inductor in a semiconductor integrated circuit, as an RF option, the uppermost metal wiring layer having a film thickness of 5 to 20 times the maximum film thickness of the normal metal wiring layer is formed on the upper layer of the normal metal wiring layer. (Also referred to as “thick film metal wiring layer” in this application). For example, when the maximum film thickness of a normal metal wiring layer is about 400 nm, when using a thick metal wiring layer having a film thickness 10 times the maximum film thickness of a normal metal wiring layer, the film thickness Is about 4 μm.

  The thick metal wiring layer has a low sheet resistance value, and can reduce the parasitic resistance of the inductor. In addition, the distance between the inductor and the semiconductor substrate is increased compared to the case where the inductor is formed in a normal metal wiring layer, and the parasitic capacitance of the inductor can be reduced. Thus, by reducing the parasitic resistance and parasitic capacitance of the inductor, the Q value of the inductor can be increased.

  The thick metal wiring layer forms a pad (external connection terminal) to which wiring (bonding wire or the like) between the terminals formed on the IC package is connected, or a capacitor (MIM) formed between the wiring layers. : Metal insulator metal). However, according to literature surveys and chip analysis, there is no example in which a thick metal wiring layer is used to form other circuit elements. The reason is presumed as follows.

  The logic circuit block is laid out by an automatic placement and routing program. On the other hand, since a thick metal wiring layer has a larger thickness than a normal metal wiring layer, it is impossible to lay out a narrow width wiring at a narrow interval as in a normal metal wiring layer. It is not suitable for layout design by an automatic placement and routing program. Therefore, a thick metal wiring layer has not been provided on the logic circuit block.

As shown in FIG. 4B, in the conventional semiconductor integrated circuit layout, the wiring pattern of the thick metal wiring layer is not formed in the GA region. The power supply pads PD1 and PD2 formed in the thick metal wiring layer are connected to the power supply wiring formed in the normal metal wiring layer, and the logic circuit arranged in the GA region through the power supply wiring. A power supply potential V _DD is supplied to the power supply line of the block. The ground pads PS1 and PS2 formed on the thick metal wiring layer are connected to the ground wiring formed on the normal metal wiring layer, and are arranged in the GA region via the ground wiring. A ground potential _VSS is supplied to the ground line of the logic circuit block.

On the other hand, as shown in FIG. 4A, in the layout of the semiconductor integrated circuit according to the embodiment of the present invention, the wiring pattern of the thick metal wiring layer is formed in the GA region. A thick film power wiring 111 formed in the thick metal wiring layer is connected to the power supply pads PD1 and PD2 formed in the thick metal wiring layer, and the GA region is connected via the thick film power wiring 111. The power supply potential V _DD is supplied to the power supply line of the logic circuit block arranged in the circuit. Further, a thick film ground wiring 112 formed in the thick metal wiring layer is connected to the ground pads PS1 and PS2 formed in the thick film metal wiring layer. A ground potential _VSS is supplied to the ground line of the logic circuit block arranged in the GA region.

  FIG. 5 is a cross-sectional view showing the structure of a semiconductor integrated circuit according to an embodiment of the present invention. FIG. 5A shows the structure of the GA region, and FIG. 5B shows the structure of the RF region. In FIG. 5, only the uppermost thick metal wiring layer is shown, and further layers are omitted.

  As shown in FIGS. 5A and 5B, a P well 71 and an N well 72 are formed in a P-type semiconductor substrate 70 (in this embodiment, a silicon substrate). In the P well 71, a set of N-type impurity diffusion regions 73 and 74 are formed which become the source and drain of an N-channel MOS transistor. In the N well 72, a pair of P-type impurity diffusion regions 75 and 76 serving as the source and drain of the P-channel MOS transistor are formed.

  On the semiconductor substrate 70, a gate insulating film 81 (for example, a silicon oxide film) is formed in a region between the pair of N-type impurity diffusion regions 73 and 74, and further on the gate insulating film 81. A gate electrode 82 (for example, polysilicon) of the N channel MOS transistor is formed. A gate insulating film 83 (for example, a silicon oxide film) is formed in a region sandwiched between the pair of P-type impurity diffusion regions 75 and 76, and further, a P-channel MOS is formed on the gate insulating film 83. A gate electrode 84 (for example, polysilicon) of the transistor is formed.

  On the semiconductor substrate 70 on which a plurality of transistors are formed, a first interlayer insulating film 91, a first metal wiring layer ALA, a second interlayer insulating film 92, a second metal wiring layer ALB, A third interlayer insulating film 93, a third metal wiring layer ALC, a fourth interlayer insulating film 94, and a fourth metal wiring layer ALD are formed. For example, aluminum is used as the material of the metal wiring layer.

  The wiring in each wiring layer is connected to the wiring in the lower wiring layer or the impurity diffusion region in the semiconductor substrate 70 through an opening (via hole or contact hole) formed in the lower interlayer insulating film. Yes. In this way, the plurality of wiring layers ALA to ALD in the GA region are connected to the plurality of transistors formed on the semiconductor substrate 70 to constitute a logic circuit block. FIG. 5A shows the power supply line 101 and the ground line 102 of the logic circuit block formed in the fourth metal wiring layer ALD.

  In the present embodiment, the uppermost interlayer insulating film 95 and the uppermost thick metal wiring layer ALE are further formed thereon. In the uppermost thick metal wiring layer ALE, a thick film power wiring 111 for directly connecting the power pads PD1 and PD2 (see FIG. 4A) of the semiconductor integrated circuit and the power line 101 of the logic circuit block; Thick film ground wirings 112 that directly connect the ground pads PS1 and PS2 (see FIG. 4A) of the semiconductor integrated circuit and the ground line 102 of the logic circuit block are formed.

  In the GA region, since the wiring width and interval are narrow, the uppermost thick metal wiring layer ALE cannot be used for normal wiring, but it cannot be used for forming power supply wiring or ground wiring. Is possible. In the uppermost thick metal wiring layer ALE, the low-resistance thick film power supply wiring 111 and the thick film ground wiring 112 are formed, so that a large number of logic circuits operate, whereby the power supply line 101 and the ground line 102 of the logic circuit block. The noise generated in the logic circuit can be reduced to prevent malfunction of the logic circuit, and the noise circulated from the logic circuit block to the analog circuit block (high frequency circuit block and low frequency circuit block) can be reduced.

  Further, as shown in FIG. 4A, by setting the wiring pattern so that the thick film power supply wiring 111 and the thick film ground wiring 112 have a comb-like shape alternately inserted, the thick film power supply Since the wiring 111 and the thick film ground wiring 112 form a bypass capacitor, noise can be further reduced. Further, by using a low-resistance thick film wiring, the power supply pad, the ground pad and the bypass capacitor can be connected with a low resistance, so that the noise reduction effect is great.

  On the other hand, in the RF region, as shown in FIG. 5B, an inductor LA or LB shown in FIG. 4A is formed by a pattern 113 formed in a spiral shape in the uppermost thick metal wiring layer ALE. Is configured. In the RF region, a plurality of circuit elements such as varicaps and capacitors are formed in addition to transistors and inductors. The plurality of circuit elements, the plurality of wiring layers ALA to ALD, and the uppermost thick metal wiring layer ALE constitute a high frequency circuit block.

  Thus, in the present embodiment, the uppermost thick metal wiring layer ALE is effectively used in both the GA region and the RF region. Even when the present invention is implemented in a semiconductor integrated circuit having no RF region, the present invention is effective because the above-described effects can be obtained.

  DESCRIPTION OF SYMBOLS 10 High frequency circuit block, 11 Low noise amplifier (LNA), 12 Mixer, 21 Modulation circuit, 22 Power amplifier (PA), 31 Oscillation circuit, 32 Control voltage generation circuit, 33, 34 Voltage control oscillator (VCO), 35, 36 Variable Frequency divider, 37 selector, 40 low-frequency circuit block, 41 filter unit, 42 digital / analog converter (DAC), 50 logic circuit block, 51 digital demodulation circuit, 52 digital modulation circuit, 61 control circuit, 62 link layer circuit 63 Host interface (I / F), 70 Semiconductor substrate, 71 P well, 72 N well, 73, 74 N type impurity diffusion region, 75, 76 P type impurity diffusion region, 81, 83 Gate insulating film, 82, 84 Gate electrode, 9 ~ 95 Interlayer insulating film, 101 power line, ground line 102, 111 thick film power wiring, 112 thick film ground wiring, ALA to ALD normal metal wiring layer, ALE thick film metal wiring layer, Q11 to Q22 transistor, L11 to L22 Inductor, C11 to C14 capacitor, V21, V22 Varicap, CS11, CS21 Constant current source

Claims (5)

A semiconductor substrate;
A plurality of wiring layers formed on the semiconductor substrate via respective interlayer insulating films, connected to the plurality of transistors formed on the semiconductor substrate and constituting at least a logic circuit block together with the plurality of transistors;
An uppermost wiring layer formed on the semiconductor substrate on which the plurality of wiring layers are formed via an interlayer insulating film and having a film thickness of 5 to 20 times the maximum film thickness of the plurality of wiring layers;
A semiconductor integrated circuit comprising:   The uppermost wiring layer directly connects a power supply pad of the semiconductor integrated circuit and a power supply line of the logic circuit block, and / or a ground pad of the semiconductor integrated circuit and a ground line of the logic circuit block. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is used to directly connect to each other.   The uppermost wiring layer includes a first wiring that directly connects a power supply pad of the semiconductor integrated circuit and a power supply line of the logic circuit block, a ground pad of the semiconductor integrated circuit, and a ground of the logic circuit block 3. The semiconductor integrated circuit according to claim 2, further comprising a second wiring that directly connects a line, wherein the first wiring and the second wiring have a comb-teeth shape that is alternately inserted.   4. The high-frequency circuit block according to claim 1, wherein a high-frequency circuit block is further configured by the plurality of circuit elements formed on the semiconductor substrate, the plurality of wiring layers, and the uppermost wiring layer. Semiconductor integrated circuit.   The semiconductor integrated circuit according to claim 4, wherein an inductor is formed in the uppermost wiring layer in the high-frequency circuit block.

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