JP2011171956A - Semiconductor integrated circuit and electronic equipment using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To facilitate layout change for each circuit block by reducing influence of noise generated in a low-speed digital circuit, exerted on an analog circuit. <P>SOLUTION: A semiconductor integrated circuit includes: an analog circuit block (a) including first and second VCOs, first and second frequency dividing circuits for frequency-dividing signals to be generated by the first and second VCOs, a selecting circuit for selecting one of the two frequency dividing signals, and a control voltage generating circuit for generating a control voltage, based on the selected frequency dividing signal; a first digital circuit block (b) including modulating and demodulating circuits; and a second digital circuit block (c) including a control circuit. The analog circuit block is arranged along the first and second sides of a substrate. The second digital circuit block is arranged along the third and fourth sides of the substrate. The first digital circuit block is arranged between the analog circuit block and the second digital circuit block. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit or the like that is used for wireless communication in a wireless communication device such as a wireless mouse that includes a frequency synthesizer that generates a high-frequency signal, a reception circuit, and a transmission circuit and performs short-range wireless communication. Furthermore, the present invention relates to an electronic device that performs wireless communication using such a semiconductor integrated circuit.

  In recent years, a wireless communication system that performs wireless communication at a distance of several tens of meters to several centimeters with low power consumption has been developed and used in wireless communication devices such as a wireless mouse. The hardware constituting such a wireless communication system includes an analog circuit that handles high-frequency and low-frequency analog signals, a high-speed digital circuit that performs relatively high-speed digital signal processing, and a low-speed that performs relatively low-speed control operations. The use of semiconductor integrated circuits composed of digital circuits has become the mainstream.

  In an analog circuit, a reception frequency synthesizer and a transmission frequency synthesizer that generate a high-frequency signal, a reception circuit that performs a reception operation using a signal generated by the reception frequency synthesizer, and a transmission frequency synthesizer A transmission circuit that performs a transmission operation using the generated signal is provided.

  However, the conventional semiconductor integrated circuit (IC) has the following problems. Since the analog circuit and the digital circuit are formed on the same semiconductor substrate, noise generated in a low-speed digital circuit that operates asynchronously with respect to the analog circuit affects the performance of the analog circuit. In addition, when the analog circuit or the high-speed digital circuit needs to be redesigned due to a change in the frequency used for wireless communication, the layout of the entire IC needs to be redesigned. On the other hand, the layout of the entire IC needs to be redesigned if the low-speed digital circuit needs to be changed even if the analog circuit or the high-speed digital circuit does not need to be changed due to the addition of a communication protocol specification. In the case of redesigning the layout of the entire IC, the design time and the verification time for evaluation and quality assurance become longer, making it difficult to produce a product that meets market requirements. In addition, as the period from design to shipment becomes longer, the power consumption in the commercialization process increases and the load on the environment increases.

  In addition, in an analog circuit, two frequency synthesizers having different oscillation frequencies are required, which increases the size of the IC. Furthermore, by installing two frequency synthesizers, the wiring length between the receiving frequency synthesizer and the receiving circuit or the wiring length between the transmitting frequency synthesizer and the transmitting circuit is increased, so that parasitic resistance In addition, the level of the high-frequency signal is reduced and the oscillation frequency is shifted due to the parasitic capacitance, resulting in an increase in current consumption.

  As a related technique, Patent Document 1 discloses a macro cell that can maintain the signal characteristics and the like of a differential signal even when arranged in various places. This macro cell is a macro cell including an interface standard circuit that performs data transfer using a differential signal, and includes a first pad for a first signal that constitutes the differential signal and a second that constitutes the differential signal. A transmission circuit connected to the second pad for the first signal, and the transmission circuit is connected to the first transmission driver for driving the signal line connected to the first pad and the second pad A second transmission driver for driving the signal line; a first damping resistor connected to the first pad; and a second damping resistor connected to the second pad; The first and second pads are arranged in line symmetry with the first line along the first direction as the symmetry axis, where the direction from the first to the opposite third side is the first direction. The first and second damping resistors are The first transmission driver and the second transmission driver of the transmission circuit are arranged on the first direction side of the first and second pads and along the first direction. The first lines are arranged symmetrically about the axis of symmetry.

  According to Patent Document 1, by defining the relative positional relationship between the first and second transmission drivers and the first and second pads, the signal of the differential signal can be obtained even if the macrocell is arranged at various locations. Characteristics and the like can be maintained. However, Patent Document 1 does not define an appropriate layout of analog circuits, high-speed digital circuits, and low-speed digital circuits when they coexist.

  Further, in Patent Document 2, when the output signal of the voltage controlled oscillator is used as a local oscillation signal by making the frequency division ratio of the frequency divider variable, the loop gain characteristic of the frequency synthesizer differs for each different oscillation frequency. A frequency synthesizer is disclosed that can improve the problem that a difference occurs in the lock-up time characteristics and C / N characteristics, which are frequency synthesizer characteristics, reduce the mounting area, and achieve low power consumption. The frequency synthesizer divides a voltage controlled oscillator that oscillates at a frequency corresponding to an external voltage, first frequency dividing means that divides an output signal of the voltage controlled oscillator, a reference oscillator, and an output signal of the reference oscillator. Phase dividing means, phase comparing means for comparing the phase of the signal obtained from the first frequency dividing means and the signal obtained from the second frequency dividing means and outputting an error signal, and phase comparing means And a low-pass filter that integrates the output signal and supplies it to the voltage controlled oscillator as an external voltage, and is configured as follows.

  That is, a plurality of voltage-controlled oscillators and first frequency dividing means are provided corresponding to a plurality of frequency bands, respectively, and a phase comparison means and a low-pass filter are common to the plurality of frequency bands. The frequency synthesizer includes a voltage-controlled oscillator selection unit that selects any one of a plurality of voltage-controlled oscillators corresponding to the selection of the frequency band, and a plurality of first frequency dividers that correspond to the selection of the frequency band. The frequency synthesizer loop gain control is made constant so that the frequency synthesizer loop gain characteristics by the frequency dividing means selecting means, the voltage controlled oscillator, the first frequency dividing means, the phase comparator, and the low pass filter are constant. Control means for performing the selection change of the plurality of voltage controlled oscillators and the selection change of the plurality of first frequency dividing means is provided. The plurality of first frequency dividers have frequency characteristics corresponding to a plurality of frequency bands, and consume different power depending on the frequency bands.

  Further, Patent Document 3 discloses a PLL frequency synthesizer that shortens the lock-up time and suppresses an increase in circuit area. The PLL frequency synthesizer is selected by a plurality of voltage controlled oscillators that output a plurality of output signals with an oscillation frequency controlled by a control voltage, a first switch that selects and outputs the output signal, and a first switch. A frequency divider that can divide the output signal, a phase comparator that outputs a phase difference between the phase of the output signal divided by the frequency divider and the phase of the reference signal, and a phase difference A second switch for switching the output path and a plurality of voltage controlled oscillators are provided corresponding to a plurality of voltage controlled oscillators, and the phase difference of which the output path is switched by the second switch is converted into a control voltage, respectively, and the time constant can be switched. And sequentially switching the operations of the first switch, the second switch, and the frequency divider so that output signals of a plurality of low-pass filters and a plurality of frequencies are always output. After after turning the output signals of all the frequency is to be stably output, and a control circuit for switching the respective time constants of a plurality of low-pass filters.

  According to Patent Document 2, even when two voltage controlled oscillators and two frequency dividers are used to obtain two types of output signals, the phase comparison means and the low-pass filter can be shared. Further, according to Patent Document 3, a frequency divider and a phase comparator can be shared even when two low-pass filters and two voltage controlled oscillators are used to obtain two types of output signals. However, in Patent Document 2, both voltage controlled oscillator selecting means and frequency dividing means selecting means are provided. In Patent Document 3, both the first switch and the second switch are provided. As a result, the circuit area increases and the wiring length between the circuits becomes long. Further, Patent Document 2 and Patent Document 3 do not particularly disclose the circuit layout.

Japanese Patent No. 413234 (first and fourth pages, FIG. 5) Japanese Patent No. 3917592 (page 4, FIG. 1) Japanese Patent No. 4094045 (page 4, FIG. 1)

  Therefore, in view of the above points, according to some aspects of the present invention, the influence of noise generated in a low-speed digital circuit on an analog circuit is reduced, and even when the circuit is changed in accordance with a change in IC specifications. The layout can be easily changed for each circuit block, and even if two voltage controlled oscillators are mounted for reception and transmission, an increase in circuit area and an increase in wiring length between circuits can be suppressed.

  In order to solve the above problems, a semiconductor integrated circuit according to a first aspect of the present invention is a semiconductor integrated circuit used for wireless communication, and (a) performs an oscillation operation at a frequency according to a control voltage. Generated by the first voltage-controlled oscillator that generates the local oscillation signal by the first voltage-controlled oscillator, the second voltage-controlled oscillator that generates the transmission signal by performing the oscillation operation at the frequency according to the control voltage and the modulation signal, and the first voltage-controlled oscillator The first frequency dividing circuit that divides the local oscillation signal to be generated, the second frequency dividing circuit that divides the transmission signal generated by the second voltage controlled oscillator, and the first frequency dividing circuit A selection circuit that selects one of the divided signal and the divided signal divided by the second divider circuit, and the phase and / or frequency of the divided signal selected by the selection circuit and the reference signal Phase of A control voltage generation circuit that generates a control voltage by comparing the frequency and / or a reception circuit that generates a baseband signal from the reception signal using a local oscillation signal generated by the first voltage-controlled oscillator; An analog circuit block including a transmission circuit that amplifies a transmission signal generated by the voltage-controlled oscillator, (b) a demodulation circuit that obtains reception data by demodulating the baseband signal generated by the reception circuit, and transmission data And a second digital circuit block including a control circuit for controlling at least the first and second frequency divider circuits. The analog circuit block is disposed along the first side and the second side of the semiconductor substrate orthogonal to each other, and the second digital circuit block is provided. Are arranged along the third side and the fourth side of the semiconductor substrate facing the first side and the second side, respectively, and the first digital circuit block includes an analog circuit block and a second digital circuit. It is arranged between the blocks.

  A semiconductor integrated circuit according to a second aspect of the present invention is a semiconductor integrated circuit used for wireless communication, and generates a local oscillation signal by performing an oscillation operation at a frequency according to a control voltage. A voltage-controlled oscillator, a second voltage-controlled oscillator that generates a transmission signal by oscillating at a frequency according to the control voltage and the modulation signal, and a local oscillation signal generated by the first voltage-controlled oscillator A first frequency dividing circuit; a second frequency dividing circuit for frequency-dividing a transmission signal generated by the second voltage controlled oscillator; a frequency-divided signal divided by the first frequency dividing circuit; A selection circuit that selects one of the frequency-divided signals divided by the frequency-dividing circuit, and a comparison between the phase and / or frequency of the frequency-divided signal selected by the selection circuit and the phase and / or frequency of the reference signal do it A control voltage generation circuit that generates a control voltage, a reception circuit that generates a baseband signal from a reception signal using a local oscillation signal generated by a first voltage controlled oscillator, and a second voltage controlled oscillator A transmission circuit for amplifying the transmission signal, wherein the reception circuit is formed in a first region along the first side of the semiconductor substrate, and the transmission circuit is a second of the semiconductor substrate orthogonal to the first side. A second voltage controlled oscillator and a second frequency divider circuit are formed in a third region adjacent to the first region and the second region, and One voltage controlled oscillator and a first frequency divider circuit are formed in a fourth region adjacent to the first region and the third region. Here, the selection circuit and the control voltage generation circuit may be formed in a fifth region adjacent to the first region and the fourth region.

Furthermore, a semiconductor integrated circuit according to a third aspect of the present invention is a semiconductor integrated circuit used for wireless communication, and generates a local oscillation signal by performing an oscillation operation at a frequency according to a control voltage. A voltage-controlled oscillator, a second voltage-controlled oscillator that generates a transmission signal by oscillating at a frequency according to the control voltage and the modulation signal, and a local oscillation signal generated by the first voltage-controlled oscillator A first frequency dividing circuit; a second frequency dividing circuit for frequency-dividing a transmission signal generated by the second voltage controlled oscillator; a frequency-divided signal divided by the first frequency dividing circuit; A selection circuit that selects one of the frequency-divided signals divided by the frequency-dividing circuit, and a comparison between the phase and / or frequency of the frequency-divided signal selected by the selection circuit and the phase and / or frequency of the reference signal Shi A control voltage generation circuit that generates a control voltage, a reception circuit that generates a baseband signal from a reception signal using a local oscillation signal generated by a first voltage controlled oscillator, and a second voltage controlled oscillator A transmission circuit for amplifying a transmission signal, wherein the reception circuit and the transmission circuit are respectively formed in a first region and a second region along the first side of the semiconductor substrate, and a second voltage controlled oscillator, A second frequency divider circuit is formed in a third region adjacent to the second region on the opposite side of the first side, and the first voltage controlled oscillator and the first frequency divider circuit are connected to the first side. Is formed in a fourth region adjacent to the first region on the opposite side. Here, the selection circuit and the control voltage generation circuit may be formed in a fifth region located between the third region and the fourth region.
In addition, an electronic apparatus according to the present invention includes any one of the above semiconductor integrated circuits.

  According to the first to third aspects of the present invention, the control voltage generation circuit is shared for transmission and reception using one selection circuit, thereby reducing circuit elements and increasing the circuit area and the wiring length between circuits. The increase can be suppressed. Thereby, cost can be reduced.

  Furthermore, according to the first aspect of the present invention, since the first digital circuit block is arranged between the analog circuit block and the second digital circuit block, the analog circuit block, the second digital circuit block, And the influence of noise generated in the second digital circuit block on the performance of the analog circuit block can be reduced. In addition, the layout of the analog circuit block and the first digital circuit block and the layout of the second digital circuit block can be easily changed independently of each other, and the IC specification can be flexibly dealt with. . For example, the size of the second digital circuit block can be flexibly changed even when the scale of the control circuit is changed in response to a change in the specification of the wireless communication protocol.

  Further, according to the second and third aspects of the present invention, the receiving circuit, the first voltage controlled oscillator and the first frequency dividing circuit of the receiving system are arranged close to each other, and the transmitting circuit and the first of the transmitting system are arranged. By arranging the voltage-controlled oscillator 2 and the second frequency divider in close proximity, the wiring of the high-frequency signal is shortened, and the level of the high-frequency signal is reduced due to parasitic resistance and parasitic capacitance, and the oscillation frequency of the voltage-controlled oscillator is reduced. Shifting can be prevented. Thereby, it is possible to reduce the power consumption of the IC.

1 is a block diagram illustrating a configuration example of a semiconductor integrated circuit according to an embodiment of the present invention. The block diagram which shows the structural example of the frequency synthesizer shown in FIG. 1, and its peripheral circuit. FIG. 3 is a circuit diagram showing a configuration example of a VCO of the transmission system shown in FIG. 2. 1 is a plan view showing a layout of a semiconductor integrated circuit according to an embodiment of the present invention. 1 is a layout diagram of an analog circuit block in an embodiment of the present invention. The layout diagram of the analog circuit block in the modification of one Embodiment of this invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same referential mark is attached | subjected to the same component and description is abbreviate | omitted.
FIG. 1 is a block diagram showing a configuration example of a semiconductor integrated circuit according to an embodiment of the present invention. This semiconductor integrated circuit is used for performing wireless communication in electronic devices including wireless communication devices such as a wireless mouse that performs short-range wireless communication.

  The semiconductor integrated circuit shown in FIG. 1 includes an analog circuit block 1 that handles high-frequency and low-frequency analog signals, and a first digital circuit block that performs relatively high-speed digital signal processing (“high-speed”). A digital circuit block ”or“ high-speed logic circuit block ”4, and a second digital circuit block (also referred to as“ low-speed digital circuit block ”or“ low-speed logic circuit block ”) 5 that performs a relatively low-speed control operation; Consists of.

  The analog circuit block 1 includes a receiving circuit 10, a transmitting circuit 20, and a frequency synthesizer 30. The receiving circuit 10 includes a low noise amplifier (LNA) 11, a mixer 12, a frequency dividing circuit 13, a phase shift circuit 14, mixers 15a and 15b, band pass filters (BPF) 16a and 16b, and a binarization circuit. 17a and 17b. The transmission circuit 20 includes a digital / analog converter (DAC) 21, a low-pass filter (LPF) 22, and a power amplifier (PA) 22. The high-speed digital circuit block 4 includes a demodulation circuit 41 and a modulation circuit 42. The low speed digital circuit block 5 includes a control circuit 50.

  The antenna ANT may be realized as an external component of a semiconductor integrated circuit, or may be formed on-chip using W-CSP (Waferlevel Chip Size Package) technology or the like. The low noise amplifier 11 amplifies a high frequency received signal supplied from an antenna ANT that has received radio waves from outside with low noise. The mixer 12 multiplies the local oscillation signal RX generated by the frequency synthesizer 30 with the reception signal amplified by the low noise amplifier 11, thereby down-converting the reception signal into an intermediate frequency signal.

The frequency divider circuit 13 divides the local oscillation signal RX generated by the frequency synthesizer 30 to generate the local oscillation signal cosω ₀ t. Furthermore, the phase shift circuit 14, by rotating the phase of the local oscillation signal cos .omega ₀ t by 90 °, to produce a local oscillation signal sin .omega ₀ t.

The mixer 15a multiplies the local oscillation signal cosω ₀ t generated by the frequency divider circuit 13 with the intermediate frequency signal, and the BPF 16a performs band-pass filter processing on the signal output from the mixer 15a, whereby a complex baseband is obtained. An I signal representing the real component of the signal is generated.

Further, the mixer 15b multiplies the local oscillation signal sin ω ₀ t generated by the phase shift circuit 14 with the intermediate frequency signal, and the BPF 16b performs band-pass filter processing on the signal output from the mixer 15b. A Q signal representing the imaginary component of the baseband signal is generated.

  In this manner, the received signal is down-converted and quadrature-detected, and complex baseband signals (I signal and Q signal) are generated. For example, the frequency of the received signal is around 2.4 GHz, the frequency of the intermediate frequency signal is around 300 MHz, and the frequency of the baseband signal is around 1 MHz. The binarization circuits 17a and 17b generate digital I and Q signals by binarizing the analog I and Q signals, respectively.

  The demodulation circuit 41 obtains received data by performing digital demodulation processing on the digital I signal and Q signal. For example, when FSK (frequency shift keying) is used as a digital modulation method on the transmission side, the digital demodulation circuit 41 performs FSK demodulation processing on the baseband signal.

  On the other hand, the modulation circuit 42 generates a modulation signal used for digitally modulating the carrier wave based on the transmission data. For example, when FSK is used as the digital modulation method, the modulation circuit 42 generates a modulation signal for frequency-modulating the carrier wave based on the transmission data. The DAC 21 converts the digital modulation signal into an analog modulation signal, and the LPF 22 performs low-pass filter processing on the analog modulation signal.

  The frequency synthesizer 30 generates a transmission signal TX by modulating a transmission carrier frequency signal (carrier wave) based on the modulation signal supplied from the LPF 22. For example, the frequency of the transmission signal is around 2.4 GHz. The power amplifier 23 amplifies the transmission signal TX generated by the frequency synthesizer 30 and supplies the amplified signal to the antenna ANT, whereby radio waves are transmitted from the antenna ANT to the outside.

  FIG. 2 is a block diagram showing a configuration example of the frequency synthesizer and its peripheral circuits shown in FIG. As shown in FIG. 2, the frequency synthesizer 30 includes an oscillation circuit 31, a variable frequency dividing circuit 32, a phase frequency comparison circuit 33, a charge pump 34, a loop filter 35, and voltage controlled oscillators (VCO) 36a and 36b. And prescalers 37a and 37b, variable frequency dividing circuits 38a and 38b, and a selector (selection circuit) 39.

  The oscillation circuit 31 generates a first reference signal having a predetermined frequency by performing an oscillation operation using a crystal resonator. However, the crystal resonator connected to the oscillation circuit 31 is provided outside the semiconductor integrated circuit. The variable frequency dividing circuit 32 generates a second reference signal by dividing the first reference signal generated by the oscillation circuit 31 by the frequency dividing ratio set by the control circuit 50. Alternatively, the oscillation circuit 31 or the variable frequency dividing circuit 32 may be omitted, and the first or second reference signal may be supplied from the outside of the semiconductor integrated circuit.

  The phase frequency comparison circuit 33 compares the phase and frequency of the divided signal selected by the selector 39 with the phase and frequency of the second reference signal, and outputs an error signal corresponding to the difference between them. Alternatively, the phase frequency comparison circuit 33 may compare the phase of the divided signal selected by the selector 39 with the phase of the second reference signal. The charge pump 34 supplies current to the loop filter 35 based on the error signal output from the phase frequency comparison circuit 33. The loop filter 35 has a low-pass characteristic, and generates a control voltage for controlling the VCOs 36a and 36b by converting the current supplied from the charge pump 34 into a voltage.

  The VCO 36a generates a local oscillation signal RX by performing an oscillation operation at a frequency according to the control voltage supplied from the loop filter 35. The prescaler 37a divides the local oscillation signal RX generated by the VCO 36a by a predetermined division ratio, thereby generating a signal having a frequency that can be divided by the variable frequency dividing circuit 38a. The variable frequency dividing circuit 38 a divides the signal divided by the prescaler 37 a by the frequency dividing ratio set by the control circuit 50, thereby generating a frequency divided signal having a frequency of about 500 kHz, for example. Here, the prescaler 37a and the variable frequency dividing circuit 38a constitute a first frequency dividing circuit.

  Further, the VCO 36b generates a transmission signal TX by performing an oscillation operation at a frequency according to the control voltage supplied from the loop filter 35 and the modulation signal supplied from the LPF 22. The prescaler 37b divides the transmission signal TX generated by the VCO 36b by a predetermined frequency division ratio to generate a signal having a frequency that can be divided by the variable frequency dividing circuit 38b. The variable frequency dividing circuit 38b divides the signal divided by the prescaler 37b by the frequency dividing ratio set by the control circuit 50, thereby generating a frequency divided signal having a frequency of about 500 kHz, for example. Here, the prescaler 37b and the variable frequency dividing circuit 38b constitute a second frequency dividing circuit.

  As the selector 39, under the control of the control circuit 50, a switch circuit that selects one of the divided signal output from the variable frequency dividing circuit 38a and the divided signal output from the variable frequency dividing circuit 38b, Alternatively, an OR (logical sum) circuit for obtaining a logical sum of the frequency-divided signal output from the variable frequency divider circuit 38a and the frequency-divided signal output from the variable frequency divider circuit 38b is used.

  The control circuit 50 includes a first enable signal that controls at least the operation of the variable frequency dividing circuit 38a in the reception system circuit, and a second control signal that controls at least the operation of the variable frequency dividing circuit 38b in the transmission system circuit. The enable signal is generated. When the first or second enable signal is deactivated and the variable frequency dividing circuit 38a or 38b is not operating, the output thereof is at a low level.

  When an OR circuit is used as the selector 39, the control circuit 50 activates the first enable signal and deactivates the second enable signal, whereby the divided signal output from the variable frequency dividing circuit 38a. Is selected, and the control circuit 50 deactivates the first enable signal and activates the second enable signal, whereby the frequency-divided signal output from the variable frequency-dividing circuit 38b is selected.

  In this way, the selector 39 selects the frequency-divided signal output from the variable frequency divider circuit 38a in the reception mode, and selects the frequency-divided signal output from the variable frequency divider circuit 38b in the transmission mode. Thus, in the reception mode, the VCO 36a to the variable frequency dividing circuit 38a constitute a PLL circuit together with the phase frequency comparison circuit 33 to the loop filter 35, and in the transmission mode, the VCO 36b to the variable frequency dividing circuit 38b A PLL circuit is configured together with the circuit 33 to the loop filter 35.

  Here, the phase frequency comparison circuit 33 to the loop filter 35 compare the phase and / or frequency of the frequency-divided signal selected by the selector 39 with the phase and / or frequency of the second reference signal, and the VCOs 36a and 36b. This corresponds to a control voltage generation circuit that generates a control voltage for controlling the oscillation frequency of the. According to the present embodiment, by sharing the control voltage generation circuit for transmission and reception using one selector 39, it is possible to reduce circuit elements and suppress an increase in circuit area and an increase in wiring length between circuits. .

In the frequency synthesizer 30, by setting the frequency dividing ratio in the first frequency dividing circuit of the receiving system to N _R : 1, the first frequency dividing circuit divides the signal RX by 1 / N _R. in mode, the signal RX obtained by multiplying the frequency of the second reference signal to the N _R times is obtained. In addition, since the second frequency divider circuit divides the signal TX by 1 / N _T by setting the frequency division ratio in the second frequency divider circuit of the transmission system to N _T : 1, in the transmission mode, A signal TX obtained by multiplying the frequency of the second reference signal by _NT times is obtained.

  The control circuit 50 sets the frequencies of the signals RX and TX by setting the frequency dividing ratios of the variable frequency dividing circuits 32, 38a, and 38b according to the selected wireless communication channel in the reception mode and the transmission mode, respectively. The control circuit 50 is connected to an external host computer and controls the entire semiconductor integrated circuit.

FIG. 3 is a circuit diagram showing a configuration example of the transmission-system VCO shown in FIG. The transmission-system VCO 36b includes P-channel MOS transistors QP1 and QP2 having sources connected to the power supply potential V _DD , inductors L1 and L2 connected between the drain of the transistor QP1 and the drain of the transistor QP2, and a control voltage. Varicaps VC1 and VC2 respectively connected between the input terminal and the drains of the transistors QP1 and QP2, and varicaps VC3 and VC4 respectively connected between the modulation signal input terminal and the drains of the transistors QP1 and QP2. connected between N-channel MOS transistors QN1 and QN2 have a drain connected to the drain of the transistors QP1 and QP2, the source and the power supply potential _{V SS} of the transistors QN1 and QN2 (the ground potential in FIG. 3) And a constant current source CS which.

  The drain of the transistor QP1 is connected to the gate of the transistor QP2, and the drain of the transistor QP2 is connected to the output terminal and the gate of the transistor QP1. The drain of the transistor QN1 is connected to the gate of the transistor QN2, and the drain of the transistor QN2 is connected to the output terminal and the gate of the transistor QN1. Here, the inductors L1 and L2 and the varicaps VC1 and VC2 constitute an oscillation frequency setting unit, and the varicaps VC3 and VC4 constitute a modulation frequency setting unit. The inductors L1 and L2 may be formed as one inductor.

  The VCO 36b shown in FIG. 3 oscillates at a higher frequency as the voltage applied to the control voltage input terminal is higher, and oscillates at a lower frequency as the voltage applied to the control voltage input terminal is lower. The VCO 36b changes the oscillation phase or frequency according to the modulation signal supplied to the modulation signal input terminal. In the example shown in FIG. 3, a differential amplification type VCO is used, but a single type VCO may be used. Further, the receiving-system VCO 36a shown in FIG. 1 can be configured by removing the varicaps VC3 and VC4 from the VCO 36b shown in FIG.

Next, a layout of the semiconductor integrated circuit according to one embodiment of the present invention will be described.
FIG. 4 is a plan view showing a layout of the semiconductor integrated circuit according to the embodiment of the present invention. As shown in FIG. 4, a semiconductor substrate 100 on which a semiconductor integrated circuit is formed has a square or rectangular shape having a first side 101 to a fourth side 104. Pads (external connection terminals) to which wiring (bonding wires or the like) to and from terminals formed on the IC package are connected are formed in the peripheral portion of the semiconductor substrate 100. For example, in the common area of the semiconductor substrate 100, the power supply pad PVDD power supply potential _{V DD} is supplied from the outside, and the ground pads PVSS to ground potential _{V SS} is supplied is formed from the outside. The analog circuit block 1 has antenna pads PANT1 and PANT2 to which an antenna is connected.

  In the present embodiment, a plurality of circuits formed in the semiconductor integrated circuit are divided into three blocks of an analog circuit block 1, a high-speed digital circuit block 4, and a low-speed digital circuit block 5. The analog circuit block 1 is disposed along a first side 101 and a second side 102 that are orthogonal to each other. The low-speed digital circuit block 5 is disposed along a third side 103 and a fourth side 104 that face the first side 101 and the second side 102, respectively. The high-speed digital circuit block 4 is disposed between the analog circuit block 1 and the low-speed digital circuit block 5.

  Thus, by disposing the high-speed digital circuit block 4 between the analog circuit block 1 and the low-speed digital circuit block 5, the interval between the analog circuit block 1 and the low-speed digital circuit block 5 can be increased. The influence of noise generated in the low-speed digital circuit block 5 operating asynchronously with the analog circuit block 1 on the performance of the analog circuit block 1 can be reduced.

  Furthermore, the analog circuit block 1 and the high-speed digital circuit block 4 constitute an intellectual property (IP) macro cell. Here, IP refers to a group of circuits for realizing a predetermined function. In the present embodiment, since the wireless communication function is realized by the analog circuit block 1 and the high-speed digital circuit block 4, the IP constituted by these blocks is referred to as “wireless communication IP”.

  Thereby, even when the redesign of the radio communication IP is required due to a change in the carrier frequency or the like, only the layout of the radio communication IP can be changed and used without changing the layout of the low-speed digital circuit block 5. On the other hand, if it is necessary to change the low-speed digital circuit block 5 even if it is not necessary to change the wireless communication IP due to a change in the specification of the wireless communication protocol, only the low-speed digital circuit block 5 is changed. It can be used as it is without changing the layout.

  FIG. 5 is a plan view showing the layout of the analog circuit block of the semiconductor integrated circuit according to one embodiment of the present invention. As shown in FIG. 5, a semiconductor substrate 100 on which a semiconductor integrated circuit is formed has a square or rectangular shape having four sides including a first side 101 and a second side 102. In the peripheral portion of the semiconductor substrate 100, antenna pads PANT1 and PANT2 to which an antenna is connected are formed.

  In the frequency synthesizer 30 (see FIG. 2), the inductor and varicap (VC) of the receiving VCO 36a, the prescaler (PS) 37a, and the variable frequency dividing circuit (DIV) 38a constitute the first high frequency block 110. The inductor and varicap (VC) of the transmission VCO 36b, the prescaler (PS) 37b, and the variable frequency dividing circuit (DIV) 38b constitute the second high-frequency block 120 and are used in transmission / reception. S) 39, a phase frequency comparison circuit (PFD) 33, a charge pump (CP) 34, and a loop filter (LF) constitute a low frequency block 130.

  In the layout of the semiconductor integrated circuit according to the present embodiment, the receiving circuit 10 is formed in a first region along the first side 101 of the semiconductor substrate 100, and the transmission circuit 20 is orthogonal to the first side 101. Formed in the second region along the second side 102. The second high frequency block 120 is formed in a third region adjacent to the first region and the second region, and the first high frequency block 110 is formed in the first region and the third region. It is formed in an adjacent fourth region. Further, the low frequency block 130 is formed in a fifth region adjacent to the first region and the fourth region.

  According to this embodiment, the receiving circuit 10 and the first high-frequency block 110 of the receiving system are arranged close to each other, and the transmitting circuit 20 and the second high-frequency block 120 of the transmitting system are arranged close to each other. By shortening the wiring of the high frequency signal, it is possible to prevent a decrease in the level of the high frequency signal due to the parasitic resistance and the parasitic capacitance and a shift of the oscillation frequency in the VCO.

  Further, since the frequency-divided signals divided by the variable frequency dividing circuits 38a and 38b have lower frequencies than the signals RX and TX generated by the VCOs 36a and 36b, the frequency-divided signals are supplied to the selector 39. Even if the wiring is somewhat longer, the influence on other circuits can be reduced.

  Further, the layout is determined for each of the reception circuit 10, the transmission circuit 20, the first high-frequency block 110, the second high-frequency block 120, and the low-frequency block 130, and the overall arrangement is determined by combining the layouts of these blocks. By doing so, it is possible to change the design without changing the layout greatly even when the specification of the IC is changed, and the performance is stable.

  FIG. 6 is a plan view showing a layout of an analog circuit block of a semiconductor integrated circuit according to a modification of the embodiment of the present invention. As illustrated in FIG. 6, the semiconductor substrate 100 on which the semiconductor integrated circuit is formed has a square or rectangular shape having four sides including a first side 101 and a second side 102. In the peripheral portion of the semiconductor substrate 100, antenna pads PANT1 and PANT2 to which an antenna is connected are formed.

  In the frequency synthesizer 30 (see FIG. 2), the inductor and varicap (VC) of the receiving VCO 36a, the prescaler (PS) 37a, and the variable frequency dividing circuit (DIV) 38a constitute the first high frequency block 110. The inductor and varicap (VC) of the transmission VCO 36b, the prescaler (PS) 37b, and the variable frequency dividing circuit (DIV) 38b constitute the second high-frequency block 120 and are used in transmission / reception. S) 39, a phase frequency comparison circuit (PFD) 33, a charge pump (CP) 34, and a loop filter (LF) constitute a low frequency block 130.

  In the layout of the semiconductor integrated circuit according to the modified example of the present embodiment, the reception circuit 10 and the transmission circuit 20 are formed in the first region and the second region along the first side 101 of the semiconductor substrate 100, respectively. ing. In addition, the second high frequency block 120 is formed in a third region adjacent to the second region on the opposite side of the first side 101, and the first high frequency block 110 is on the opposite side of the first side 101. In the fourth region adjacent to the first region. Further, the low frequency block 130 is formed in a fifth region located between the third region and the fourth region. The same effect as the layout shown in FIG. 5 can be obtained by the layout shown in FIG.

  1 analog circuit block, 4 high-speed digital circuit block, 5 low-speed digital circuit block, 10 receiving circuit, 11 low noise amplifier (LNA), 12, 15a, 15b mixer, 13 frequency divider circuit, 14 phase shift circuit, 16a, 16b band pass Filter (BPF), 17a, 17b Binary circuit, 20 Transmitter circuit, 21 Digital / analog converter (DAC), 22 Low-pass filter (LPF), 23 Power amplifier (PA), 30 Frequency synthesizer, 31 Oscillator circuit, 32 Variable frequency divider circuit, 33 phase frequency comparison circuit, 34 charge pump, 35 loop filter, 36a, 36b voltage controlled oscillator (VCO), 37a, 37b prescaler, 38a, 38b variable frequency divider circuit, 39 selector 41, demodulator circuit, 42 modulation circuit, 50 control circuit, 100 semiconductor substrate, 101 first side, 102 second side, 103 third side, 104 fourth side, 110 first high frequency block, 120 2nd high frequency block, 130 low frequency block, QP1, QP2 P channel MOS transistor, QN1, QN2 N channel MOS transistor, L1, L2 inductor, VC1 to VC4 varicap, CS constant current source, PVDD power supply pad, PVSS ground Pads, PANT1, PANT2 antenna pads

Claims (6)

A semiconductor integrated circuit used for wireless communication,
A first voltage controlled oscillator that generates a local oscillation signal by performing an oscillation operation at a frequency according to a control voltage, and a second voltage controlled oscillator that generates a transmission signal by performing an oscillation operation at a frequency according to the control voltage and the modulation signal A first frequency dividing circuit for frequency-dividing the local oscillation signal generated by the first voltage-controlled oscillator, and a second frequency-dividing for the transmission signal generated by the second voltage-controlled oscillator A circuit, a selection circuit that selects one of the frequency-divided signal divided by the first frequency-dividing circuit and the frequency-divided signal divided by the second frequency-dividing circuit, and the selection circuit A control voltage generating circuit for generating a control voltage by comparing the phase and / or frequency of the selected divided signal with the phase and / or frequency of the reference signal, and a station generated by the first voltage controlled oscillator A receiving circuit for generating a baseband signal from the received signal using an oscillation signal, and an analog circuit block and a transmitting circuit for amplifying a transmission signal generated by said second voltage controlled oscillator,
A first digital circuit block including a demodulation circuit that obtains reception data by demodulating the baseband signal generated by the reception circuit; and a modulation circuit that generates a modulation signal based on the transmission data;
A second digital circuit block including a control circuit for controlling at least the first and second frequency dividers;
The analog circuit block is disposed along a first side and a second side of the semiconductor substrate orthogonal to each other, and the second digital circuit block includes the first side and the second side. The first digital circuit block is disposed between the analog circuit block and the second digital circuit block. The third digital circuit block is disposed along the third side and the fourth side of the semiconductor substrate. A semiconductor integrated circuit. A semiconductor integrated circuit used for wireless communication,
A first voltage controlled oscillator that generates a local oscillation signal by performing an oscillation operation at a frequency according to the control voltage;
A second voltage controlled oscillator that generates a transmission signal by oscillating at a frequency according to the control voltage and the modulation signal;
A first frequency divider that divides the local oscillation signal generated by the first voltage controlled oscillator;
A second frequency divider that divides the transmission signal generated by the second voltage controlled oscillator;
A selection circuit that selects one of the divided signal divided by the first divider circuit and the divided signal divided by the second divider circuit;
A control voltage generation circuit that generates a control voltage by comparing the phase and / or frequency of the divided signal selected by the selection circuit with the phase and / or frequency of the reference signal;
A receiving circuit that generates a baseband signal from a received signal using a local oscillation signal generated by the first voltage-controlled oscillator;
A transmission circuit for amplifying a transmission signal generated by the second voltage controlled oscillator;
Comprising
The reception circuit is formed in a first region along a first side of the semiconductor substrate, and the transmission circuit is a second region along a second side of the semiconductor substrate orthogonal to the first side. The second voltage controlled oscillator and the second frequency divider circuit are formed in a third region adjacent to the first region and the second region, and the first voltage controlled oscillator is formed. A semiconductor integrated circuit, wherein the oscillator and the first frequency divider circuit are formed in a fourth region adjacent to the first region and the third region.   The semiconductor integrated circuit according to claim 2, wherein the selection circuit and the control voltage generation circuit are formed in a fifth region adjacent to the first region and the fourth region. A semiconductor integrated circuit used for wireless communication,
A first voltage controlled oscillator that generates a local oscillation signal by performing an oscillation operation at a frequency according to the control voltage;
A second voltage controlled oscillator that generates a transmission signal by oscillating at a frequency according to the control voltage and the modulation signal;
A first frequency divider that divides the local oscillation signal generated by the first voltage controlled oscillator;
A second frequency divider that divides the transmission signal generated by the second voltage controlled oscillator;
A selection circuit that selects one of the divided signal divided by the first divider circuit and the divided signal divided by the second divider circuit;
A control voltage generation circuit that generates a control voltage by comparing the phase and / or frequency of the divided signal selected by the selection circuit with the phase and / or frequency of the reference signal;
A receiving circuit that generates a baseband signal from a received signal using a local oscillation signal generated by the first voltage-controlled oscillator;
A transmission circuit for amplifying a transmission signal generated by the second voltage controlled oscillator;
Comprising
The receiving circuit and the transmitting circuit are respectively formed in a first region and a second region along a first side of a semiconductor substrate, and the second voltage controlled oscillator and the second frequency divider circuit are: Formed in a third region adjacent to the second region on the opposite side of the first side, wherein the first voltage controlled oscillator and the first frequency divider circuit are opposite to the first side. A semiconductor integrated circuit formed in a fourth region adjacent to the first region.   The semiconductor integrated circuit according to claim 4, wherein the selection circuit and the control voltage generation circuit are formed in a fifth region located between the third region and the fourth region.   An electronic device comprising the semiconductor integrated circuit according to claim 1.

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