JPH10116913A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce an area occupied only by a wiring film constituting data buses, and the charging and discharging currents of the buses, by connecting the data buses and a logic circuit with data buses in between which extend in such a direction that the latter data buses and the former data buses will intersect with each other above a memory and are composed of a wiring film different from that of the former data buses. SOLUTION: Data buses 90 , 91 , ..., 931 in a memory and a logic circuit 1 are connected with each other through data buses 30 , 31 , ..., 331 that extend in such a direction that the data buses 30 , 31 , ..., 331 will be crossed with the data buses 90 , 91 , ..., 931 above the memory 2 and are composed of a wiring film different from that of the data buses 90 , 91 , ..., 931 . Therefore, it is possible to run the data buses 30 , 31 , ..., 331 that connect the logic circuit 1 with the memory 2, on the memory 2 and thus reduce the area occupied only by the data buses almost to zero. By running the data buses 90 , 91 , ..., 931 on the memory, it is possible to shorten the data buses 90 , 91 , ..., 931 and reduce the charging and discharging currents of the buses.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a logic circuit and a plurality of memories having a plurality of input data buses, output data buses, or input / output common data buses.

[0002]

2. Description of the Related Art In recent years, three-dimensional graphics technology has been actively used in personal computers, game machines, and the like. In the three-dimensional graphics technology, it is necessary to perform high-speed data transfer between a memory and a graphics processor, and its bandwidth is an important factor that determines rendering performance. Therefore, it is necessary to increase the bandwidth in order to enhance the drawing performance, and various methods have been proposed for that purpose, but the highest bandwidth can be achieved only when the memory and the graphic processor are made of the same semiconductor. This is a method of arranging them on a chip and connecting them with a large number of data buses. For example, 1024
By operating a memory having a data bus of 100 bits at 100 MHz, a bandwidth of 12.8 GB / S can be realized.

FIG. 2 shows a schematic configuration of one memory. In the figure, 4 is an array, 5 is a Y decoder, 6 is an X decoder, 7 is a sense amplifier, and 8 is an input / output buffer. FIG. 3 shows a conventional example of a semiconductor integrated circuit device having a memory, a plurality of (32) 32-bit memories, and a graphic processor (logic circuit), and connecting them with a 32-bit data bus. FIG. 4 shows another conventional example. In the conventional example shown in FIG. 4, four memories are arranged in two vertical columns (hence, eight memories), and a graphic processor divided into eight is arranged outside the four memories.

[0004]

According to the semiconductor integrated circuit device as shown in FIG. 3, since the data bus occupies its own area, the area ratio of the wiring in the semiconductor integrated circuit device increases. There is a problem. Also,
4, the area occupied by the data bus can be reduced, but the degree of freedom regarding the arrangement of the memory and the graphic processor is restricted, and for example, it is necessary to divide the graphic processor. Then, it is good if the graphic processor is allowed to be divided, but sometimes it is not allowed. In that case, the semiconductor integrated circuit device as shown in FIG. 4 cannot be manufactured.

The present invention has been made to solve such a problem, and has a semiconductor device having a logic circuit and a plurality of memories having a plurality of input data buses, output data buses, or input / output common data buses. In an integrated circuit device,
The area occupied only by the wiring film constituting the data bus is reduced or substantially eliminated without restricting the degree of freedom in designing the layout of the memory and the logic, and the wiring length of the data bus is shortened to reduce the charge / discharge current of the bus. The purpose is to:

[0006]

According to a first aspect of the present invention, a data bus in a memory is formed in a direction in which a bit line extends, and the data bus and the logic circuit are arranged above the data bus and the memory. It extends in the direction intersecting and is connected via a data bus made of a wiring film different from the data bus.

Therefore, according to the semiconductor integrated circuit device of the first aspect, the data bus in the memory and the logic circuit extend in a direction intersecting the data bus and above the memory, and have a different wiring film from the data bus. , The data bus connecting the logic circuit and the memory can pass over the memory, and therefore, it is not prevented that only the data bus occupies the area. Can be reduced.

By passing the data bus over the memory, the bus length can be shortened, so that the charge / discharge current of the bus can be reduced, and the wasteful power consumption can be reduced.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

FIGS. 1A and 1B show a first embodiment of a semiconductor integrated circuit device according to the present invention, wherein FIG. 1A is a plan view showing a schematic configuration, and FIG. It is the enlarged plan view which paid attention. In the drawing, 1 is a graphic processor (logic circuit), 2, 2,.
_0, 3 _1, ... 3 ₃₁ a 32-bit data bus from the 0th bit to the 31st bit, connects the memory 2 and the graphics processor 1.

4 is an array of the memory 2, 5 is a Y decoder,
6 is an X decoder, 7 is a sense amplifier, and 8 is an input / output buffer. Although the sectional structure of the memory 2 is not shown,
The word line (X selection line) is constituted by a gate electrode made of polysilicon, and the first-layer aluminum wiring film (1Al) is used as a shunt wiring for it.
Then, the bit line is formed of a second-layer aluminum wiring (2A
1).

[0012] 9 _0, 9 _1, ... 9 ₃₁ is a 32-bit data bus from the 0th bit to the 31st bit, each bit and the data bus 3 ₀ of the output buffer 8, 3 _1,
Used to connect between the ... 3 _31, for example, is constituted by a third layer of aluminum interconnection film (3Al), extends in the bit line direction. Then, the data bus 3 ₀ connected to the logic circuit 1, 3 _1, intersects with ... 3 ₃₁ are connected by the through hole. The data bus 3
_0, 3 _1, ... 3 ₃₁ is constituted by, for example, fourth-layer aluminum wiring film (4Al).

In the present embodiment, the data buses 3 ₀ , 3 ₁ ,... 3 ₃₁ connected to the graphic processor 1, which is a logic circuit, are connected to the graphic processor 1.
The memory connected to the memory 2 closer to the memory 2 and the memory connected to the memory 2 farther are formed by the same layer of the wiring film (4Al), and the formation positions (extending positions) are different. However, wiring films of different layers [for example, a fifth wiring film (5Al) and a sixth wiring film (6A)]
1)]. In particular, when the number of bits is large (for example, 64 bits or 128 bits), it is difficult to form in the same layer, so that it must be formed in another layer. Whatever form it takes,
According to the present invention, the number of wiring layers for the memory 3 is increased. However, originally, the circuit in the graphic processor 1 is extremely complicated, and the number of wiring layers is larger than that of a normal memory. Since there are a number of layers, the wiring films of the upper layer of the processor 1 are connected to the data buses 3 ₀ , 3 ₁ ,.
If it is also used to form 3 ₃₁ , 9 ₀ , 9 ₁ ,... 9 ₃₁ , the number of wiring film formation layers does not increase particularly for the implementation of the present invention. In order to increase the number of wiring films to be formed in order to form a data bus, which wiring film is to be a lower layer is determined by whether the formation density is high or low. It is preferable that the lower the wiring film, the higher the layer. This is to increase the flatness of the surface of the semiconductor integrated circuit device as much as possible.

According to such a semiconductor integrated circuit device,
Memory data bus 9 _0, 9 _1, and ... 9 ₃₁ and the logic circuit 1, extends in a direction crossing with the data bus 9 _0, 9 _1, ... 9 ₃₁ and the memory 2 above, the data Bus 9
_0, 9 _1, the data bus 3 ₀ consisting of another wiring film and ... 9 _31, 3 _1, since connected via a ... 3 _31,
Data bus 3 connecting logic circuit 1 and memory 2
_0, 3 _1, ... 3 ₃₁ can be made to pass over the memory 2, and by extension the data bus 3 _0, 3 _1, ... 3 ₃₁
Only occupying the area can be made almost zero. The data buses 9 ₀ , 9 ₁ ,... 9 ₃₁ can be shortened by passing them on the memory 2, and the charge / discharge current of the bus can be reduced, thereby reducing wasteful power consumption. can do.

In the above embodiment, the present invention is applied to a semiconductor integrated circuit device in which the data bus is an input / output common data bus. However, the data bus has an input data bus and an output data bus separately. The present invention can also be applied to a device having only an output data bus.

[0016]

According to the semiconductor integrated circuit device of the first aspect, the data bus in the memory and the logic circuit extend in a direction crossing the data bus and above the memory, and have a different wiring film from the data bus. , The data bus connecting the logic circuit and the memory can pass over the memory, and therefore, it is not prevented that only the data bus occupies the area. Can be reduced. Then, the data bus can be shortened by passing the data bus through the memory, and the charge / discharge current of the bus can be reduced, and wasteful power consumption can be reduced.

[Brief description of the drawings]

1A and 1B show a first embodiment of a semiconductor integrated circuit device of the present invention, wherein FIG. 1A is a plan view showing a schematic configuration, and FIG. 1B is an enlarged view of one memory; It is a top view.

FIG. 2 is a plan view showing a schematic configuration of a memory.

FIG. 3 is a plan view showing a schematic configuration of one conventional example of a semiconductor integrated circuit device.

FIG. 4 is a plan view showing a schematic configuration of another conventional example of a semiconductor integrated circuit device.

[Explanation of symbols]

1 ... Logic circuit (graphic processor), 3
₀ , 3 ₁ ,... 3 ₃₁ ... Data bus connected to the logic circuit, 2... Memory, 4.
-I / O buffers, 9 ₀ , 9 ₁ , ... 9 ₃₁ ... data bus in the memory.

────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] August 5, 1997

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0003

[Correction method] Change

[Correction contents]

FIG. 2 shows a schematic configuration of one memory. In the figure, 4 is an array, 5 is a Y decoder, 6 is an X decoder, 7 is a sense amplifier, and 8 is an input / output buffer. FIG. 3 shows a memory and a plurality of (eight) 32-bit memories 4 ₁ ,
4 _2, and a ... 4 ₈ and the graphic processor (logic circuit) 10, which is one conventional example of a semiconductor integrated circuit device connected between them in 32-bit data bus.
FIG. 4 shows another conventional example. In the conventional example shown in FIG. 4, four memories are arranged in two vertical columns (therefore, memory 8
), And a graphic processor divided into eight parts is arranged outside of this.

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0004

[Correction method] Change

[Correction contents]

[0004]

According to the semiconductor integrated circuit device as shown in FIG. 3, since the data bus occupies its own area, the area ratio of the wiring in the semiconductor integrated circuit device increases. There is a problem. Also,
If, as shown in FIG. 4, although the area in which the data bus is occupied can be reduced, the memory 4 _{1, 4} 2, ... _{4 8} and the graphic processor 10 _{1, 10} 2, free with respect to the arrangement of the ... 10 ₈ The degree is limited, for example, it is necessary to divide the graphic processor. Then, it is good if the graphic processor is allowed to be divided, but sometimes it is not allowed. In that case, the semiconductor integrated circuit device as shown in FIG. 4 cannot be manufactured.

[Procedure amendment 3]

[Document name to be amended] Drawing

[Correction target item name] Figure 3

[Correction method] Change

[Correction contents]

FIG. 3

[Procedure amendment 4]

[Document name to be amended] Drawing

[Correction target item name] Fig. 4

[Correction method] Change

[Correction contents]

FIG. 4

──────────────────────────────────────────────────の Continued on front page (51) Int.Cl. ⁶ Identification code FI H01L 21/822 H01L 27/04 D

Claims (2)

[Claims] 1. A semiconductor integrated circuit device having a logic circuit and a plurality of memories having a plurality of input data buses, output data buses, or input / output common data buses, wherein a data bus in the memory extends in a direction in which a bit line extends. Wherein the data bus and the logic circuit extend in a direction intersecting the data bus and are connected via a data bus made of a different wiring film from the data bus. Circuit device 2. The data bus according to claim 1, wherein the data bus in the memory and the data bus connected to the logic circuit are formed by a lower wiring film when the wiring density is higher than when the wiring density is lower. Semiconductor integrated circuit device