JP2003224225A - Semiconductor device and semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a high speed semiconductor device including an SDRAM. <P>SOLUTION: A chip 10 of a SDRAM is divided into a plurality of subchip regions 11 and a package wiring 22 formed in a package substrate is employed for interconnecting respective subchip regions 11 and for interconnecting each subchip region 11 with an external electrode 21. The package wiring 22 is thicker than the ordinary wiring 15 in the chip and has a smaller signal delay. Since the speed is increased in the subchip region 11, high speed of the SDRAM is realized as a whole even if the delay is increased at the package wiring 22 part. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a semiconductor memory device, and more particularly to a semiconductor device and a semiconductor memory device suitable for application to a DRAM or the like.

[0002]

2. Description of the Related Art In semiconductor memory devices such as DRAMs, their storage capacities are continuously expanding, and in recent years, 256
DRAM with Mbit capacity has appeared. 256Mbit D
Some RAMs have, for example, an input / output bit width of x32. In this specification, such 256 Mbit
256 DRAM with capacity and input / output bit width of x32
It is abbreviated as M or x32 DRAM. The data input / output line, the data input / output pin, and the data input / output terminal for inputting / outputting the stored contents of the memory cell are referred to as an I / O line, an I / O pin, and an I / O terminal, respectively.

FIG. 16 shows a conventional 256M, x32 DR.
FIG. 6 is a plan view schematically showing the arrangement of input / output terminals in the AM chip. The DRAM chip 10 has 32 I / O
Pin and signal pin 1 including a certain number of address pins (ADD), clock pins (CLK), and multiple control pins (CTL)
6 is arranged. 32 I / O pins are I / O0-I
/ O7, I / O8 to I / O15, I / O16 to I / O2
3 and I / Os 24 to 31 are arranged in four places. The number of pins is reduced in the drawing.

FIG. 17 is a schematic plan view showing a package 20 in which the DRAM chip 10 is mounted on a package substrate. Each signal pin 16 including the I / O pin of the DRAM chip 10 is bonded to the corresponding internal electrode of the package substrate. These internal electrodes are BG
There is a one-to-one correspondence with the external electrodes (bumps) 21 arranged as A, and each internal electrode and the corresponding external electrode 21 are connected by a wiring pattern 22 inside the package substrate.

Generally, in accessing a memory cell, an address signal is input from an address pin ADD, and a specific memory cell is designated by the address signal transmitted by an address bus. The data of the designated memory cell is transmitted to the outside via the I / O bus and the I / O pin, or is transmitted from the outside to perform reading or writing.

The length of the signal transmission path in the DRAM and the accompanying signal transmission time depend on the arrangement of the memory cells inside the DRAM chip 10. In this case, the operation speed of the DRAM as a whole is limited by the signal transfer time of the far-end memory cell, which has the longest signal transfer time because it exists at a position distant from the address pins and I / O pins. This signal transmission time increases as the storage capacity of the DRAM increases, which imposes restrictions on the speedup of the DRAM.

With the increase in storage capacity of DRAM, D
Although the signal transmission time inside the RAM chip becomes long, the further speeding up of the DRAM is required along with the speeding up of the CPU. Therefore, various proposals have been made for speeding up the DRAM.

[0008]

[Patent Document 1] Japanese Patent Application Laid-Open No. 7-45795
The publication describes a DRAM in which a memory cell array inside a large-capacity DRAM is divided into two parts in the long side direction and the short side direction, respectively, and a total of four mats (sub-arrays) are divided. In one write cycle or one read cycle, the data of each of the four memory cells accessed in each of the four sub-arrays is combined to obtain the input / output bit width x1.
Data corresponding to 6 is input / output.

In the DRAM described in the above publication, the memory cell array is divided into four sub-arrays, and the bit lines and data lines in the memory cell array are shortened to reduce the load capacitance of the wiring, thereby increasing the speed of the DRAM. In addition, by arranging four I / O pins corresponding to each sub-array adjacent to the sub-array, the signal transmission time of write and read data is shortened and the speed is increased.

However, the DRAM described in the above publication has a problem that the delay of the wiring from each sub-array area to the data input / output pin of the chip is not sufficiently reduced. In addition, there is a problem in that there are large restrictions on the layout of wirings common to the sub-array regions.

In view of the above, the present invention is a semiconductor device suitable for a semiconductor device such as a DRAM and capable of high-speed operation, and delays the wiring between the sub chip area obtained by division and the data input / output pin. It is an object of the present invention to provide a semiconductor device in which the chip area can be divided and the restriction on the layout of the wiring common to the sub-chip area is small.

[0012]

In order to achieve the above object, a semiconductor device of the present invention includes a semiconductor chip having a plurality of sub-chip regions each having a plurality of data (signal) input / output pins, and the semiconductor chip. And a package substrate having a plurality of external electrodes, a wiring connecting the external electrodes and the data input / output pins, and a wiring connecting the data input / output pins in common. Is characterized by.

In the semiconductor device of the present invention, the chip area is divided into a plurality of sub-chip areas, and the wiring for connecting the data input / output pins of these sub-chip areas to each other and the data input / output pins of the sub-chip area and the external electrodes are formed. A structure is used in which the wiring to be connected is provided on the package substrate. By dividing the chip into each sub-chip area and arranging the data input / output pins in that sub-chip area, the signal transmission time in each sub-chip area and the signal transmission time between each sub-chip area and the data input / output pin Is shortened. The wiring common to the sub-chip area is the wiring of the package substrate, which reduces the restrictions on the wiring arrangement. Here, the wiring of the package substrate for wiring between the sub-chip regions and the like becomes long, but the thickness of these package wirings can be made larger than the wiring pattern in the chip, and the increase in signal transmission time can be suppressed.

In the semiconductor device of the present invention, as described above,
By suppressing an increase in signal transmission time in the package wiring and shortening a signal transmission time in the sub chip area and between the sub chip area and the data input / output pin, it is possible to speed up the semiconductor device as a whole. The package board is typically configured as a multilayer wiring board, for example, 2
A wiring pattern is formed between layers of the insulating layer having a layered structure. The wiring of the package substrate of the present invention is not limited to this and may be any wiring arranged outside the chip, and may be a bonding wire, for example.

According to a preferred embodiment of the semiconductor device of the present invention,
The plurality of sub-chip areas have substantially the same circuit configuration. Since the semiconductor chip has such a repetitive circuit structure, division into sub chip regions can be easily performed.

It is preferable that the semiconductor chip further has a common region having a circuit commonly used for the plurality of sub-chip regions. By making the wiring between the common region and the external electrode and the wiring between the common region and each sub-chip region as in-chip wiring as possible, the speed of the semiconductor device can be increased. As a circuit formed in the common circuit area, for example, a clock circuit can be given.

The semiconductor device of the present invention is a DRAM or SDR.
By applying it to a semiconductor memory such as AM, the effect is maximized. However, the semiconductor device of the present invention is not necessarily limited to a semiconductor memory, and can be applied to a system LSI including a semiconductor memory portion, and various semiconductor devices such as a general gate array.

When the semiconductor device of the present invention is applied to a semiconductor memory, a control system, an address system circuit, a pad, and a part of I / O (for example, 32 I's) are provided in a sub-chip area in a chip. Of the / O lines, 8 I / O lines, etc.)
Is preferably provided, and a clock circuit or the like is preferably provided in a common area in the chip.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a chip structure of an SDRAM constituting a semiconductor device according to an embodiment of the present invention.
The entire chip 10 has four sub-chip areas 11 and 1
It is divided into two common areas 12. Each sub-chip area 1
1, a memory area 13 in which a large number of memory cells are arranged in an array on both sides thereof is arranged, and I / O pins I / O0 to I / O31 and addresses are arranged in the central portion sandwiched between them. An indirect region 14 in which a signal pin 16 including a pin ADD and a control pin CTL is arranged is arranged. In the common area 12, the clock pin CLK and the clock circuit connected thereto are arranged. Each sub-chip area 11 and the common area 12 constitute one chip, are independent on the circuit, and
It is integrated in structure and appearance.

FIG. 2 shows a circuit configuration of a package 20 in which the SDRAM chip 10 is mounted on a package substrate. This SDRAM is 256M, x32
32 I / O terminals I / O0 to I / O31, which are internal terminals of the package 20, are grouped into four groups each of which has eight I / O terminals 21, and this grouping is performed. Corresponding to, the memory cell array of the chip 10,
It is divided into four sub-chip regions 11. Each sub-chip area 11 is composed of an SDRAM array of 64M × 8 structure.

Each I forming the external terminal 21 of the package 20
The / O terminal is independent for each sub-chip area 11 and passes through the grouped internal terminals of the package 20 and the corresponding sub-chip area 11 by the in-package wiring 22.
I / O pin of Further, the address and control signals are divided from the external terminal 21 of the package 20 by the in-package wiring 22 into four and supplied to the respective sub-chip regions 11. The internal clock supplied to each sub-array region 11 is transmitted by the in-chip clock wiring 15 passing inside the chip.

FIG. 3 is a plan view schematically showing the package 20 of FIG. The external electrode 21 of the package 20 is configured as, for example, a BGA (Ball Grid Array). The external electrodes 21 are bumps composed of solder or a metal ball similar thereto, and the number thereof is omitted in the drawing. The power supply terminal and the like are omitted. As shown in FIG. 3, the I / O terminals I / O0 to I / O31 are connected to the corresponding sub-chip areas 11, and the address terminals ADD and the control terminals CTL are commonly connected to the four sub-chip areas 11. There is. The clock terminal CLK is arranged in the common area 12 and is connected to a clock synchronization circuit common to the chips arranged in the common area 12.

The SDRAM of this embodiment is the same as the conventional DRAM shown in FIG.
It is similar to (SDRAM), and can be used in the same way as a conventional DRAM after being incorporated in a package.

In the SDRAM of the above-described embodiment, the chip 10 has a short signal transmission path from the input of the address signal to the input / output of the data, so that the wiring delay in the chip is reduced. FIG. 4 shows a signal transmission path in this access. In the example of the figure, a case is shown where a memory cell at the far end of the sub-chip area 11 is accessed from an address pin arranged at the central position of the indirect area 14 of the sub-chip area 11.

Here, assuming that the conventional SDRAM has a chip size of 10 × 6 mm ² , the SDRA of the above-described embodiment is used.
In M, some waste was generated in the placement of the indirect region 14 and the like, and the extended width was considered to be 1 mm each, and 11 x 8 mm ²
Suppose that In this case, the SDR of the present embodiment example
In AM, since the size of the sub-chip area 11 is 5 x 4 mm ² , the wiring length when the signal makes a round trip from the center to the far end of the sub-chip area 11 is (5/2 + 4/2) x 2 = 9 mm. . When the signal wiring of this length is driven equally in the signal propagation direction into, for example, 10 wirings, the delay per stage is τ1 = RC = when the wiring resistance is 200Ω / mm and the capacitance is 0.2pF / mm. 200x0.
9 x 0.2E-12x0.9 = 0.03ns, τall = 0.03ns x
10 = 0.3ns.

On the other hand, when the similar wiring delay is obtained in the conventional SDRAM chip, the signal path is as shown in FIG. 5, and the wiring length is 16 mm. Similar to the case of the above embodiment, if this wiring length is divided into 10 equal parts in the signal propagation direction, the delay per stage becomes τ1 = 0.09 ns, τall = 0.9 ns, and the present invention speeds up by about 0.6 ns. To do. In reality, the wiring delay tends to be slightly smaller than the time constant, and it is difficult to increase the speed by 0.6 ns.
It is considered that the speed is about ns). In the present embodiment example, further speedup as described below can be obtained.

Generally, in order to drive the signal wiring, the signal wiring is driven by a driver having a size corresponding to the load capacitance. Therefore, when the signal wiring inside the SDRAM has a large load capacitance, the number of stages of the driver is changed. Need to increase. Figure 6
9A schematically illustrates the configuration of the driver circuit 30 when the load capacitance of the signal wiring 35 is large. The driver circuit 30 has a three-stage configuration including a small drive capacity driver 31, a medium drive capacity driver 32, and a large drive capacity driver 33 in order from the output side of the signal generation circuit 34. In order to reduce the number of stages, the medium driving capacity driver 32 is excluded, and the small driving capacity driver 31
Even if an attempt is made to drive the large drive capacity driver 33 with (
(B)), the signal delay becomes large at that portion, and as a result, the time required for signal propagation rather increases. In the present embodiment, since the load capacitance of the signal wiring 35 including the I / O line is reduced, it can be driven by the driver circuit 30 having a two-stage configuration of the small driving capacitance driver 31 and the medium driving capacitance driver 32 (FIG. 6). (C)). Therefore, it is possible to speed up the signal corresponding to the delay of one driver.

Although the number of driver circuits varies depending on the circuit configuration, for example, there are 10 drive circuits corresponding to the driver circuits between the signal input and the signal output, and 0.2 ns per driver stage. Assuming that a delay is required, according to the above embodiment example, 0.2 ns x 10 stages = 2
ns can be speeded up. In practice, the signal generation circuit is designed to secure a certain level of driving capability, so the number of stages does not often simply increase. In addition, increasing the number of stages increases the driving capability and, conversely, increases the speed. In some cases, the speed up to 2ns cannot be expected, but a certain speed can be expected.

Further, in the SDRAM of the above embodiment,
Since the circuit scale of each sub-chip area 11 is reduced, the circuit scale of the decoder circuit is also reduced. 7 (a) and 7 (b) respectively illustrate configurations of a decoder circuit in the related art and the above-described embodiment. conventionally,
Assuming that the word driver circuit 40 drives eight word lines 41, in this case, the driver 43 driving the input line 44 of the decoder circuit 42 needs to drive four decoder circuits 42. On the other hand, in the present embodiment, since the circuit scale of the sub chip area 11 is small, the number of word lines 41 to be driven by the word driver circuit 40 is reduced to four, and along with this, the decoder circuit to be driven by the driver 43. 42 is halved to two. In reality, since the number of word lines 41 is larger, for example, 512 lines are provided, the number of decoder circuits 42 to be driven is greatly reduced, and thus a large speedup is achieved.

By the way, as a result of performing part of the signal wiring conventionally performed inside the chip by the package wiring 22 of the package 20, the signal wiring becomes long. Where I
Since the / O pins I / O0 to I / O31 exist in each sub-chip area 11, the external I / O terminal 21 of the package is arranged in the immediate vicinity of each sub-chip area 11 to increase the length of the I / O wiring. Can be suppressed to some extent. However, in the signal lines such as the address lines and the control signal lines, the signals have to be distributed to four places, so that the line length inevitably increases. The increasing wiring length is determined depending on the pattern of the package wiring 22, and therefore cannot be simply calculated, but the model illustrated in FIG. 8 is used for comparison. FIG. 1A is a simulation circuit 50 simulating the wiring of a conventional SDRAM, and FIG. 1B is a simulation circuit 50 simulating the wiring of the SDRAM of the present embodiment. The signal delay resulting from the comparison is shown in FIG.

The model of the simulation circuit 50 in FIG. 8 assumes a DRAM 53 as an external cache memory connected to the CPU 51 at a ratio of 1: 1. CPU5
In No. 1, the same package model of 7 nH, 60 mΩ, and 1.1 pF was used for the SDRAMs of the conventional and the present embodiment. The driver of the CPU 51 was replaced with an ideal power supply. C
The wiring in the substrate 52 from the PU 51 is assumed to be a wiring having a characteristic impedance of 50Ω and a length of about 3 cm (a delay amount of 0.2 ns). It is assumed that the SDRAM 53 and the terminating resistor are connected to this wiring end, and the terminating resistor is 50Ω and the terminating voltage is 1.4V. The SDRAM 53 is a conventional SDR.
In AM, a model of 1.7 nH, 20 mΩ, and 0.4 pF was used, and in this embodiment, a model in which each constant is 2.5 times is assumed. The input capacitance of the DRAM chip is 1 pF
And In the conventional SDRAM, the pin capacitance is 1.4 pF, which is 0.4 pF of the package, and in the present embodiment, it is 1x4 +.
0.4x2.5 = 5pF.

The internal model of the DRAM chip 53 has a different load capacity to be connected to each wiring, and even if the circuit type is the same, the gate size is different when the chip size is different. Is difficult to create. For this reason, a model is used in which drivers (inverter circuits) in which a plurality of inverters are arranged are connected by wiring. In the embodiment, the number of inverter stages of each driver is two, and in the past, the number of inverter stages of each driver is three. This is because the conventional configuration cannot effectively drive the two stages. Other assumed wiring lengths are shown in FIG. In this model, the effect due to the reduction in the number of decoders is not simulated, so it is expected that the improvement effect is actually larger than this result.

According to the simulation result, in the model of the present embodiment, the package portion is 0.2 compared with the conventional one.
A delay of ns is observed. But inside the chip 0.6
A high speed of ns is obtained, and a high speed of 0.4 ns is realized as a whole.

FIG. 10 and FIG. 11 show the consideration of the effect of the present invention which differs depending on the type of SDRAM. SD
In the RAM, there are a form in which read data is latched by a clock signal and a form in which it is not latched. The SDRAM mainly used at present is a type that latches read data. In the non-latching type, the package delay is large according to the above model, but the output can be speeded up by reducing the internal delay. This speedup
The conventional delay is shown in FIG. 10 (a), and the delay of this embodiment example is shown in FIG. 10 (b).

In the case of the SDRAM of the type that latches the output, by adopting the structure in which the chip is divided into the sub-chip areas, if the output clock has a package delay, the data must wait for the output clock. The delay from the clock to the output may be slower than the conventional device. This situation is shown in FIG. 11A showing the delay of the conventional device, and FIG. 11B showing the delay when the output clock is delayed. In this embodiment, a clock synchronizing circuit arranged in the common area is used to generate a clock for controlling the output at an appropriate timing, and such a delay due to the clock delay is removed. By doing so, even in the case of the type in which the output is latched, the output clock is not delayed, and the speedup as a whole is possible ((c) in the figure).

In the present embodiment, in addition to the above configuration, as shown in FIG. 12, a clock input buffer is provided for each sub-chip area. The clock circuit 60 inputs the clock signal input from the clock pin 61 to the four clock buffers 62 corresponding to the sub-chip area 11, and outputs these outputs to the internal clock signal line 63 (1 in FIG. 2).
59) supply to each sub-chip area 11.

In this embodiment, a clock system circuit is arranged in the common area 12. However, not only the clock system circuit but also circuits related to the entire chip, such as circuits related to power supply, are laid out in the common area 12. However, it is preferable that the wiring connecting these be in-chip wiring. Further, the division into the sub-chip regions is four in the present embodiment, but may be divided into eight or two and can be performed without being restricted by the arrangement of the external electrodes of the package. Further, the divided shape is not particularly limited. For example, as shown in FIG. 13, in a DRAM having 18 I / O lines, the sub chip areas may be divided so that the sizes thereof are different from each other.

In the example shown in FIG. 3, the wiring 22 inside the package is laid out in a single layer. However, when all the signal pins 16 are actually connected, it is expected that a single layer layout will be difficult. In this case,
As shown in FIG. 4, the package wiring 22 is laid out in a plurality of layers. In this way, by using the package wirings 22 of a plurality of layers, the wiring distances from the external electrodes 21 of the package 20 to the signal pins 16 of the chip 10 can be made equal to some extent, and the delays can be made uniform for each sub-chip area 11. .

As shown in FIG. 15, the sub-chip area 11
The arrangement is symmetrical with respect to the common area 12 having the clock system circuit as shown by a straight line or a dotted line in the figure. In addition, it is preferable to lay out a circuit that is particularly required by a clock, such as an address circuit or a control system circuit, on the clock circuit side. In this case, the clock can be distributed efficiently, and the speed of the chip can be further increased.

Although the present invention has been described based on its preferred embodiments, the semiconductor device of the present invention is not limited to the configurations of the above-described embodiments, but has the configurations of the above-described embodiments. Various modifications and changes are also included in the scope of the present invention.

[0041]

As described above, according to the semiconductor device of the present invention, the area inside the chip is divided into a plurality of sub-chip areas, and the wiring between each sub-chip area and between each sub-chip area and the external electrode is divided. By adopting a configuration in which wiring is performed by package wiring, when dividing the chip area for speeding up the semiconductor device, in the sub-chip area,
Further, there is an effect that the delay of the wiring connecting the sub chip area and each data input / output pin is reduced, and the speed of the semiconductor device can be increased as a whole.

[Brief description of drawings]

FIG. 1 is an SD according to a semiconductor device of an embodiment of the present invention.
The block diagram which shows the chip structure of RAM.

FIG. 2 is a circuit diagram in a package of a semiconductor device according to an embodiment of the present invention in which the SDRAM chip of FIG. 1 is mounted.

FIG. 3 is a plan view schematically showing the arrangement of the packages shown in FIG.

FIG. 4 is a plan view showing signal transmission during access of the SDRAM chip of FIG.

FIG. 5 is a plan view showing signal transmission when a conventional SDRAM chip is accessed.

FIG. 6 is a circuit diagram showing a comparison of configurations of driver units for driving wirings.

FIG. 7 is a circuit diagram showing a configuration of a decoder circuit in the embodiment and a conventional SDRAM in comparison.

FIG. 8 is a circuit diagram used when simulating a signal delay inside a package.

FIG. 9 is a graph showing a result of simulating delay in the example embodiment and the conventional SDRAM.

FIG. 10 is a timing chart showing a comparison of signal delay with a conventional one when the present invention is applied to an SDRAM of a type that is not latched by a clock.

FIG. 11 is a timing chart showing a comparison of signal delay with that of the prior art when the present invention is applied to an SDRAM of a clock latch type.

FIG. 12 is a circuit diagram showing a configuration of a clock circuit.

FIG. 13 is a plan view of a chip showing division of a sub-chip area according to another embodiment of the present invention.

FIG. 14 is a plan view showing package wiring in a semiconductor device according to still another embodiment of the present invention.

FIG. 15 is a plan view of a chip showing a preferred example of division of the chip area.

FIG. 16 is a plan view schematically showing an SDRAM chip in a conventional semiconductor device.

FIG. 17 is a plan view schematically showing the arrangement of a conventional semiconductor device in a package.

[Explanation of symbols]

10: Chip 11: Sub-chip area 12: Common area 13: Memory area 14: Indirect area 15: Clock wiring 16: Signal pin 20: Package 21: Package external electrode 22: Package wiring 30: Driver circuit 31-33: Driver 34: Signal generation circuit 35: Wiring load 40: Word driver circuit 41: Word line 42: Decoder circuit 43: Driver 50: Simulation circuit 51: CPU 52: Package wiring 53: DRAM 60: Clock circuit 61: Clock pin 62: Clock buffer 63: clock signal line 70: sRAM chip 71, 72: Sub-chip area

Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 27/10 681F

Claims (6)

[Claims] 1. A semiconductor chip having a plurality of sub-chip regions each having a plurality of data input / output pins, and a package substrate on which the semiconductor chip is mounted,
A semiconductor device comprising: a package substrate having a plurality of external electrodes, a wiring connecting the external electrodes to the data input / output pins, and a wiring connecting the data input / output pins in common. 2. The semiconductor device according to claim 1, wherein the plurality of sub-chip regions have substantially the same circuit configuration. 3. The semiconductor device according to claim 1, wherein the semiconductor chip further has a common region in which a circuit commonly used in the sub chip region is formed. 4. The semiconductor device according to claim 4, wherein a clock circuit is formed in the common area, and the clock circuit and each of the sub-chip areas are connected by an in-chip wiring. 5. The semiconductor device according to claim 1, which is configured as a semiconductor memory. 6. A semiconductor memory including a memory chip having a signal pin including a plurality of data input / output pins, a memory cell array in which a plurality of memory cells are arranged in an array, and a package substrate on which the memory chip is mounted. In the device, the data input / output pins are grouped, the memory cell array is divided into a plurality of sub-array regions corresponding to the grouping, wiring between the sub-array regions, and external electrodes of the package substrate and each sub-array region. A semiconductor memory device characterized in that the wiring between the two is connected by a package wiring provided on a package substrate.