JP2008153288A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the reliability of transmission timing that regulates a differential strobe signal to a single-end signal transmitted on a wiring board. <P>SOLUTION: To equalize a signal propagation delay in a single-end signal route (PAS_sng) that inputs/outputs a signal among a plurality of semiconductor devices (1, 2, 3) mounted to a wiring board (6) and in a differential strobe signal route (PAS_dif) that inputs/outputs a differential strobe signal to regulate signal transmission timing among devices, the differential strobe signal route is made longer than the single-end signal route while it is equivalent to the length of wiring having a specified width that is formed on the wiring layer of the wiring board. A difference between characteristic impedances in both routes causes the displacement of load driving timing due to signals transmitted in the respective routes on the wiring board, however, a difference in length between both routes offsets the displacement of timing on the basis of the difference of characteristic impedances. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a technique for reducing a difference in timing of a propagation signal between a single-ended wiring and a differential signal wiring that connect devices on a wiring board, for example, DDR conforming to JEDEC STANDARD No. 79-2B (Double Data Rate) This invention relates to a technology effective when applied to a mounting board on which 2-SDRAM (Synchronous Dynamic Random Access Memory) and a microcomputer having a memory interface circuit are mounted.

  As an international standard for SDRAM, there is a JEDEC standard (JEDEC STANDARD), which standardizes standards for terminal arrangement, terminal function, operation mode, and the like. For example, in the DDR2-SDRAM defined by JEDEC STANDARD No. 79-2B according to non-patent literature, the data strobe signal and the clock signal are a differential pair, and the terminal group of the data and data strobe signal system and the command and address system The terminal groups are separated, and in particular for the interface specification with 16 parallel data input / output bits (× 16 bits), the upper byte data and data strobe signal system terminal group, the lower byte data and The arrangement with the terminal group of the data strobe signal system is also separated.

  In order to equalize the signal propagation delay between the signal lines of a plurality of bits on the wiring board, an equal length wiring method is generally used. At this time, in the detour delay wiring portion for adjusting the length of the signal line, by partially changing the line width or line thickness of the line, the technology for making the signal propagation delay time substantially the same in a plurality of signal paths There exists description in patent document 1. FIG.

JEDEC STANDARD, DDR2 SDRAM SPECIFICATION JESD79-2B (Revision of JESD79-2A), January 2005, JEDEC SOLID STATE TECHNOLOGY ASSOCITION JP 2003-152290 A

  The present inventor examined the propagation delay in both transmission systems when transmitting a data strobe signal that defines data transmission timing differentially as represented by DDR2-SDRAM and transmitting data in a single end. . According to this, if the single-end data line and the differential data strobe line are simply made equal in the wiring board design, an error occurs in the propagation delay between the data and the data strobe signal, and the possibility of erroneous recognition of the read data increases. As a result, the write operation margin is reduced. As represented by DDR2-SDRAM, the influence increases as the access cycle becomes shorter.

  An object of the present invention is to improve the reliability of transmission timing defined by a differential strobe signal with respect to a single-ended signal transmitted on a wiring board.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, a single-end signal path (PAS_sng) for inputting / outputting a signal between the plurality of semiconductor devices (1, 2, 3) mounted on the wiring board (6), and transmission of the signal between the plurality of devices. A predetermined width formed in the wiring layers (L1, L6) of the wiring board in order to equalize the signal propagation delay in the differential strobe signal path (PAS_dif) for inputting / outputting the differential strobe signal defining the timing The differential strobe signal path is made longer than the single-ended signal path, corresponding to the length of the wiring.

  The difference in characteristic impedance between the two paths causes a shift in load drive timing due to a signal propagating through each path on the wiring board and a difference in drive speed with respect to the load. This offsets the difference in timing and the difference in driving speed. Thereby, for example, an error in data recognition according to the timing of the data strobe signal does not occur, and a write operation margin defined by the timing does not decrease.

  A representative one of the inventions disclosed in the present application will be briefly described as follows.

  That is, it is possible to improve the reliability of the transmission timing defined by the differential strobe signal with respect to the single-ended signal transmitted on the wiring board.

1. Representative forms of embodiments of the inventions
First, an outline of a typical embodiment of the invention disclosed in the present application will be described. The reference numerals in the drawings referred to with parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  In a semiconductor device according to a typical embodiment of the present invention, a memory device (2, 3) and an access control device (1) capable of controlling access to the memory device are mounted on a wiring board (6). The memory device has a plurality of first data terminals (DQ0 to DQ15) and first differential strobe signal terminals (LDQS, LDQSB, UDQS, UDQSB) corresponding to the first data terminals. The access control device includes second data terminals (DQ0 to DQ15) electrically connected to the first data terminal and second differential strobe signal terminals (LDQS, LDQS, electrically connected to the first differential strobe signal terminal). LDQSB, UDQS, UDQSB). The wiring board has a single-end data path (PAS_sug) from the first data terminal to the second data terminal, and a differential strobe signal path (PAS_dif) from the first differential strobe signal terminal to the second differential strobe signal terminal. ). In order to equalize the signal propagation delay in the single-ended data path and the differential strobe signal path, the differential strobe signal path corresponds to the length of a predetermined width of wiring formed in the wiring layer of the wiring board. It is longer than the data path.

  The impedance (Zodd = odd mode impedance) of both conductors when a pair of conductors is driven by a differential signal in the differential strobe signal path is half of the differential impedance of the differential strobe signal path. The mode impedance is slightly smaller than the characteristic impedance of the single-ended signal path. This difference causes a shift in load drive timing due to a signal propagating through each path on the wiring board and a difference in drive speed with respect to the load. The difference in path length between the differential strobe signal path and the single-ended signal path cancels out the timing shift and the drive speed difference. Thereby, for example, an error in data recognition according to the timing of the data strobe signal does not occur, and a write operation margin defined by the timing does not decrease. The odd mode impedance is the impedance of both conductors with respect to the ground when a conductor pair is driven by a differential signal. The differential impedance can be defined as a value when the impedance between two conductors is measured, and the differential impedance where the conductor is insulated from the ground is equal to the characteristic impedance. In this sense, in this specification, the differential impedance may be read as the characteristic impedance of the conductor pair.

  As a specific form, the single-ended data path and the differential strobe signal path have the same cross-sectional shape of the single wiring, and the characteristic impedance of the single-ended data path is more than half the differential impedance of the differential strobe signal path. It has been enlarged. Wiring design of the single-ended data path and the differential strobe signal path on the wiring board is facilitated.

  As a more specific form, the wiring board has wiring layers on the front and back surfaces thereof, and the front and back wiring layers (L1, L6) and the front and back surfaces are used to form the single-ended data path and the differential strobe signal path. Vias (VIA) for connecting the wiring layers on the back surface to each other are used. Compared with the pair of either the front or back wiring layer and the inner wiring layer, the pair of wiring layers on both the front and back surfaces can easily meet physical conditions such as the effective dielectric constant, and can be connected to the device. In this respect, it is suitable for equal delaying of the single-ended data path and the differential strobe signal path.

  As a more specific form, the memory device includes a plurality of bytes (DQ0 to DQ15) for the first data terminal and the first differential strobe signal terminals (LDQS, LDQSB, UDQS, UDQSB) in units of bytes. The access control device has a plurality of bytes (DQ0 to DQ15) for the second data terminal and has the second differential strobe signal terminals (LDQS, LDQSB, UDQS, UDQSB) in units of bytes. The first data terminal and the first differential strobe signal terminal of the memory device and the second data terminal and the second differential strobe signal terminal of the access control device are arranged to face each other in a corresponding byte unit. . Single-end data path and differential strobe signal path can be arranged in a single unit for each corresponding byte, so it is easy to design equal-length wiring of single-end data path and equal delay with differential strobe signal path .

  As a more specific form, the memory device and the access control device are mounted on one wiring layer on the front and back surfaces. At this time, the single-end data path of the corresponding byte has a path formed in the one wiring layer without passing through the via and a path formed in both the front and back wiring layers through the via. . This is because if the pitch of the external terminals of the device is narrow, all the wirings of the single-ended data path cannot be formed on the device mounting surface.

  As a more specific form, when a predetermined single-ended data path is formed in the same wiring layer as the corresponding differential strobe signal path, and both paths have the same number of vias, both The difference in the path lengths of these paths is the difference in the lengths of the wirings formed in the wiring layer. A predetermined single-end data path is formed in the same wiring layer as the corresponding differential strobe signal path, and the same is true when no via is interposed on both paths. Also, the predetermined single-ended data path is not formed in the same wiring layer as the corresponding differential strobe signal path, and vias are interposed in the corresponding differential strobe signal path, When there is no via, the difference in the path length between the two paths is the difference in the length of the wiring formed in the wiring layer and the difference depending on the presence or absence of the via. Further, the predetermined single-ended data path is not formed in the same wiring layer as the corresponding differential strobe signal path, and no via is interposed in the corresponding differential strobe signal path. When there is a via in the path, the difference in path length between the two paths is the difference in the length of the wiring formed in the wiring layer and the difference in the presence or absence of the via, or the difference in the presence or absence of the via.

  As a more specific form, the memory device is a DDR2-SDRAM having a JEDEC standard terminal arrangement, and the access control device is a microcomputer to which the DDR2-SDRAM is connected.

  In a more specific form, the data processing device outputs write data together with a data strobe signal to the memory device in a write access, and the memory device outputs read data together with the data strobe signal in response to a read access instruction from the data processing device. Output.

2. Next, the embodiment will be described in more detail.

<< Arrangement of microcomputer and SDRAM >>
FIG. 1 shows an example of a semiconductor device according to the present invention. A microcomputer 1 and two DDR2-SDRAMs (also simply referred to as SDRAMs) 2 and 3 are mounted on the wiring board 6. The microcomputer 1 includes a package substrate (substrate) 1B, a microcomputer chip (semiconductor chip) 1A mounted on the surface of the package substrate 1B, a resin sealing body for sealing the microcomputer chip 1A, and a back surface of the substrate. A package of a BGA (Ball Grid Array) type or a package of a CSP (Chip Size Package) type having a ball electrode provided on the substrate. As a representative, the microcomputer 1 separately shows a microcomputer chip (MCU_CHP) 1A and a package substrate 1B.

  The SDRAMs 2 and 3 may be configured by a BGA type package or a CSP type package similarly to the microcomputer 1, but the present invention is not limited to this, and the pitch of the electrode pads of the semiconductor chip is converted by a rewiring pattern. It may be configured by a wafer level CSP or a WPP (Wafer Level Package) type package.

  The terminal arrangement of the BGA package in the SDRAMs 2 and 3 is defined in Non-Patent Document 1. For example, the terminal arrangement in the case where the number of parallel data input / output bits is 16 bits is shown in FIG. According to this terminal arrangement, the data and data strobe system signal terminal group and the command and address system terminal group CAPA are separated, and the data and data strobe system signal terminal group is also connected to the upper byte unit terminal group UBPA and the lower byte unit terminal group LBPA. To be separated. These terminal groups are based on the short side on the A1 terminal (A1 pin) side in the standard, and along the long side, the upper byte unit terminal group UBPA, the lower byte unit terminal group LBPA, the command and address system terminal group CAPA. Are arranged in the order of In FIG. 2, DQ0 to DQ15 are data input / output terminals (first data terminals) to which data is input or output, and LDQS and LDQSB are input to or output from lower byte data of DQ0 to DQ7. The differential data strobe signal terminal (first differential strobe signal terminal), UDQS, and UDQSB that specify the transmission timing of the data are input to the upper byte data of DQ8 to DQ15 or the transmission timing of the data output from the lower byte data. Differential data strobe signal terminals (first differential strobe signal terminals) to be defined, A0 to A15 are address input terminals, and BA0 to BA2 are bank address input terminals. Hereinafter, the data strobe signal terminals LDQS and UDQS may be collectively referred to as the data strobe signal terminal DQS, and the data strobe signal terminals LDQSB and UDQSB may be collectively referred to as the data strobe signal terminal DQSB. RASB, CASB, and WEB are command input terminals, CSB is a chip selection terminal, CK and CKB are differential clock input terminals, CKE is a clock enable terminal, LDM is a data mask terminal for lower byte data of DQ0 to DQ7, and UDM is DQ8 This is a data mask terminal for the upper byte data of .about.DQ15. VDD and VDDQ are memory power supply terminals, and VSS and VSSQ are ground terminals. VDDQ and VSSQ are dedicated to the power supply and ground of the DDR2-SDRAM data input / output system and the data strobe signal input / output circuit (external output and external input / output circuit). VDD and VSS are used as a power source for other circuits (core circuit) of DDR2-SDRAM and an external terminal of the ground. Here, it is assumed that the voltage levels of VDDQ and VDD are equal to 1.8V, for example, and the voltage levels of VSSQ and VSS are also equal to 0V. VDDL and VSSDL are a power supply and a ground voltage dedicated to a DLL (Delay Locked Loop) circuit used for generating internal timing. VREF is an input terminal for a reference potential, and is given a determination level for an external interface in SSTL (Stub Series Terminated Transceiver Logic). NC is a non-connection terminal.

  In FIG. 1, a microcomputer chip (semiconductor chip) 1A has memory interface circuits 4 and 5 for SDRAMs 2 and 3 arranged in a divided manner along both sides of the edge having one corner as a base point. The memory interface circuits 4 and 5 are connected to a memory controller (not shown) provided in the microcomputer chip (semiconductor chip) 1A. In FIG. 1, the microcomputer chip 1 </ b> A has a square shape in plan view, and is constituted by a square, for example. The SDRAMs 2 and 3 have a square planar shape, for example, a rectangular shape. As a connection form of the SDRAMs 2 and 3 to the microcomputer chip 1A, a form in which the long sides of the SDRAMs (DDR2-SDRAMs, memory devices) 2 and 3 are opposed to the microcomputer (access control device) 1 capable of access control is exemplified. . This connection form has the following advantages. In view of the fact that the terminal pitch of the BGA package is the same in all directions, it is easier to reduce the density of wiring (PCB wiring) connecting the microcomputer 1 and the SDRAMs 2 and 3 with the long sides facing each other. Furthermore, considering the terminal arrangement of the SDRAMs 2 and 3 that the upper byte unit terminal group UBPA and the lower byte unit terminal group LBPA are separated along the long side, the PCB wiring is regulated for each byte unit. It becomes easy to make. Further, the data of the memory interface circuits 4 and 5 and the data strobe signal system circuit in the microcomputer chip 1A can be ordered for each byte unit, which can contribute to the simplification of circuit design.

  By connecting the command and address system terminal group CAPA separated from the data and data strobe system signal terminal groups closer to the corner of the microcomputer 1, these terminals and the microcomputer 1 are connected. The PCB wiring can have a wiring topology in which the signal wiring drawn from the microcomputer 1 branches into two and the two wiring lengths after branching are equal. Also in this case, the PCB wiring length is shorter in the arrangement form in which the long sides of the SDRAMs 2 and 3 are opposed to the microcomputer 1. In FIG. 1, UBCL means upper byte unit system PCB wiring, LBCL means lower byte unit system PCB wiring, and CACL means command and address system PCB wiring.

  FIG. 3 illustrates the interface function of the data system unit in the memory interface circuits 4 and 5 of the microcomputer 1. The memory interface circuits 4 and 5 divided in the microcomputer 1 are also arranged in a command and address system terminal group CAPA, a lower byte unit terminal group LBPA, and an upper byte unit terminal group UBPA along the long sides of the SDRAMs 2 and 3. Correspondingly, it has two data system unit units as a command and address system interface unit CAIF and a data system unit. One data system unit is the upper data system interface unit UBIF, and the other data system unit is the lower data system interface unit LBIF. The command and address interface unit CAIF includes an address output and command input / output interface circuit connected to a command and address group terminal group CAPA and the like. Each data system unit LBIF, UBIF uses the unit of data input / output as bytes, and the circuit configuration itself is the same whether it corresponds to the lower byte or the upper byte. Is only different. According to the JEDEC standard DDR2-SDRAM terminal arrangement, in the DDR2-SDRAM, the data and data strobe signal system terminal groups UBPA and LBPA and the command and address system terminal group CAPA are separated along the long side thereof. In particular, for interface specifications in which the number of parallel data input / output bits is 16 bits (× 16 bits), the upper byte unit terminal group UBPA of the upper byte data and data strobe signal system, and the lower byte data and data strobe signal The arrangement with the system terminal group LBPA is also separated. When this long side is opposed to the data system units UBIF and LBIF of the microcomputer 1, the wiring path from the byte data and data strobe signal system terminal groups UBPA and LBPA to the data system units UBIF and LBIF is simplified. Is possible. This ensures the ease of wiring design in the wiring board 6.

  In FIG. 3, each of the data system unit units LBIF and UBIF includes seven data input / output circuits 10, a data mask signal circuit 11, an inverted data strobe signal circuit 12, non-sequentially in order from one corner side of the microcomputer chip 1A. It has an inverted data strobe signal circuit 13 and one data input / output circuit 14.

  FIG. 4 shows the reason for adopting the arrangement of the interface functions shown in the data system unit units LBIF and UBIF of FIG. In FIG. 4, the wiring lead-out path from the ball electrodes (BALL) of the SDRAMs 2 and 3 to the wiring board 6 is illustrated, but here, the wiring passing between the balls is one, and the through-hole (THRH) is formed on the wiring board 6. ) To connect between wiring layers. The signal arrangement of the lead wiring at this time is the arrangement SGA1 for the lower byte data and data strobe signal system terminal group LBPA of the SDRAM 2, and for the upper byte data and data strobe signal system terminal group UBPA. The sequence is SGA2. For the lower byte data and the data strobe signal system terminal group LBPA of the SDRAM 3, the array SGA3 is used. For the upper byte data and the data strobe signal system terminal group UBPA, the array SGA4 is used. The signal arrays SGA1, SGA2 and SGA4 are equal, whereas the signal array SGA3 is different only in the data 1 bit array. Therefore, the arrangement of the interface functions in the data system unit LBIF, UBIF described with reference to FIG. 3 is made to coincide with the signal arrays SGA1, SGA2, SGA4. In short, the configuration of the data and data strobe signal system circuits of the memory interface circuits 4 and 5 in the microcomputer chip 1A is made the same for each byte unit, and priority is given to the simplification of the circuit design. This is to avoid changing the configuration of some circuit units in order to optimize the data terminal arrangement of 1 bit at most with respect to the PCB wiring.

  FIG. 5 illustrates the ball electrode arrangement of the microcomputer 1. Actually, the ball electrodes are arranged in a matrix at a predetermined pitch in the vertical and horizontal directions. Here, for convenience, the individual ball electrodes are drawn as square frames. The microcomputer package is in BGA form, the pad electrode of the microcomputer chip is connected to a solder bump electrode (not shown) via the WPP wiring (redistribution layer) on the chip surface, and the solder bump electrode is connected to the ball electrode Is done. The terminal functions are assigned to the ball electrodes so that the correspondence between the terminals and lead wiring arrangements of the DDR2-SDRAMs 2 and 3 (FIG. 4) and the pad electrode arrangements of the microcomputer chip (FIGS. 3 and 4) can be maintained as much as possible. That's fine. An example is illustrated in FIG.

  Regarding the assignment of terminal functions to the ball electrodes, the arrangement of differential terminals is considered. That is, a pair of LDQS and LDQSB, a pair of UDQS and UDQSB, and a pair of CK and CKB are assigned to the adjacent ball electrodes on the first and second rounds from the outermost circumference, or on the third round. Are assigned to the adjacent ball electrodes on the fourth circumference to form differential terminals. Here, it is assumed that one wiring passes between the balls on the PCB, and the connection between the wiring layers is made using a through-through hole (THRH) on the PCB. Then, the wiring connected to the ball electrode on the first circumference is drawn out from the outermost periphery of the ball grid array as it is, and the wiring connected to the ball electrode on the second circumference is connected to the ball electrode on the first circumference. It is pulled out through the wiring of the book. The wirings connected to the third and fourth ball electrodes are similarly drawn out through different wiring layers from the first and second ball electrodes. Considering the correspondence to such a general wiring structure, the differential terminals are arranged adjacent to the third and fourth circumferences as shown in the figure, or the first and second circumferences are not shown. Since the wirings connected to the differential terminals can be adjacent to each other on the same wiring layer by arranging adjacently on the circumference, it is easy to maintain the canceling effect of the common-mode noise component even on the wiring board 6. become. Note that the pair of CK and CKB is often arranged at a corner, and the wiring is not as dense as other areas. Therefore, the pair of CK and CKLB is not limited to this form.

  In the description so far, the microcomputer 1 is arranged so that the long side of the SDRAM faces the microcomputer 1, but as illustrated in FIG. 6, the microcomputer 1 and the SDRAM 2 have the short sides of the SDRAMs 2 and 3 facing the microcomputer 1. , 3 can also be mounted on the wiring board 6. In this case, it is not possible to obtain all the effects of the arrangement form shown in FIG.

<< Data wiring and differential data strobe signal wiring >>
In the read operation, the DDR2-SDRAMs 2 and 3 transfer 2n bits of data from the memory cell array to the I / O buffer for each clock of the clock signal supplied from the outside, and every 1/2 clock cycle (clock signal Output both n bits at the rising and falling edges). Data supplied from outside to the I / O buffer is transferred from the I / O buffer to the memory cell array in units of 2n bits every n clock cycles. At this time, the internal bus width is twice the number n of parallel data input / output bits of the I / O buffer, thereby realizing input / output of data at twice the data rate of the internal bus. For example, the data transfer rate of the DDR2-SDRAMs 2 and 3 is 400 to 800 Mbps / pin. As described above, since the DDR2-SDRAMs 2 and 3 control data input / output in synchronization with both rising and falling edges of the clock signal, the data input / output timing is accurately controlled based on the single clock. Adopt a differential clock because it is difficult to do. Accordingly, a differential signal is also used for the data strobe signal that defines the input / output timing of data. In the read operation, the SDRAMs 2 and 3 output read data together with the data strobe signal, and the microcomputer 1 receives the data strobe signal and adjusts the timing for reading the read data. In the write operation, the microcomputer 1 outputs a data strobe signal and write data, and the SDRAMs 2 and 3 take in the write data in synchronization with the change of the data strobe signal. As illustrated in FIG. 7, in the write operation, the edge of the data strobe signal is located at the center of the write data, but in the read operation, the edge of the data strobe signal is matched with the edge of the read data. When the microcomputer 1 receives read data from the SDRAMs 2 and 3, the microcomputer 1 controls to internally delay the received data strobe signal to the center of the read data, and reads the read data in synchronization with the edge change of the delayed data strobe signal. recognize. Such delay control by the microcomputer 1 is performed by using a delay locked loop circuit.

  As is apparent from the above, it is important that the phase relationship shown in FIG. 7 is maintained between the data input or output between the microcomputer 1 and the SDRAMs 2 and 3 and the data strobe signal. When signals propagate on the wiring board connecting the microcomputer 1 and the SDRAMs 2 and 3, the delays generated in both signal wirings must be equalized. If the phases of the data and the differential strobe signal (complementary signal) deviate from the state shown in FIG. 7, it is apparent that read data is erroneously recognized in read operation and write operation margin is reduced in write operation.

  Hereinafter, a single-end data path (single-end data wiring) for electrically connecting the data terminal (second data terminal) of the microcomputer 1 and the data terminals (first data terminals) corresponding to the SDRAMs 2 and 3 respectively. The differential strobe signal terminal (second differential strobe signal terminal) of the microcomputer 1 and the differential data strobe signal terminal (first differential strobe signal terminal) corresponding to each of the SDRAMs 2 and 3 are electrically connected. A configuration for equal delay (equal length, equal impedance) with the differential strobe signal path (differential data strobe signal wiring) will be described.

  FIG. 8 illustrates the difference in charge / discharge speed with respect to the load due to the difference in characteristic impedance. The waveform shown in the figure is, for example, when a wiring (T-Line) having a characteristic impedance Z0 = 40 to 75Ω and a propagation delay time of 204 ps (corresponding to a length of 40 mm) is driven by a driver (DRV). Waveforms that can be observed by using a circuit analysis. The illustrated input capacitance and termination resistance of the load are examples. According to this, the charge / discharge timing of the load and the charge / discharge speed depend on the characteristic impedance. In the figure, the case of Z0 = 40 and Z0 = 75 is representatively illustrated. However, as the characteristic impedance increases, the charge / discharge timing with respect to the load is delayed and the charge / discharge rate is also decreased.

  FIG. 9 illustrates the difference in charge / discharge speed and the like for the load due to the single-ended data line L_DQ connecting the corresponding data terminal and the differential strobe signal lines L_DQS and L_DQSB connecting the corresponding data strobe signal terminals. Is done. The single-end data wiring L_DQ means wiring in a wiring layer for connecting the data terminal of the microcomputer 1 and the corresponding data terminals of the SDRAMs 2 and 3. The differential strobe signal wires L_DQS and L_DQSB mean a pair of wires in a wiring layer for connecting the differential strobe signal terminals of the microcomputer and the differential strobe signal terminals of the SDRAMs 2 and 3.

  The waveform shown in the figure is a load that is driven when an equal-width and equal-length single-end data line L_DQ and differential strobe signal lines L_DQS and L_DQSB formed in the same wiring layer on the wiring board are driven from the SDRAM. Waveforms that can be observed on the side are obtained by circuit analysis. L = a is the length of each single wiring. According to this, the charge / discharge timing of the load and the charge / discharge speed are different between the single-ended data line L_DQ and the differential data strobe signal lines L_DQS and L_DQSB, and the differential data strobe signal lines L_DQS and L_DQSB are different. The signal arrives early.

  In the differential strobe signal line L_DQS, the impedance of both conductors when the conductor pair is driven by a differential signal, that is, the odd mode impedance (= Zodd) is half of the differential impedance (Zdiff) of the differential strobe signal line. However, the odd mode impedance is slightly smaller than the characteristic impedance of the single-ended data line L_DQ. Similar to FIG. 8, this difference also causes a difference in load drive timing and load drive speed due to signals propagating through the respective paths on the wiring board in the case of FIG. The determination level of the input circuit for detecting changes in the differential data strobe signals DQS and DQSB in the SDRAMs 2 and 3 is set to a level half the signal amplitude in the signals DQS and DQSB. For example, in FIG. 9, when the signal amplitude is 1.8 V, the determination level is 0.9 V, and at this determination level, the intersection of the differential data strobe signals DQS and DQSB causes a time difference between the data strobe signal DQ and δ. . For example, when δ = 30 ps, the time corresponds to a propagation delay time of 5 mm in terms of the length of the wiring. Therefore, the differential data strobe signal path formed on the wiring substrate 6 is made longer than the single-ended data path by the length corresponding to the time difference δ corresponding to the wiring length of the wiring layer. The difference in path length between the path of the differential strobe signal and the path of the single-ended signal cancels the timing shift. In short, the propagation signal delay between the differential strobe signal path corresponding to the difference and the single-ended signal path is equalized. Thereby, for example, an error in data recognition according to the timing of the data strobe signal does not occur, and a write operation margin defined by the timing does not decrease.

  Further specific examples will be described. FIG. 10 illustrates a vertical cross-sectional structure of the wiring board 6. Although not particularly limited, the wiring board 6 includes two core layers (COR) 20 and 21 made of glass fiber-impregnated epoxy resin and three layers impregnated with the resin, so-called prepreg layers (PP) 22 to 24. Wiring layers L1 to L6 are sequentially formed on the front and back surfaces of the core layers 20 and 21 and the surface layers of the prepreg layers 22 and 24, and the surfaces of the wiring layers on the front and back surfaces are covered with protective layers (SR) 25 and 26. ing. The core layers 20 and 21 are, for example, 0.4 mm, and the intermediate layers 22 to 24 are 0.2 mm. The mounting surface of the microcomputer 1 and the SDRAMs 2 and 3 is a wiring layer L1. The wirings of the wiring layers L1 to L6 are, for example, copper wirings. The figure illustrates one via (through through hole) VIA that connects the wiring layer L1 and the wiring layer L6.

  The formation of the single-ended data wiring L_DQ for connecting the microcomputer 1 and the corresponding data input / output terminals of the SADRAMs 2 and 3 and the differential strobe signal wirings L_DQS and L_DQSB for connecting the corresponding differential data strobe signal terminals The wiring layers L1 and L6 on the back surface are assigned. In addition, the wiring layer L1 is assigned a clock wiring for connecting a corresponding clock terminal and a wiring for connecting a corresponding address / command terminal. Wiring for connecting address / command terminals corresponding to others is assigned to the wiring layer L6. The wiring layer L2 is mainly assigned to form a ground plane. The wiring layer L3 is assigned to a clock wiring for connecting a corresponding clock terminal, a wiring for connecting a corresponding address / command terminal, and a voltage (reference voltage) wiring of the determination level used as a reference for logical value determination of input data. . The wiring layer L4 is assigned to the formation of a power plane for the core power source of the microcomputer. The wiring layer L5 is assigned to form the power supply plane for the SDRAM interface power supply and the power supply plane for the other interface power supply.

  FIG. 11 illustrates the difference in characteristic impedance between single-ended wiring and differential wiring. The characteristic impedance shown in the figure is obtained by electromagnetic field analysis. The wiring width was 0.15 mm and the wiring interval was 0.15 mm. The characteristic impedance of the single-end data wiring formed in the surface wiring layer L1 is Z0 = 69.2Ω, and the odd mode impedance of the differential data strobe signal wiring formed in the wiring layer L1 is Zodd = 47.7Ω. The differential impedance Zdiff of the differential data strobe signal wiring has a relationship of Zdiff = Zodd × 2. The single-end data lines L_DQ and the differential strobe signal lines L_DQS and L_DQSB have the same cross-sectional shape, and the characteristic impedance of the single-end data path is larger than half the differential impedance of the differential strobe signal path. ing. In FIG. 11, ground shield lines L_GND are arranged in parallel on the left and right sides of the differential data strobe signal lines L_DQS and L_DQSB in order to further strengthen noise countermeasures. FIG. 11 also illustrates the difference in characteristic impedance between the single-ended wiring and the differential wiring formed in the inner wiring layer L3. The difference between the two characteristic impedances is the same, but the values are different.

  Compared with the pair of either the front or back wiring layer and the inner wiring layer, the pair of wiring layers on both the front and back surfaces can easily meet physical conditions such as the effective dielectric constant, and can be connected to the device. In this respect, it is possible to assign the wiring layers L1 and L6 on the front and back surfaces to the formation of the single-end data line L_DS and the differential strobe signal lines L_DQS and L_DQSB. This is suitable for equal delay.

  FIGS. 12 to 19 show specific examples of forms of forming the single-ended data path PAS_sng and the differential strobe signal path PAS_dif. When data terminals and data strobe signal terminals are connected to each other between the microcomputer 1 and the SDRAMs 2 and 3, the presence or absence of wiring layers and vias used according to the distance of the corresponding terminals is different. 12 to 19 show the connection form.

  The single end data path PAS_sng is a generic name for a path for connecting corresponding data terminals of the microcomputer and the SDRAM on the wiring board. The differential strobe signal path PAS_dif is a generic name for a path for connecting the corresponding differential data strobe signal terminals of the microcomputer and the SDRAM on the wiring board. These paths are constituted by wiring of wiring layers and necessary vias.

  The signal propagation delay time in each of the single-end data path PAS_sng and the differential strobe signal path PAS_dif is a wiring delay Ld mechanically determined from the length of the wiring formed in the wiring layer, and a delay Vd by two VIAs. Considering roughly the correction amount Id for canceling the delay difference δ due to the difference in characteristic impedance. Here, consider a case where the SDRAMs 2 and 3 and the microcomputer 1 are mounted on the wiring layer L1.

  12 and 13 show a case where the single-end data path PAS_sng of the same byte and the corresponding differential strobe signal path PAS_dif are formed in the wiring layer L1, and no via is interposed on both paths. At this time, when the delay of the differential data strobe signal lines L_DQS and L_DQSB is Ld1, and the delay of the single-end data line L_DQ is Ld2, the relationship of Ld1 = Ld2 + Id is satisfied. For example, when the length of the wiring corresponding to the correction is Lid, as illustrated in FIG. 13, when the length of the differential data strobe signal wirings L_DQS and L_DQSB is La, the length of the single end data wiring L_DQ is an error. It may be La-Lid within the range.

  When the wirings of different wiring layers L6 and vias VIA are used as shown in FIGS. 14 and 15 to connect the data terminals in the same byte using the same data strobe signal as in FIGS. 12 and 13, the relationship of Ld1 = Ld2 + Id + Vd is satisfied. The In this case, it is necessary to provide an equal length path between the single-ended data wiring layers. If the wiring length corresponding to the delay Vd due to VIA is Lvd, the length of the single-ended data wiring L_DQ of the wiring layer L6 shown in FIGS. 14 and 15 may be La-Lid-Lvd within the error range. .

  FIGS. 16 and 17 show the case where the single-byte data path PAS_sng of the same byte is formed in the wiring layer L1, and the corresponding differential strobe signal path PAS_dif is formed in the wiring layer L6 via the via VIA. At this time, when the delay of the differential data strobe signal lines L_DQS and L_DQSB is Ld1, and the delay of the single-end data line L_DQ is Ld2, the relationship of Ld1 + Vd = Ld2 + Id is satisfied. For example, assuming that the wiring length corresponding to the correction is Lid, as illustrated in FIG. 17, when the length of the differential data strobe signal wirings L_DQS and L_DQSB is Lb, the length of the single end data wiring L_DQ is an error. Lb−Lid + Lvd may be used within the range.

  In the case of using different wiring layers L6 and vias VIA as shown in FIGS. 18 and 19 to connect data terminals in the same byte using the same data strobe signal as in FIGS. 16 and 17, the relationship of Ld1 + Vd = Ld2 + Id + Vd is satisfied. The In this case, it is necessary to provide an equal length path between the single-ended data wiring layers. If the wiring length corresponding to the delay Vd due to VIA is Lvd, the length of the single-ended data wiring L_DQ of the wiring layer L6 shown in FIGS. 18 and 19 may be Lb-Lid within the error range.

  FIG. 20 shows an example of specific wiring lengths of the single end data wiring in the wiring layer L1 and the differential data strobe signal wiring in the wiring layer L6 in the case of FIG. 16 and the case of FIG. The data strobe signals DQS0 and DQSB0 and the data DQ0 to DQ7 are exemplified for one byte. Here, it is assumed that the wiring length Lid corresponding to the correction amount is 6 mm, and the wiring length corresponding to the delay amount Vd by two VIAs is Lvd = 6 mm. DQS0, DQSB0, DQ0, DQ2, DQ5, and DQ7 use the wiring layer L6 as shown in FIG. 18, and DM0, DQ1, DQ3, DQ4, and DQ6 use the wiring layer L1 as shown in FIG. The wiring lengths of DQS0 and DQSB0 in the wiring layer L6 are made longer than the DQ0, DQ2, DQ5, and DQ7 by the correction wiring length Lid = 6 mm. As for DM0, DQ1, DQ3, DQ4, and DQ6, the corrected wiring length Lid = 6 mm is canceled with the wiring length Lvd for the via. As a result, the wiring lengths of DQM0, DQ1, DQ3, DQ4, and DQ6 of the wiring layer L1 are It is substantially equal to DQS0 and DQSB0.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the memory device is not limited to the DDR2-SDRAM, and may be an SDRAM with a higher speed, for example, a DDR3-SDRAM that achieves an access speed twice that of the DDR2-SDRAM. SDRAM I / O is not limited to x16 bits. Further, the memory device may not be an SDRAM but may be another memory using a differential data strobe signal. The data processing device is not limited to the microcomputer, and may be a memory controller, an accelerator for reducing the burden on the data processor, or the like. The wiring board is not limited to a six-layer board. The present invention can also be applied to an SIP (System In Package) module substrate on which a microcomputer and a DDR2-SDRAM are mounted, in addition to a motherboard and a daughter board of a data processing system.

1 is a block diagram generally showing a semiconductor device according to the present invention. It is explanatory drawing which illustrates the terminal arrangement | sequence of the BGA package of DDR2-SDRAM based on a JEDEC standard. It is a block diagram which illustrates the interface function of the data system unit in the memory interface circuit of a microcomputer. It is explanatory drawing which shows the reason for employ | adopting arrangement | positioning of the interface function in the data system unit LBIF of FIG. 3, UBIF. It is a top view which illustrates ball electrode arrangement of a microcomputer. 1 is a block diagram generally showing a semiconductor device in which a microcomputer and an SDRAM are mounted on a wiring board with a short side of the SDRAM facing the microcomputer. FIG. 5 is a timing diagram showing a relationship between a data strobe signal and data in each of a write operation and a read operation. It is explanatory drawing which illustrates the difference in the charging / discharging speed | rate with respect to the load by the difference in characteristic impedance, etc. It is explanatory drawing which illustrates the difference in the charging / discharging speed | rate with respect to the load by each of the single end data wiring L_DQ which connects a corresponding data terminal, and the differential strobe signal wiring L_DQS which connects a corresponding data strobe signal terminal. It is sectional drawing which illustrates the longitudinal cross-section of a wiring board. It is explanatory drawing which illustrates the difference in the characteristic impedance in a single end wiring and a differential wiring. FIG. 5 is a longitudinal sectional view schematically illustrating a connection when a single-end data path of the same byte and a differential strobe signal path corresponding to the same byte are formed in the wiring layer L1, and no via is interposed on both paths. . FIG. 13 is a plan view illustrating a planar configuration of connections illustrated in FIG. 12. FIG. 13 is a longitudinal sectional view schematically illustrating connections in the case where wirings and vias of different wiring layers are used for connecting data terminals in the same byte using the same data strobe signal as in FIG. 12. FIG. 15 is a plan view illustrating the planar configuration of the connection illustrated in FIG. 14. FIG. 6 is a longitudinal sectional view schematically illustrating a connection in a case where a single-end data path of the same byte is formed in the wiring layer L1 and a corresponding differential strobe signal path is formed in the wiring layer L6 through a via. . FIG. 17 is a plan view illustrating a planar configuration of connections illustrated in FIG. 16. FIG. 17 is a longitudinal sectional view schematically illustrating connections in the case where wirings and vias of different wiring layers L6 are used for connection of data terminals in the same byte using the same data strobe signal as in FIG. 16; FIG. 19 is a plan view illustrating a planar configuration of connections illustrated in FIG. 18. FIG. 19 is an explanatory diagram showing an example of specific wiring lengths of a single-end data wiring in the wiring layer L1 and a differential data strobe signal wiring in the wiring layer L6 corresponding to the cases of FIGS. 16 and 18;

Explanation of symbols

1 Microcomputer 2,3 DDR2-SDRAM
4,5 Memory interface circuit 6 Wiring board UBPA Upper byte unit terminal group LBPA Lower byte unit terminal group DQ0 to DQ15 Data input / output terminals LDQS, LDQSB Differential data strobe signal terminal for lower byte data UDQS, UDQSB Differential for upper byte data Data strobe signal terminal UBCL Upper byte unit system PCB wiring LBCL Lower byte unit system PCB wiring CACL command and address system PCB wiring L_DQ Single-ended data wiring in the wiring layer of the wiring board L_DQS, L_DQSB Differential data strobe signal in the wiring layer of the wiring board Wiring L1, L6 Surface wiring layer L2-L5 Inner wiring layer VIA Via

Claims (13)

A semiconductor device in which an access control device capable of controlling access to a memory device and the memory device is mounted on a wiring board,
The memory device has a plurality of first data terminals to which data is input or output, and a first differential strobe that inputs or outputs a differential strobe signal that defines a transmission timing of data output from the first data terminal. A signal terminal,
The access control device has a second data terminal electrically connected to the first data terminal and a second differential strobe signal terminal electrically connected to the first differential strobe signal terminal;
The wiring board has a single-ended data path from the first data terminal to the second data terminal, and a differential strobe signal path from the first differential strobe signal terminal to the second differential strobe signal terminal;
A semiconductor device in which the differential strobe signal path is longer than the single-ended data path.   2. The single-ended data path and the differential strobe signal path have the same cross-sectional shape of the single wiring, and the characteristic impedance of the single-ended data path is larger than half of the differential impedance of the differential strobe signal path. Semiconductor device.   The wiring board has wiring layers on the front and back surfaces thereof, and the formation of the single-ended data path and the differential strobe signal path includes a wiring layer on the front and back surfaces and a via for connecting the wiring layers on the front and back surfaces to each other. 3. The semiconductor device according to claim 2, which is used. The memory device includes a plurality of bytes of the first data terminal, and the first differential strobe signal terminal in byte units.
The access control device comprises a plurality of bytes of the second data terminal and has the second differential strobe signal terminal in byte units;
The first data terminal and the first differential strobe signal terminal of the memory device and the second data terminal and the second differential strobe signal terminal of the access control device are arranged to face each other in a corresponding byte unit. The semiconductor device according to claim 3. The memory device and the access control device are mounted on one wiring layer on the front and back surfaces,
The single-ended data path of a corresponding byte includes a path formed in the one wiring layer without passing through a via, and a path formed in both wiring layers on both front and back sides via the via. 4. The semiconductor device according to 4.   When a given single-ended data path is formed in the same wiring layer as the corresponding differential strobe signal path and the same number of vias are interposed on both paths, the difference in path length between the two paths 6. The semiconductor device according to claim 5, wherein is a difference in length of wiring formed in the wiring layer.   When a predetermined single-ended data path is formed in the same wiring layer as the corresponding differential strobe signal path and no via is interposed on both paths, the difference in path length between both paths is the wiring layer. The semiconductor device according to claim 5, wherein the semiconductor device has a difference in length between wirings formed on the semiconductor device.   A predetermined single-ended data path is not formed in the same wiring layer as a corresponding differential strobe signal path, and a via is interposed in the corresponding differential strobe signal path, and a via is included in the predetermined single-ended data path. 6. The semiconductor device according to claim 5, wherein the difference between the path lengths of the two paths is a difference between the lengths of the wirings formed in the wiring layer and the difference due to the presence or absence of vias.   The predetermined single-ended data path is not formed in the same wiring layer as the corresponding differential strobe signal path, the via is not interposed in the corresponding differential strobe signal path, and the predetermined single-ended data path 6. The difference in path length between the two paths when a via is interposed is a difference in the length of a wiring formed in the wiring layer and a difference due to the presence or absence of a via, or a difference due to the presence or absence of a via. Semiconductor device. The memory device is a DDR2 or DDR3-SDRAM with a JEDEC standard terminal array;
6. The semiconductor device according to claim 5, wherein the access control device is a microcomputer connected to the DDR2 or DDR3-SDRAM. A semiconductor device in which a memory device and a data processing device capable of controlling access to the memory device are mounted on a wiring board,
The wiring board includes a single-ended data path for inputting or outputting data between the memory device and the data processing device, and a difference defining transmission timing of the data between the memory device and the data processing device. A differential strobe signal path for inputting or outputting a dynamic strobe signal;
A semiconductor device in which the differential strobe signal path is longer than the single-ended data path.   12. The data processing device outputs write data together with a data strobe signal to a memory device in a write access, and the memory device outputs read data together with a data strobe signal in response to a read access instruction by the data processing device. Semiconductor device. A semiconductor device in which a plurality of semiconductor devices are mounted on a wiring board,
The wiring board includes a single-ended signal path for inputting / outputting a signal between the plurality of semiconductor devices, and a difference for inputting / outputting a differential strobe signal defining a transmission timing of the signal between the plurality of devices. A dynamic strobe signal path,
In order to equalize the signal propagation delay in the single-ended signal path and the differential strobe signal path, the differential strobe signal path is equivalent to the length of a predetermined width of wiring formed in the wiring layer of the wiring board. A semiconductor device that is longer than the signal path.

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