KR100355240B1 - Two sides memory module sharing clock signal and wiring method thereof - Google Patents

Abstract

The present invention is described with respect to a clock sharing double-sided memory module and a wiring method thereof. The memory module is disposed to face and face each other with a module substrate having via holes and ball pads disposed on both sides thereof, a first memory chip mounted on ball pads at a front side of the module substrate, and a first memory chip at a rear side of the module substrate. And a second memory chip mounted on the pads and sharing the clock of the first memory chip. The direction of connecting the via hole of the ball pad connected to the clock of the first memory chip is the same as the direction of connecting the via hole of the ball pad connected to the clock of the second memory chip. The direction in which the via hole of the ball pad connected to the data of the first memory chip is connected is different from the direction in which the via hole of the ball pad connected to the data of the second memory chip is connected. The first and second memory chips are each configured in a mirror package, and the clock is configured in a loop manner which is inputted to the memory module and then output. Therefore, since the present invention uses a double-sided memory module sharing the clock signal, the number of clock signal lines and the number of clock pins of the memory module can be reduced.

Description

Two sides memory module sharing clock signal and wiring method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory module and a memory system, and more particularly, to a memory module sharing a clock signal, a wiring method thereof, and a memory system using the memory module.

As the performance and speed of the computer system is high, the memory system used for this requires much data processing and high speed operation. Data in the memory system is connected to the memory chips via data bus lines, which increases data throughput by widening the data bus width. Accordingly, an architecture for connecting a plurality of memory chips in parallel is used. In order to improve the data input / output speed, the data bus structure employs an impedance-matched loop bus structure. The loop bus structure refers to a structure in which data input to a memory module is outputted out of the memory module through corresponding memory chips.

On the other hand, there are clock signal lines that are as important as data bus lines for high speed operation. In particular, in the distribution of clock signals, a method for minimizing time delay with data is required. In general, source synchronous is performed so that the clock signal has the same path as the data or address / command path. Method is used. At this time, the clock signal path, the data path, and the address / command path are designed to maintain the same line impedance and line length as well as the capacitive load of each memory chip pin.

1 is a diagram illustrating a conventional memory module 100. The memory module 100 includes a plurality of memory chips 101, 102, 103, and 104, and the data signal DQ and the clock signal DCLK are input and output to the memory chips 101, 102, 103, and 104, respectively. The data signal DQ and the clock signal DCLK have a loop structure which is inputted to the memory module 100 and then outputted out of the memory module 100 again. Therefore, the number of pins connected to the clock signal DCLK among the pins of the memory module 100 is required as many as the number of the memory chips 101, 102, 103, and 104. In addition, the number of clock bus lines in the memory module 100 may be as many as the number of memory chips 101, 102, 103, and 104.

However, when the number of memory chips 101, 102, 103, and 104 mounted on the memory module 100 increases, the number of clock bus lines that need to be driven from the viewpoint of the system as well as the memory module 100 increases. Specifically, at least 64 clock signals should be present in a memory module having a small data input / output width, for example, a × 4 memory chip having a x64 data bus, and in the case of a loop bus method, an input clock signal and an output clock signal may be separately Since present, 128 clock signal lines are needed. In addition, the addition of a line necessary for the grounding of the clock signal line increases the burden on the system for clock signal distribution, thereby increasing the system configuration price.

Since the clock signal is a high frequency signal, the clock signal serves as a representative electromagnetic interference (EMI) noise source. Therefore, the increase in the clock signal line is a factor that worsens the EMI problem.

Therefore, a memory module capable of reducing the total number of clock signal lines is required.

An object of the present invention is to provide a double-sided memory module that shares a clock signal.

Another object of the present invention is to provide a wiring method of the memory module.

In order to more fully understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.

1 is a diagram illustrating a conventional memory module.

2 is a diagram illustrating a memory module according to an exemplary embodiment of the present invention.

3 is a diagram illustrating a mirror package type.

4 is a diagram illustrating a wiring method of a clock signal pin of the memory module of FIG. 2.

FIG. 5 is a diagram illustrating a wiring method of data pins of the memory module of FIG. 2.

FIG. 6 is a diagram illustrating a single rank module using the memory module of FIG. 2.

FIG. 7 is a diagram illustrating a memory system including the single rank module of FIG. 6.

FIG. 8 is a diagram illustrating a double rank module using the memory module of FIG. 2.

FIG. 9 is a diagram illustrating a memory system including the double rank module of FIG. 8.

FIG. 10 is a diagram illustrating a wiring method of the double rank module of FIG. 8.

In order to achieve the above object, a memory module according to an embodiment of the present invention includes a module substrate having via holes and ball pads disposed on both sides thereof, a first memory chip mounted to ball pads on a front surface of the module substrate, and a module substrate And a second memory chip disposed to face the first memory chip on a rear surface of the rear panel, mounted on the ball pads, and sharing a clock of the first memory chip.

The direction of connecting the via hole of the ball pad connected to the clock of the first memory chip is the same as the direction of connecting the via hole of the ball pad connected to the clock of the second memory chip. The direction in which the via hole of the ball pad connected to the data of the first memory chip is connected is different from the direction in which the via hole of the ball pad connected to the data of the second memory chip is connected. The first and second memory chips are each configured in a mirror package, and the clock is configured in a loop manner which is inputted to the memory module and then output.

According to another embodiment of the present invention, a memory module includes a module substrate having via holes and ball pads disposed on both sides thereof, a first memory chip mounted on ball pads in front of the module substrate, and a first memory chip facing each other. A second memory chip disposed on the back side of the module substrate and mounted on the ball pads and sharing the clock of the first memory chip, and a third mounted on the ball pads on the front side of the module substrate and arranged side by side with the first memory chip. And a fourth memory chip disposed on a rear surface of the module substrate facing each other and facing the third memory chip, mounted on ball pads, and sharing a clock of the third memory chip.

The ball pads connected to the clocks of the first and third memory chips are connected to the via holes in the same direction as the ball pads connected to the clocks of the second and fourth memory chips, respectively. The direction in which the ball pads respectively connected to the data of the first and third memory chips are connected to the via holes is different from the direction in which the ball pads respectively connected to the data of the second and fourth memory chips are connected to the via holes. Each of the first to fourth memory chips is configured as a mirror package, and the clock is configured in a loop manner which is input to the memory module and then output.

In the wiring method of the memory module of the present invention in order to achieve the above object, the memory module is a module substrate, ball pads arranged on the front and back of the module substrate, the left side of the ball pads on the front and back of the module substrate First via holes disposed on the upper side and selectively connected to the ball pads, second via holes disposed on the lower left side of the ball pads on the front and rear surfaces of the module substrate and selectively connected to the ball pads, A first memory chip mounted on the ball pads of the front surface and a second memory chip mounted on the ball pads of the rear surface of the module substrate. In the clock wiring method, a ball pad connected to a clock of a first memory chip is connected to a first via hole, and a ball pad connected to a clock of a second memory chip is connected to a first via hole. In the data wiring method, a ball pad connected to data of a first memory chip is connected to a first via hole, and a ball pad connected to data of a second memory chip is connected to a second via hole.

According to the present invention as described above, since the double-sided memory module sharing the clock signal is used, the number of clock signal lines can be reduced. As a result, the number of clock pins of the memory module can be reduced.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. For each figure, like reference numerals denote like elements.

2 is a diagram illustrating a memory module 200 sharing a clock signal according to an embodiment of the present invention. The memory module 200 is a double-sided memory module, in which first and third memory chips 201 and 203 are disposed on a front surface thereof, and second and fourth memory chips 202 and 204 are disposed on a rear surface thereof. The first memory chip 201 and the second memory chip 202 are disposed to face each other with the memory module substrate interposed therebetween, and the third memory chip 203 and the fourth memory chip 204 also interpose the memory module substrate. Are placed so as to face each other. The first memory chip 201 and the second memory chip 202 are configured as mirror packages in which the pin configurations of the package are symmetrical to each other.

3 is a diagram illustrating an example of a mirror package. The first memory chip 201 and the second memory chip 202 represent a back side of a package of a ball grid array (BGA) type. For convenience of explanation, the pins arranged on the side of the package will be described with a series of numbers. Looking at the first memory chip 201, first, second, ... , In the order of 6 and from the bottom of the right side to the top 7, 8,... The pins are arranged in the order of 12. On the other hand, the second memory chip 202 has the first, second, ... In the order of 6 and from the bottom left side to the top 7, 8,.. The pins are arranged in the order of 12. Thus, the first memory chip 201 and the second memory chip 202 are configured in a mirror type package.

When the first memory chip 201 and the second memory chip 202 are disposed to face each other with the memory module substrate interposed therebetween as shown in FIG. 2, the first pin of the first memory chip 201 is a second memory chip. Pin 1 of the memory chip 202, pin 2 of the first memory chip 201, pin 2 of the second memory chip 202; And, pin 12 of the first memory chip 201 meets at the same position as pin 12 of the second memory chip 202. Here, suppose that pin 1 of the first and second memory chips is a clock signal DCLK pin and pin 2 is a data DQ pin.

4 is a diagram illustrating a shared wiring method of a clock signal DCLK pin. Referring to this, the ball pad 1 and the via holes A and B of the first memory chip 201 are formed on the front surface 200 of the memory module, and the second memory is formed on the rear surface 200 ′ of the memory module. The ball pad 1 'of the chip 202 and the via holes A' and B 'are disposed. The ball pad 1 on the front side and the ball pad 1 'on the rear side are connected to each other through via holes A-A' and B-B '. The ball pad 1 of the front side is connected to the second via hole B, and the ball pad 1 'of the rear side is connected to the second via hole B'. The front ball pad 1 and the rear ball pad 1 'are connected to each other through the second via holes B-B' so that the clock signal DCLK pin and the clock signal DCLK pin of the back are connected. Are connected to each other. Thus, as shown in FIG. 2, the clock signals DCLK of the first memory chip 201 and the second memory chip 202 are shared with each other.

On the other hand, the isolation wiring method of the data (DQ) pin is shown in FIG. 2, the ball pad 2 of the first memory chip 201 of the front surface of the memory module 200 is connected to the first via hole A ′, and the second memory chip of the rear surface 200 ′ of the first memory chip 201. The second ball pad 2 ′ of 202 is connected to the second via hole B ′. Thus, the ball pad 2 on the front side is connected to the wiring through the first via holes A-A ', and the ball pad 2' on the rear side is connected to the wiring through the second via holes B-B '. Therefore, the data DQ pins are separated from each other. As a result, the data DQ of the first memory chip 201 and the data DQ of the second memory chip 202 are inputted and outputted without collision.

FIG. 6 illustrates a single rank module 600 as a memory module that is substantially the same as the memory module 200 of FIG. 2. The single rank module 600 has a rank0 structure, and the rank refers to a structure in which data input and output by one address is provided by a group of memory chips 601, 602, 603, and 604. The clock signal DCLK of the first memory chip 601 and the second memory chip 602 is shared, and the first data DQ line is connected to the first memory chip 601 on the front side, and the second data line ( DQ ′) is connected to the second memory chip 602. Similarly, the clock signal DCLK of the third memory chip 603 and the fourth memory chip 604 are shared and the data lines DQ and DQ 'are separated.

FIG. 7 is a diagram illustrating a memory system including the single rank module of FIG. 6. In the memory system 700, data (DQ) bus lines 710 and 740, clock (DCLK) bus lines 720 and 750, and a command / address (CMD / ADDR) bus line 730 are disposed, and a first single rank module is provided. 701 and a second single rank module 702 are included. Data is input and output to the first single rank module 701 through first and second data lines 760 and 760 'connected to the data bus lines 710 and 740, respectively. The command / address line 770 connected to the command / address bus line 730 is disposed in the horizontal direction of the first single rank module 701 and connected to each memory chip. Here, the clock DCLK lines provided to the first single rank module are inputted and outputted in the same manner as the data lines 760 and 760 '. Since the line wiring of the second single rank module 702 is substantially the same as the first single rank module 701, a detailed description thereof will be omitted in order to avoid duplication of description.

8 is a diagram illustrating a double rank module. The double rank module 800 has two ranks (rank0, rank1) structure, the first rank (rank0) and the second rank (rank1) has the effect of increasing the data density (density). The data density refers to the number of data that can be stored in a group of memory groups. The double rank module 800 is compared with the single rank module 600 of FIG. Because data can be stored in rank1), it has twice the data density. At this time, since the number of data input / output through the first rank (rank0) and the second rank (rank1) is the same as the number of data input / output through the first rank (rank0), the band whistle of the double rank module is single Same as the band whisker of the rank module.

The first memory chip 801 and the second memory chip 802 of the first rank (rank0) are disposed to face each other with the module substrate therebetween and share a clock DCLK line. The third memory chip 803 and the fourth memory chip 804 of the second rank rank1 are disposed to face each other with the module substrate interposed therebetween, and share a clock DCLK line. The clock DCLK of the first rank 0 and the clock of the second rank 1 are connected to each other. Thus, the clock DCLK input to the memory module 800 is output through the first rank 0 and the second rank 1 and then out of the memory module 800.

The first data DQ input and output in the first rank 0 is connected to the first memory chip 801 and the third memory chip 803, that is, the memory chips 801 and 803 disposed on the front surface of the memory module 800. Input and output to and from the memory module 800. The second data DQ ′ is connected to the second memory chip 802 and the fourth memory chip 804, that is, the memory chips 802 and 804 disposed on the rear surface of the memory module 800, and then out of the memory module 800. Input and output

The fifth to eighth memory chips 805 to 808 are configured as described above, and the number of data DQ and DQ ′ input and output from the first to fourth memory chips 801 to 804 and the fifth to eighth memory chips 805 to 808 are also included. The sum of the numbers of data DQ and DQ ′ input and output from the eighth memory chips 805 to 808 becomes a band whistle of the double rank module.

FIG. 9 illustrates a memory system configured with the double rank module of FIG. 8. The memory system 900 is almost identical to the memory system 700 of FIG. 7. However, there is only a difference in using the double rank module described above. Therefore, specific description is omitted to avoid duplication of description.

FIG. 10 is a diagram schematically illustrating a wiring diagram of the double rank module of FIG. 8. The wiring diagram is composed of multiple layers, and shows an example of eight layers. The first layer represents the top layer, the third and sixth layers represent the intermediate layers INNER1 and INNER2, and the eighth layer represents the bottom layer. The first layer and the eighth layer are shown to be wired by the wiring method described with reference to FIGS. 4 and 5, and the third and sixth layers show a connection relationship between the ranks.

Therefore, the present invention uses a double-sided memory module that shares the clock signal, thereby reducing the number of clock signal lines. As a result, the number of clock pins of the memory module can be reduced.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

The present invention described above uses a double-sided memory module that shares a clock signal, thereby reducing the number of clock signal lines. As a result, the number of clock pins of the memory module can be reduced.

Claims (12)

A module substrate having via holes and ball pads disposed on both surfaces thereof; A first memory chip mounted on the ball pads on a front surface of the module substrate; And And a second memory chip disposed on a rear surface of the module substrate so as to face the first memory chip, mounted on the ball pads, and sharing a clock of the first memory chip. The method of claim 1, wherein the memory module The direction in which the via hole of the ball pad connected to the clock of the first memory chip in the front side of the module substrate is the same as the direction in which the via hole of the ball pad connected with the clock in the rear of the module substrate is connected. Memory module. The method of claim 1, wherein the memory module A direction in which the via hole of the ball pad connected to the data of the first memory chip is connected to the via hole of the ball pad connected to the data of the second memory chip at the rear of the module substrate; Memory module, characterized in that the other. The memory device of claim 1, wherein the first and second memory chips Memory modules, characterized in that each consisting of a mirror package. The method of claim 1, wherein the memory module And the clock is inputted to the memory module and configured to be output in a loop manner. A module substrate having via holes and ball pads disposed on both surfaces thereof; A first memory chip mounted on the ball pads on a front surface of the module substrate; A second memory chip disposed on a rear surface of the module substrate so as to face the first memory chip, mounted on the ball pads, and sharing a clock of the first memory chip; A third memory chip mounted on the ball pads and disposed in parallel with the first memory chip on a front surface of the module substrate; And And a fourth memory chip disposed on a rear surface of the module substrate to face the third memory chip, mounted on the ball pads, and sharing a clock of the third memory chip. The method of claim 6, wherein the memory module The ball pads connected to the clock holes of the first and third memory chips on the front side of the module substrate are connected to the via holes, respectively, and are connected to the clocks of the second and fourth memory chips on the back side of the module substrate. And the ball pads are connected to the via holes in the same direction. The method of claim 6, wherein the memory module The ball pads connected to data of the first and third memory chips on the front surface of the module substrate are connected to the via holes, respectively, and the balls connected to data of the second and fourth memory chips on the back surface of the module substrate. And a pad different from a direction in which pads are connected to the via hole. The method of claim 6, wherein the first to fourth memory chips Memory modules, characterized in that each consisting of a mirror package. The method of claim 6, wherein the memory module And the clock is inputted to the memory module and configured to be output in a loop manner. In the wiring method of a memory module, the memory module A module substrate; Ball pads arranged on the front and rear surfaces of the module substrate; First via holes disposed on front and rear surfaces of the module substrate, the first via holes being disposed on upper left sides of the ball pads and selectively connected to the ball pads; Second via holes disposed on the front and rear surfaces of the module substrate, the second via holes being disposed on the lower left side of the ball pads and selectively connected to the ball pads; A first memory chip mounted to the ball pad on the front surface of the module substrate; And A second memory chip mounted to the ball pad on the rear surface of the module substrate, The ball pad connected to the clock of the first memory chip is connected to the first via hole, and the ball pad connected to the clock of the second memory chip is connected to the first via hole. Way. The method of claim 11, wherein the wiring method of the memory module is performed. The ball pad connected to the data of the first memory chip is connected to the first via hole, and the ball pad connected to the data of the second memory chip is connected to the second via hole. Way.